JP2002261027A - GaN-FAMILY SEMICONDUCTOR BASE AND ITS MANUFACTURING METHOD - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the structure of a GaN-family semiconductor base where dislocation density is reduced, and to provide a method for manufacturing the structure. SOLUTION: An etch pit P is formed on an upper surface 1a of a first GaN- family crystal layer 1, and a second GaN-family crystal layer 2 is formed on the upper surface 1a so that the etch pit becomes a cavity, and/or is filled with a GaN-family crystal, thus controlling the propagation of a dislocation line by the etch pitch, hence reducing dislocation of an upper layer low.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a GaN-based semiconductor substrate and a method for producing the same, and more particularly, to a structure of a substrate useful for reducing dislocations of a crystal and a method for producing the substrate.

[0002]

2. Description of the Related Art A field for crystal growth of a GaN-based semiconductor material
In this case, this type of material has no
Sapphire, SiC, spinel, recently Si
Is used. However,
Described the GaN-based crystal grown on such a crystal substrate.
Due to the lack of lattice matching, 10^TenPieces/
cm ^TwoThere are also dislocations. In recent years, high-brightness light emitting
Iodine and semiconductor lasers have been realized,
It is desired to reduce the dislocation density in order to improve the property.

[0003]

As a method for reducing the dislocation density, there is, for example, a selective growth method (lateral growth method). This method uses a buffer layer on the crystal substrate (as it is in the case of a GaN crystal substrate)
In vapor-phase growth of a GaN-based crystal, a partial mask (made of a material that cannot substantially grow a GaN-based crystal) is provided on a crystal substrate and selectively grown, whereby a crystal in a lateral direction is formed on the upper surface of the mask. In this method, high-quality crystals with a reduced dislocation density are grown by performing growth.
0-312971).

However, in the above method, it is necessary to form a mask layer on the GaN substrate, and there is a problem that the number of steps such as a layer forming step using a mask material and a step of transferring a pattern such as stripes is extremely increased. Was. A material commonly used as a mask layer material is S
Since it is made of iO ₂ or the like, if a GaN-based crystal layer is grown thereon, there is a problem of so-called auto-doping contamination in which a Si component moves into the crystal growth layer. Furthermore, when a GaN-based material (for example, AlGaN) containing an Al component is grown on the SiO ₂ mask layer, crystal growth also occurs from the upper surface of the mask layer, and the lateral growth method itself cannot be effectively performed. There was also.

On the other hand, as an attempt to solve the above problem, a lateral growth method without using a mask has been proposed. This method is applied to a crystal substrate in which a buffer layer and a GaN layer are formed on a base substrate made of SiC.
This is a method in which stripe grooves are formed from the upper surface of the substrate to the SiC substrate to leave convex portions connected in a band shape, and a crystal is grown from a GaN layer located above the convex portions (MRS 1998 Fall Meeting Meeting) G3.38). Also, a sapphire substrate can be used as a base substrate,
The method is also disclosed (for example, see JP-A-11-19).
No. 1659). In addition, concave and convex parts are processed on the substrate,
A method of suppressing propagation of dislocations by growing a gallium nitride based semiconductor so as to form a cavity in a concave portion
-106455).

[0006] According to these methods, it is possible to laterally grown without the SiO ₂ mask, it is possible to solve the various problems caused by the use of SiO ₂ mask described above.

However, all of the above-described lateral growth methods using no mask require a step of transferring a pattern such as a stripe or the like in order to leave a projection serving as a growth starting point in a band shape (ridge line shape). There is a problem that the number of steps increases.

An object of the present invention is to solve the above problems and to provide a new structure of a GaN-based semiconductor substrate having a reduced dislocation density and a method of manufacturing the same.

[0009]

SUMMARY OF THE INVENTION The present invention has the following features. (1) Second GaN on the first GaN-based crystal layer
A GaN-based semiconductor substrate having a stacked structure formed by growing a system-based crystal layer, wherein the top surface of the first GaN-based crystal layer is
Etch pits are formed, and the second Ga
A GaN-based semiconductor substrate, wherein the etch pits are in a hollow state and / or filled with GaN-based crystals by growing an N-based crystal layer.

(2) Etch pits are formed again on the upper surface of the second GaN-based crystal layer, or the second Ga
Another GaN-based crystal layer is grown on the upper surface of the N-based crystal layer, etch pits are formed again on the upper surface, and the re-formed etch pits are in a cavity state and / or a state filled with GaN-based crystals. The GaN-based crystal layer according to the above (1), wherein a further GaN-based crystal layer is grown, and by this repetition, two or more GaN-based crystal layers having an upper surface on which etch pits are formed are stacked. Based semiconductor substrate.

(3) The G according to the above (1) or (2), wherein the etch pits are present at a density of 1 × 10 ⁶ / cm ² or more on the upper surface on which the etch pits are formed.
aN-based semiconductor substrate.

(4) The GaN-based semiconductor substrate according to the above (1) or (2), wherein the etch pit has a diameter of 100 nm or more.

(5) An etch pit is formed on an upper surface of the first GaN-based crystal layer, and the etch pit is formed on the upper surface such that the etch pit is in a hollow state and / or is filled with a GaN-based crystal. A method for producing a GaN-based semiconductor substrate, comprising a step of growing a second GaN-based crystal layer.

(6) Etch pits are formed again on the upper surface of the second GaN-based crystal layer, or
Another GaN-based crystal layer is grown on the upper surface of the system-crystal layer, and etch pits are formed again on the upper surface, and the re-formed etch pits are in a cavity state and / or a state filled with GaN-based crystals. (5) The manufacturing method according to the above (5), which has a repeated step of growing a further GaN-based crystal layer.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A GaN-based semiconductor substrate according to the present invention will be described in detail along with a manufacturing method. FIG. 1 is a cross-sectional view for explaining a crystal growth state of a GaN-based semiconductor substrate according to the present invention. As shown in FIG.
-Based semiconductor substrate is a first GaN-based crystal layer (hereinafter, referred to as a GaN-based crystal layer).
It includes a stacked structure formed by growing a second GaN-based crystal layer (hereinafter abbreviated as “second layer”) 2 on a “first layer” 1. In the example shown in the figure, a crystal substrate S serving as a base for starting initial crystal growth is used as the lowermost layer, and the first layer 1 is formed thereon. The first layer 1 has an etch pit P formed on the upper surface,
This etch pit P is formed by the growth of the second layer 2 as shown in FIG.
Is in a hollow state as shown in (a), or
As shown in FIG. 1B, the second layer is filled with the GaN-based crystal. The state of the cavity / fill of these etch pits changes depending on the growth condition of the second layer, as described later, and among a large number of etch pits formed on the upper surface of the first layer, some are cavities and some are. The object may be filled with crystals.

In order to manufacture the GaN-based semiconductor substrate having such a laminated structure, first, as shown in FIG. 1, the upper surface of the first layer 1 is etched to form etch pits P. The second layer may be grown on the upper surface such that the pits are in a hollow state and / or a filled state.

"GaN-based" and "GaN-based semiconductor"
Al _x Ga _1-xy In _y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0
≦ x + y ≦ 1). As the composition ratios x and y in the above formula are changed, GaN, A
lGaN (eg, Al _0.2 Ga _0.8 N), InGaN
(For example, In _0.4 Ga _0.6 N). In the present invention, the first layer and the second layer are obtained by crystal-growing a GaN-based semiconductor represented by the above formula, and may have the same composition or different compositions. The first layer and the second layer referred to in the present invention may be located at any part in the stacked body composed of the GaN-based crystal layer.

As shown in FIG. 1, when a crystal substrate S serving as a base for starting initial crystal growth is used, such a crystal substrate may be sapphire (C-plane, A-plane,
R surface), SiC (6H, 4H, 3C), GaN, Al
Examples include N, Si, spinel, ZnO, GaAs, and NGO, but are not limited thereto, and other materials may be used as long as the first layer can be obtained. The plane orientation of the base crystal substrate is not particularly limited,
Further, a just substrate or a substrate having an off angle may be used.

In order to improve the crystal quality of the first layer, a buffer layer for lattice matching may be formed on the base crystal substrate, or a GaN-based crystal thin film may be grown. May be. For example, a substrate in which a GaN-based semiconductor of several μm is epitaxially grown on a sapphire substrate or the like is used.

Next, the etch pit formed on the surface of the first layer will be described in detail. It is known that when a surface of a crystal including a crystal defect such as a dislocation is etched, a small pit (a pit) is formed at the position of the defect. This depression is an etch pit. For example, in the literature (Proc. Int. Works
hop on Nitride Semiconductors IPAP Conf.Series 1
pp. 536), it has been reported that etch pits formed by etching with HCl gas correspond to dislocations. Conventionally, an etch pit has been used as a measuring means for examining the number and distribution of dislocations on a crystal surface (etch pit method). That is, in the related art, forming an etch pit is a kind of destructive test performed on a sample to check the quality of a crystal. On the other hand, in the present invention, as described in detail below, a process of forming an etch pit is incorporated in the manufacturing process of the crystal base material, and by actively including the etch pit inside the crystal base material itself, Lower dislocations in the upper layer that grows over the etch pits have been achieved.

In the present invention, first, the emission intensity of the LED and
We note that there is a strong correlation with the etch pit density. For example, on a sapphire substrate, an AlN low-temperature buffer layer, an n-GaN contact layer, an n-AlGa
Forming an N cladding layer (Al composition 10%), an InGaN light emitting layer (In composition 7%), a p-AlGaN cladding layer (Al composition 10%), and a p-GaN contact layer,
An epi-wafer having a D structure was obtained. About this wafer,
After measuring the light emission intensity of the light emitting layer by PL measurement, an etch pit was formed by dry etching. When the relationship between the PL emission intensity and the etch pit was examined, it was found that there was a correlation as shown in FIG.

When a certain density of etch pits appears on the upper surface of the crystal layer, dislocation lines having a density equal to or higher than the density of the etch pit always exist in the crystal layer. Since dislocation lines propagate from the lower layer to the upper layer, similar dislocation lines exist in the light emitting layer. On the other hand, it is known that dislocations in the light emitting layer act as non-light emitting centers. Therefore, it is considered that the magnitude of the etch pit density of the surface p-GaN layer in the device structure corresponds to the magnitude of the dislocation density in the light emitting layer, and has a strong correlation with the PL intensity.

In the present invention, attention is paid to the fact that when the surface of a GaN-based crystal is etched, an etch pit is formed in a portion where a dislocation exists, and the etch pit is formed as shown in FIG. Thus, dislocation lines (m1, m
2, m3) stops propagating upward, or as shown in FIG. 1 (b), dislocation lines (m1, m2, m
The propagation direction in 3) is changed there, and it is gathered into one dislocation line m4 to lower the dislocation in the upper layer.

The fact that the dislocation density of the upper layer is reduced by the etch pit will be described in more detail. The dislocation existing in the first layer is generated, for example, at the interface with the first crystal substrate S, and propagates upward as a dislocation line as indicated by a broken line m drawn in the stacked body in FIG. When etching the upper surface of the first layer containing dislocation lines to form etch pits,
As shown in FIGS. 1A and 1B, the dislocation line m1 is located at the center of the etch pit. The etch pits and dislocation lines do not always correspond one-to-one at the center,
Dislocation lines may be located on the slopes of the etch pits as indicated by m2 and m3 in FIG.

When the second layer is regrown on the first layer on which the etch pits are formed, depending on the growth conditions,
As shown in FIG. 1A, the second layer 2 grown from the upper surface 1a of the first layer grows not only in the thickness direction but also in the lateral direction so as to cover the etch pits P. Represents that the etch pit P is completely covered and remains as a cavity as shown in FIG. As a result, the dislocation lines m1, m2, and m3 are stopped from propagating to the second layer by the etch pits formed due to the existence of the dislocation lines m1, m2, and m3, and the second layer is reduced in dislocation. Alternatively, depending on the growth conditions, as shown in FIG. 1B, the second layer may grow so as to fill the inside of the etch pit. In such a case, the concave surface of the etch pit becomes a regrowth interface, and the dislocation lines m1, m2, and m3 change the propagation direction at the interface (especially, the slope of the etch pit), and gather at the vicinity of the center of the etch pit. The dislocation line m4 is formed, and the periphery thereof is reduced in dislocation. Also in this case, the number of the dislocation lines m1, m2, and m3 that propagate to the second layer is reduced by the etch pits formed due to the existence of the dislocation lines m1, m2, and m3. Become.

As described above, in the present invention, the etch pit, which has been conventionally used exclusively as a destructive inspection means for confirming the existence of dislocations, is applied to crystal growth, and is actively incorporated into a crystal base material. It is applied to dislocation line propagation control.
As a result, only by etching the upper surface of the first layer under predetermined conditions, etch pits are automatically and selectively generated in response to countless dislocations randomly present on the upper surface. The propagation to the above layers is effectively suppressed.

FIG. 3 shows an SEM image of an etch pit that appears when the C plane of the GaN crystal is dry-etched.
In the image of FIG. 3, the shape of the etch pit is a conical depression, but depending on the etching conditions, various shapes such as a hexagonal pyramid, a partially spherical shape, a slash-like shape, and a composite of them appear.

As an etching method for forming an etch pit, any method can be used as long as an etch pit corresponding to a dislocation can be formed, such as gas phase etching using a gas such as HCl, phosphoric acid, sulfuric acid, KOH, or the like. Wet etching using an etching solution, dry etching using a chemical / physical reaction at a gas-solid interface such as Cl ₂ and BCl _3, and the like.

As described above, it is difficult to uniquely express the size of the etch pit due to the various shapes of the entire etch pit as described above. However, according to the present invention, the upper surface of the crystal layer on which the etch pit is to be formed ( The size is represented by the diameter of the opening portion of the etch pit on the C plane in general crystal growth). If the opening is not circular, the maximum length is the diameter. In the case where a plurality of etch pits are connected, the shape of each etch pit is estimated,
What is necessary is just to check the caliber. The diameter of the etch pit changes depending on the etching conditions, for example, the etching time.
m to over 10 μm,
In order to obtain the effect of reducing the dislocation density, the thickness is preferably 10 nm or more, more preferably 100 nm or more, and particularly 1 μm or more, the effect of reducing the dislocation density becomes more remarkable.

Various shapes of the etch pits appear depending on the etching conditions, and any shape has an effect of reducing the dislocation density. Among them, the hexagonal pyramid (concave shape) having a facet surface is an etch pit. Even if the pits are regrown to fill the crystal, as shown in FIG. 1B, the plurality of dislocation lines bend more effectively on the facet surface, coalesce, and the dislocation density can be reduced. Therefore, it is a preferable shape.

In the present invention, G is actively used by using etch pits.
The first layer is to lower the dislocation of the aN-based crystal layer.
On the upper surface, an etch pit having a diameter of 100 nm or more is 1 ×
10 ^FourPieces / cm^TwoA crystal containing dislocations as described above
Then, the effect of reducing the dislocation density becomes remarkable.
× 10⁶Pieces / cm^TwoAbove, furthermore, 1 × 10⁷Pieces / cm^Two
For crystals of the above-mentioned quality, the dislocation density
The reduction effect becomes extremely remarkable.

In the above description, the dislocation density of an object in which the usefulness of the present invention is remarkable is expressed by the density of etch pits. The number and size of the etch pits differ depending on the etching method. It is difficult to make a one-to-one correspondence. On the other hand, as a method of observing dislocations on the crystal surface,
A method using cathodoluminescence is known,
It is said that the dark spot observed by the method can obtain a number close to one-to-one with the dislocation. As a representative value, if the number of etch pits formed by dry etching is about 1/100 of the number of dark spots observed by cathodoluminescence, the first layer is If the crystal has such a quality that a dark spot of 1 × 10 ⁶ / cm ² or more is observed, the effect of reducing the dislocation density becomes remarkable, but 1 × 10 ⁸ / c 2
It can be said that the effect of reducing the dislocation density according to the present invention is extremely remarkable for a crystal having a quality of at least m ² , especially at least 1 × 10 ⁹ / cm ² .

In the GaN-based semiconductor substrate according to the present invention, it is naturally possible to observe the etch pit in detail during the manufacturing process, but even after the second layer or more is formed and the substrate is completed, It is possible to confirm the fact that etch pits were formed on the upper surface of the first layer existing inside the base material and to evaluate the diameter of the etch pits. For example, as shown in FIG. 1 (a), a cross section of an object in which etch pits are clearly left as cavities and those in which an etch pit shape is clearly left as an interface are observed by SEM (scanning electron microscope). Can be easily determined from the confirmation of the existence of the etch pit cavity by the method. Further, as shown in FIG. 1B, the etch pits are filled with the crystal of the second layer, and the first layer GaN / the second layer Ga
The regrowth interface of the same composition, such as N, can be determined by SEM observation of the cross section, and it can be seen that etch pits have been formed. According to TEM (transmission electron microscope) observation of the cross section, the regrowth interface having an etch pit shape can be easily identified from the discontinuity of the lattice. When regrowth is performed after providing an interruption time during crystal growth, the regrowth interface remains in the crystal, and the existence of the regrowth interface (and the fact that the regrowth interface was interrupted) can be confirmed by the above-described method or the like.
Therefore, in a GaN crystal laminated structure such as a crystal base material or a light emitting element / device, those in which an etch pit-shaped regrowth interface remains are those obtained by forming an etch pit on the crystal surface and then performing regrowth. It can be concluded that the GaN-based semiconductor substrate and the manufacturing method according to the present invention are used.

In the above, the case where the etch pit is formed on the upper surface of the first layer and the second layer is regrown thereon has been described, but the same process may be further repeated. For example, as shown in FIG. 4, an etch pit P2 is formed directly on the upper surface of the second layer 2, or another GaN-based crystal layer is grown and formed on the second layer, and the etch pit P is formed on the upper surface again. Is formed, and a further GaN-based crystal layer 3 is grown thereon. By this repetition, Ga having an upper surface on which an etch pit is formed is formed.
Two or more N-based crystal layers are multiply stacked, and the dislocations that propagate are reduced each time the surfaces on which the etch pits are formed are stacked, so that a higher quality crystal can be obtained.

The method of growing a GaN-based crystal layer is based on HV
PE, MOVPE (MOCVD), MBE and the like are preferable. When forming a thick film, the HVPE method is preferable, but when forming a thin film, the MOVPE method or the MBE method is preferable.

Whether the crystal growth is such that the second layer covers the etch pits and leaves the etch pits as cavities, or whether the crystal growth is to fill the etch pits, depends on the growth conditions (gas type, (Growth pressure, growth temperature, etc.). For example, when the growth temperature of the second layer is increased, lateral growth is promoted, and the etch pits tend to become hollow. Even when N ₂ is used as an atmosphere gas during growth, the lateral growth is accelerated, and the etch pits tend to become hollow. Further, in order to perform crystal growth so as to fill the inside of the etch pit, it is only necessary to select conditions opposite to the case of forming a cavity, such as growing the second layer at a low temperature. In addition to these, other growth methods such as MOVPE for the first layer and HVP for the second layer
A combination of different growth methods such as growth by the E method may be performed. Although it has been shown that the formation of cavities can be controlled by the growth conditions as described above, any method can be used depending on the purpose as long as the effects of the present invention are obtained.

[0037]

EXAMPLE 1 A C-plane sapphire substrate having a diameter of 2 inches was mounted on a MOVPE apparatus, heated to 1100 ° C. in a hydrogen atmosphere, and subjected to thermal etching. Thereafter, the temperature was lowered to 500 ° C., and trimethylgallium (hereinafter referred to as TM)
G) Ammonia was flowed as an N source to grow a GaN low-temperature buffer layer. Next, the temperature was raised to 1000 ° C., TMG and ammonia were flowed as raw materials, silane was flowed as a dopant, and n-type Ga was used as the first layer in the present invention.
An N layer was grown 4 μm.

The laminate was taken out of the MOVPE apparatus, and the upper surface of the first layer was observed by cathodoluminescence.
^{It was 9} pieces / cm ^-2 .

Further, this laminate is subjected to RIE (Reactive
Ion Etching) 1/100 of dark spot density observed by cathodoluminescence
The upper surface of the first layer was etched under such etching conditions that the average diameter of the etch pits was 3.5 μm. When the density of the etch pits on the upper surface of the first layer was measured, it was 1.0 × 10 ⁷ / cm ⁻² .

The laminated body having the etch pits formed on the upper surface of the first layer was mounted again on the MOVPE apparatus, TMG, ammonia and silane were flown, and the n-type GaN layer was regrown by 3 μm.
The GaN-based semiconductor substrate according to the present invention was obtained as the second layer according to the present invention. The growth conditions of the second layer were selected such that the growth rate in the lateral direction was promoted and the etch pits remained as cavities.

For comparison, the MO layer was grown after the first layer was grown.
The sample was taken out of the VPE apparatus, but was not etched, but was returned to the MOVPE apparatus, and a comparative sample in which the second layer was regrown was also prepared. The conditions other than the presence or absence of the etching are the same for both the example sample and the comparative example sample. The upper surfaces of the second layers of both samples were observed by cathodoluminescence, and the dark spot density was measured. The measurement results are shown in Table 1 together with the dark spot density on the upper surface of the first layer.

[0042]

[Table 1]

As shown in Table 1, in the example product, when the upper surface of the first layer and the upper surface of the second layer were compared, the dark spot density was reduced. Is clear. On the other hand, in the comparative example product in which no etch pits were formed on the upper surface of the first layer, while using the first layer having the same quality as the example product, the dark spot density of the second layer was lower than that of the first layer of the example product. There is almost no change when compared.

Example 2 In this example, the GaN-based semiconductor substrate was manufactured in the same manner as in Example 1, except that the average diameter of the etch pits on the upper surface of the first layer was 2 μm. When the dark spot density on the upper surface of the second layer of the obtained example sample was measured, it was 6.8 × 10 ⁸ / cm ⁻² . From this, it was found that the diameter of the etch pit formed in the first layer greatly affected the dislocation density of the upper layer.

Example 3 In this example, an LED was manufactured using the GaN-based semiconductor substrate obtained in Example 1 as a substrate. On the upper surface of the second layer of the GaN-based semiconductor substrate obtained in Example 1, n-type Al _0.1
Ga _0.9 N cladding layer, In _0.07 Ga _0.93 N light emitting layer, p
-Type Al _0.1 Ga _0.9 N cladding layer and a p-type GaN contact layer are sequentially grown in layers to form an ultraviolet L having an emission wavelength of 370 nm.
A wafer for ED was manufactured. For this wafer,
Further, an n-type and a p-type electrodes are formed, and element isolation is performed.
An ED element was used. The output of the collected LED chip (20
mA) and the value of the leakage current when -10 V was applied (reverse current characteristic). Table 2 shows the average value of the measurement results.

Comparative Example Sample 1 In order to compare with the LED of Example 3, the comparative example sample having no etch pit, which was formed for comparison in Example 1 above, was used as a wafer substrate in the same manner as in Example 3 for UV LE.
A D chip was prepared, and this was designated as Comparative Example Sample 1. Comparative Example Sample 2 Ga was deposited on a sapphire substrate without regrowth of the second layer.
N low-temperature buffer layer / n-type GaN layer (4 μm) / n-type Al
_0.1 Ga _0.9 N clad layer / In _0.07 Ga _0.93 N light emitting layer /
A p-type Al _0.1 Ga _0.9 N clad layer / p-type GaN contact layer is continuously grown to produce an ultraviolet LED chip,
Comparative Example Sample 2 was used. LE of these comparative samples
Table 2 shows the average value of the output (20 mA) of the D chip and the result of measuring the value of the leakage current (reverse current characteristic) when -10 V was applied.

[0047]

[Table 2]

As shown in Table 2, the output of the LED manufactured using the substrate according to the present invention was higher than that of the sample in which no etch pit was formed on the surface of the first layer (= conventional).
It turned out that it was a high quality LED with little leak current.

Embodiment 4 In this embodiment, when the second layer is regrown on the upper surface of the first layer on which the etch pits are formed in the first embodiment, the growth is performed under growth conditions that fill the inside of the etch pits. went. Except for the growth condition of the second layer, it is the same as Example 1. When etch pits were formed on the upper surface of the second layer under the same conditions as in Example 1, the dark spot density was 4.8 × 1.
0 ⁷ / cm ^-2, reduction of dislocation density was achieved.

Embodiment 5 In this embodiment, the formation of etch pits was repeated twice to reduce the dislocation density. Ga obtained in Example 1
An N-based semiconductor substrate (as shown in Example 1, the dark spot density on the upper surface of the second layer was 3.8 × 10 ⁷ / cm ⁻² ) was set in an RIE apparatus, and the upper surface was dry-etched and etched. A pit was formed. At this time, the diameter of the etch pit was 2 μm on average.

The GaN-based structure having the etched pits
Attach the semiconductor substrate to the MOVPE equipment and place
Same conditions as above (the growth rate in the lateral direction is
TMG, Ammo
Near, silane is flowed, and the n-type GaN layer is regrown by 3 μm.
To form a third layer. Dark spot on the upper surface of the obtained third layer
When the cut density was measured, 2.6 × 10 ⁷Pieces / cm^-2
Compared to the dark spot density on the upper surface of the second layer
It was found that the dislocation density was further reduced.

[0052]

As described above, according to the present invention, the formation of etch pits is positively incorporated into the crystal growth process, and the propagation of dislocation lines is controlled using the etch pits. In addition, the present invention can provide a new GaN-based semiconductor substrate having a reduced dislocation density and a method for manufacturing the same by simply etching the etch pits.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically illustrating an example of the structure of a GaN-based semiconductor substrate according to the present invention.

FIG. 2 shows PL intensity in a general GaN-based LED;
9 is a graph showing a relationship with the density of etch pits on the upper surface of a p-GaN layer on the uppermost layer of an element structure.

FIG. 3 is a SEM image of an etch pit appearing when a C-plane of a GaN crystal is dry-etched, and FIG.
FIG. 3 shows the magnification higher than that of FIG.

FIG. 4 is a cross-sectional view schematically showing another example of the structure of the GaN-based semiconductor substrate of the present invention.

[Explanation of symbols]

 Reference Signs List 1 First GaN-based crystal layer (first layer) 2 Second GaN-based crystal layer (second layer) P Etch pit m1 to m3 Dislocation line

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yoichiro Ouchi 4-3 Ikejiri, Itami-shi, Hyogo Prefecture Mitsubishi Cable Industries, Ltd. Itami Works (72) Inventor Takashi Tsunekawa 4-3-1 Ikejiri, Itami-shi, Hyogo Mitsubishi Electric Wire F-term (reference) in Itami Works 4K030 AA06 AA11 AA13 AA17 BA38 CA05 DA04 FA10 LA14 5F004 AA16 DB19 FA08 5F041 AA03 AA40 CA40 CA65 CA74 5F043 AA05 BB06 DD02 GG10 5F045 AA04 AA12 AF04

Claims (6)

[Claims] 1. A Ga having a stacked structure in which a second GaN-based crystal layer is grown on a first GaN-based crystal layer.
An N-based semiconductor substrate, wherein an upper surface of the first GaN-based crystal layer has an etch pit formed thereon, and the second GaN-based crystal layer grows, whereby the etch pit is A GaN-based semiconductor base material, which is in a hollow state and / or a state filled with a GaN-based crystal. 2. Etch pits are formed again on the upper surface of the second GaN-based crystal layer, or another GaN-based crystal layer is grown on the upper surface of the second GaN-based crystal layer and etched again on the upper surface. A pit is formed, and the re-formed etch pit is in a hollow state and / or
Or, so as to be filled with GaN-based crystal,
2. The GaN-based semiconductor substrate according to claim 1, wherein a further GaN-based crystal layer is growing, and by this repetition, two or more GaN-based crystal layers each having an upper surface on which an etch pit is formed are stacked. 3. 3. The GaN-based semiconductor substrate according to claim 1, wherein the etch pits are present at a density of 1 × 10 ⁶ / cm ² or more on the upper surface on which the etch pits are formed. 4. The GaN-based semiconductor substrate according to claim 1, wherein the etch pit has a diameter of 100 nm or more. 5. An etching pit is formed on an upper surface of a first GaN-based crystal layer, and the etching pit is formed on the upper surface of the first GaN-based crystal layer such that the etching pit is in a hollow state and / or a state filled with a GaN-based crystal. A method for producing a GaN-based semiconductor substrate, comprising a step of growing a second GaN-based crystal layer. 6. An etch pit is formed again on the upper surface of the second GaN-based crystal layer, or another GaN-based crystal layer is grown on the upper surface of the second GaN-based crystal layer and etched again on the upper surface. A repetitive process of forming pits and growing a further GaN-based crystal layer such that the re-formed etch pits are in a cavity state and / or a state filled with GaN-based crystals. The manufacturing method according to claim 5, wherein