JP2006147942A - Nitride semiconductor element manufacturing method and nitride semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a nitride semiconductor element which reduces pits caused by a high dislocation area of a substrate. <P>SOLUTION: A high dislocation area 15e is shown with dots on the main surface 15a of a gallium nitride substrate 15. A gallium nitride film 17 is deposited on the gallium nitride substrate 15 at the growing rate of 3 micrometers/hr or higher. Pits 21 are formed in the surface 17a of the GaN film 17 at pit surface density D(P). The growth of the gallium nitride film reduces the surface density of the pit 21 or 23 formed due to the high dislocation area 15e appearing on the surface 15a of the gallium nitride substrate 15, resulting in that the pitch surface density D(P) is reduced as small as 0<(D(P)/D(H))<0.8. Each pit 21 is composed of a plurality of facets (not shown) corresponding to the high dislocation area 15e on the main surface 15a of the GaN substrate 15. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a nitride semiconductor device and a nitride semiconductor device.

  Patent Document 1 describes a method for producing a low dislocation GaN single crystal of 106 cm −2 or less. In this method, a GaN single crystal thick film is grown so that the growth surface of vapor phase growth is not flat but has a three-dimensional facet structure. If the dislocation is reduced by growing without embedding the facet structure with the facet structure, single crystal gallium nitride is grown. Thereafter, in order to form a single crystal GaN substrate, the single crystal GaN substrate is flattened by mechanical processing, and a processed surface of the single crystal GaN substrate is further polished to obtain a mirror surface. This single crystal GaN substrate has a linear high dislocation region substantially perpendicular to the growth surface, and the density of the linear defect region is 105 cm −2 or less.

Patent Document 2 describes a single crystal gallium nitride substrate and a growth method thereof. A seed pattern is regularly provided on the base substrate to form facet pits thereon, and GaN is facet grown while maintaining the pits. By the facet growth, a high dislocation region is formed at the bottom of the pit formed by the facet surface, and the dislocation is collected in the region to lower the periphery thereof. Gallium nitride is obtained using this crystal.
JP 2001-102307 A JP 2003-165799 A

  The gallium nitride substrate described in the above patent document is made of a single crystal and has a high dislocation region distributed on the surface thereof and a low dislocation region surrounding the high dislocation region. When epitaxially growing on the gallium nitride substrate, the epitaxial layer does not grow normally on the high dislocation region, and pits are formed. When a nitride semiconductor device such as a light emitting diode is manufactured and a current is passed, leakage occurs from the pit portion, and good light emission characteristics cannot be obtained. In addition, when a nitride semiconductor element such as a diode is manufactured and a current is passed, leakage occurs from the pit portion, and good current-voltage characteristics cannot be obtained. Therefore, what is required is to reduce the leakage current caused by pits in the nitride semiconductor device.

  Accordingly, an object of the present invention is made in view of the above matters, and an object of the present invention is to provide a method of manufacturing a nitride semiconductor device that can reduce pits caused by a high dislocation region of a substrate. An object of the present invention is to provide a nitride semiconductor device in which pits resulting from a high dislocation region of a substrate are reduced.

  One aspect of the present invention is a method of manufacturing a nitride semiconductor device. This method includes the step of (a) preparing a group III nitride substrate having a main surface including a plurality of high dislocation areas and a low dislocation area surrounding the high dislocation areas, and the defect density in the high dislocation areas is low. The high dislocation area is larger than the defect density of the dislocation area, and the high dislocation area is distributed with the defect area surface density D (H) on the main surface, and (b) the group III nitride substrate at a growth rate of 3 micrometers / hour or more. And a surface of the gallium nitride film has pits distributed at a pit surface density D (P), and a pit surface corresponding to a defect area surface density D (H). The ratio of density D (P) (D (P) / D (H)) is greater than zero and less than 0.8.

  According to this method, since the gallium nitride film is grown at a growth rate of 3 micrometers / hour or more, the surface density of pits generated due to the high dislocation region appearing on the surface of the group III nitride substrate substrate, That is, the pit surface density D (P) can be reduced. As a result, the pit surface density D (P) decreases to about 0 <(D (P) / D (H)) <0.8.

  Another aspect of the present invention is a method of manufacturing a nitride semiconductor device. This method includes the step of (a) preparing a group III nitride substrate having a main surface including a high dislocation area and a low dislocation area surrounding the high dislocation area, and the defect density in the high dislocation area is the low dislocation area. And the high dislocation area is distributed with a defect area surface density D (H) on the main surface, and (b) on the main surface of the group III nitride substrate at a growth temperature of 1050 degrees Celsius or higher. The surface of the gallium nitride film has pits distributed at a pit surface density D (P), and the pit surface density D with respect to the defect area surface density D (H). The ratio (D) (D (P) / D (H)) is greater than zero and less than 0.4.

  According to this method, since the gallium nitride film is grown on the main surface of the group III nitride substrate at a growth temperature of 1050 degrees Celsius or higher, the generation occurs due to the high dislocation region appearing on the surface of the group III nitride substrate substrate. Pit surface density, that is, pit surface density D (P) can be reduced. As a result, the pit surface density D (P) is reduced to about 0 <(D (P) / D (H)) <0.4.

  Another aspect of the present invention is a method of manufacturing a nitride semiconductor device. This method includes the step of (a) preparing a group III nitride substrate having a main surface including a high dislocation area and a low dislocation area surrounding the high dislocation area, and the defect density in the high dislocation area is the low dislocation area. The high dislocation area is distributed with a defect area surface density D (H) on the main surface, and (b) the main group III nitride substrate has a growth rate of 3 micrometers / hour or more. Gallium nitride is deposited on the surface to form a gallium nitride film having a pit size of 5 micrometers or less.

  According to this method, since the gallium nitride film is grown on the main surface of the group III nitride substrate at a growth rate of 3 micrometers / hour or more, it is caused by the high dislocation region appearing on the surface of the group III nitride substrate substrate. Thus, the size of the generated pit can be reduced. As a result, the maximum pit size is reduced to 5 micrometers or less.

  Another aspect of the present invention is a method for manufacturing a nitride semiconductor device. This method includes the step of (a) preparing a group III nitride substrate having a main surface including a high dislocation area and a low dislocation area surrounding the high dislocation area, and the defect density in the high dislocation area is the low dislocation area. The high dislocation area is distributed at a defect area surface density D (H) on the main surface, and (b) on the main surface of the group III nitride substrate at a growth temperature of 1050 degrees Celsius or higher. And depositing gallium nitride to form a pit-sized gallium nitride film of 5 micrometers or less.

  According to this method, since the gallium nitride film is grown on the main surface of the group III nitride substrate at a growth temperature of 1050 degrees Celsius or higher, the generation occurs due to the high dislocation region appearing on the surface of the group III nitride substrate substrate. The size of the pit to be played can be reduced. As a result, the maximum pit size is reduced to 5 micrometers or less.

  In the method for manufacturing a nitride semiconductor device according to the present invention, the thickness of the gallium nitride layer is preferably 6 micrometers or less.

  If the thickness of the gallium nitride layer exceeds 6 micrometers, the size of the pits increases with increasing film thickness.

  The method according to the present invention further includes (c) a step of growing an AlXGa1-XN film (0 <X ≦ 1) on the main surface of the group III nitride substrate prior to the growth of the gallium nitride film. Is preferred.

  According to this method, AlGaN grows not only on the surface of the group III nitride substrate but also on contaminants adhering to the surface, and the surface of the AlGaN film becomes flat. Therefore, a suitable base for the growth of the gallium nitride film can be provided.

  According to still another aspect of the present invention, a nitride semiconductor device includes: (a) a main surface including a plurality of high dislocation areas and a low dislocation area surrounding the high dislocation area; and a back surface opposite to the main surface. A group III nitride supporting base having: (b) a gallium nitride based semiconductor region including a gallium nitride layer provided on the group III nitride supporting base; and (c) provided on the gallium nitride based semiconductor region. And (d) a second electrode provided on the back surface of the group III nitride support substrate, wherein the defect density in the high dislocation area is larger than the defect density in the low dislocation area. The high dislocation areas are distributed with a defect surface density D (H) on the main surface, the thickness of the gallium nitride based semiconductor region is T micrometers, and the surface of the uppermost layer of the gallium nitride based semiconductor region Is the defect area surface Pits distributed at a pit surface density D (P) smaller than degree D (H), and the size of the pits on the surface is not less than 1 micrometer and not more than 10 micrometers, The depth of the pit is not less than 0.1 micrometers and not more than T micrometers.

  In the manufacture of the nitride semiconductor device, pits resulting from the high dislocation area are formed on the surface of the gallium nitride layer in the gallium nitride based semiconductor region. It is also possible to deposit gallium nitride under film forming conditions so that the pits are not formed. However, the crystal quality of gallium nitride deposited under such conditions is not very good. On the other hand, in a vertical nitride semiconductor device in which current flows from one of the first and second electrodes to the other across the group III nitride support base and the gallium nitride based semiconductor region, every pit formed is a nitride semiconductor device. The inventors have found that the nitride semiconductor element exhibits characteristics in a desired range if the size and depth are pits as described below. That is, the pit size is in the range of 1 to 10 micrometers, and the depth of the pits on the surface is in the range of 0.1 to T micrometers.

  In the nitride semiconductor device according to the present invention, the ratio (D (P) / D (H)) of the pit surface density D (P) to the defect area surface density D (H) is larger than zero and smaller than 0.8. It is preferable. According to D (P) / D (H) in this range, the nitride semiconductor device exhibits good current-voltage characteristics.

  In the nitride semiconductor device according to the present invention, the ratio (D (P) / D (H)) of the pit surface density D (P) to the defect area surface density D (H) is larger than zero and smaller than 0.4. It is preferable. According to this nitride semiconductor device, according to D (P) / D (H) in this range, the nitride semiconductor device exhibits good current-voltage characteristics.

  In the nitride semiconductor device according to the present invention, the maximum size of the pits on the surface is preferably 5 micrometers or less.

  If the maximum size of the pits is 5 micrometers or less, the characteristics of the nitride semiconductor device are not significantly affected by the pits in this range.

  In the nitride semiconductor device according to the present invention, it is preferable that the pit surface density D (P) is greater than zero and less than 800 cm −2, and the chip area of the nitride semiconductor device is 0.1225 square millimeters or less. If the pit surface density D (P) is less than 800 cm −2, a nitride semiconductor element corresponding to a side size of 350 μm or less exhibits good characteristics.

  In the nitride semiconductor device according to the present invention, it is preferable that the pit surface density D (P) is greater than zero and less than 25 cm −2, and the nitride semiconductor device has a chip area of 4 mm 2 or less. When the pit surface density D (P) is less than 25 cm −2, a nitride semiconductor element having a side size of 2 millimeters or less exhibits good characteristics.

  In the nitride semiconductor device according to the present invention, the gallium nitride layer preferably has a thickness of 6 micrometers or less. If the thickness of the gallium nitride layer exceeds 6 micrometers, the size of the pits increases as the film thickness increases, deteriorating the device characteristics.

  The nitride semiconductor device according to the present invention may further include an AlXGa1-XN layer (0 <X ≦ 1) provided between the group III nitride support base and the gallium nitride layer.

  According to this nitride semiconductor device, since AlGaN grows also on the contaminant adhering on the surface of a group III nitride substrate, the surface morphology of the AlGaN layer is good. Therefore, a suitable base for the growth of the gallium nitride layer can be provided.

  The above and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

  As described above, according to the present invention, there is provided a method for manufacturing a nitride semiconductor device capable of reducing pits resulting from a high dislocation region of a group III nitride substrate. Moreover, according to the present invention, a nitride semiconductor device in which pits resulting from a high dislocation region of a substrate are reduced is provided.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, embodiments of the nitride semiconductor device manufacturing method and the nitride semiconductor device according to the present invention will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals.

(First embodiment)
FIG. 1A illustrates a method for manufacturing a nitride semiconductor device. FIG. 1B is an enlarged view of the group III nitride substrate in the broken line BOX shown in FIG. 2A, 2B, and 2C are views for explaining a method of manufacturing a nitride semiconductor device.

  Referring to FIG. 1A, a prepared group III nitride substrate such as a gallium nitride substrate 15 is placed on a susceptor 13 of a film forming apparatus 11. An AlXGa1-XN (0≤X≤1) substrate can be used as the group III nitride substrate. In the following explanation, the gallium nitride substrate 15 is referred to as the group III nitride substrate. For example, a metal organic vapor phase growth apparatus can be used as the film forming apparatus 11.

  The gallium nitride substrate 15 has a structure as shown in FIG. Group III nitride is deposited on the main surface 15a of the gallium nitride substrate 15 in a later step. Referring to FIG. 1B, one arrangement of a high dislocation region 15c and a low dislocation region 15d in a gallium nitride (GaN) substrate 15 for a vertical group III nitride semiconductor device is shown. Each of the high dislocation regions 15c is surrounded by the low dislocation regions 15d and extends from the main surface 15a of the gallium nitride substrate 15 to the back surface 15b. The main surface 15a of the gallium nitride substrate 15 has a first area 15e in which a high dislocation region 15c having a relatively large threading dislocation density appears and a second area 15d in which a low dislocation region 15d having a relatively small threading dislocation density appears. And an area 15f. Since the high dislocation region 15c is surrounded by the low dislocation region 15d, the first area 15e is distributed in the form of dots in the second area 15f on the main surface 15a. The threading dislocation density as a whole is, for example, 1 × 10 8 cm −2 or less. For example, the high dislocation regions 15 c are irregularly (randomly) arranged on the gallium nitride substrate 15. The defect area surface density D (H) of the high dislocation region 15c in the main surface 15a of the substrate 15 is, for example, 100 / cm 2 or more and 1 × 10 5 / cm 2 or less. Further, the ratio of the surface area of the first area 15e to the area of the main surface 15a of the gallium nitride substrate 15 is, for example, 1% or less. The dislocation density in the high dislocation region 15c is, for example, 3 × 10 7 cm −2 or less, and the dislocation density in the low dislocation region 15 d is, for example, 5 × 10 6 cm −2 or less. According to this epitaxial substrate 15, since the dislocation density is small, dislocations in the epitaxial layer are reduced.

  A gallium nitride based semiconductor region is grown on the gallium nitride substrate 15. First, as shown in FIG. 2A, a gallium nitride film is grown on the main surface 15a of the gallium nitride substrate 15 at a growth rate of 3 micrometers / hour or more. Thereby, an epitaxial substrate is provided. The surface 17a of the gallium nitride film 17 has pits (reference number 21 shown in FIG. 3B or reference number 23 shown in FIG. 3C) distributed at a pit surface density D (P). The ratio (D (P) / D (H)) of the pit surface density D (P) to the defect area surface density D (H) is larger than zero and smaller than 0.8. As a result, the epitaxial substrate E1 is provided.

  According to this method, since the gallium nitride film 17 is grown at a growth rate of 3 micrometers / hour or more, pits generated due to the high dislocation area 15e appearing on the surface 15a of the gallium nitride substrate 15 (FIG. 3). The surface density of the reference number 21 shown in (B) or the reference number 23 shown in FIG. As a result, the pit surface density D (P) decreases to about 0 <(D (P) / D (H)) <0.8.

  Prior to the growth of the gallium nitride film 15, an AlXGa1-XN film (0 <X ≦ 1) 19 is preferably grown on the main surface 15 a of the gallium nitride substrate 15. AlGaN grows not only on the surface 15a of the gallium nitride substrate 15 but also on the contaminants adhering to the surface 15a, and the surface 19a of the AlGaN film 19 exhibits good morphology. Therefore, a suitable base for the growth of the gallium nitride film 15 can be provided.

  Referring to FIG. 3A, high dislocation areas 15e (for example, 25 high dislocation areas) are indicated by dots on the main surface 15a of the gallium nitride substrate 15. Referring to FIG. 3B, a gallium nitride film 17 is deposited on the gallium nitride substrate 15 shown in FIG. 3A under the conditions according to the present embodiment. On the surface 17a of the GaN film 17, pits 21 are formed with a pit surface density D (P). Although not shown, each pit 21 includes a plurality of facets, and corresponds to the high dislocation area 15e of the main surface 15a of the GaN substrate 15. Referring to FIG. 3C, an AlGaN film 19 and a GaN film 17 are deposited on the gallium nitride substrate 15 shown in FIG. 3A under the conditions according to the present embodiment. On the surface 17a of the GaN film 17, pits 23 are formed with a pit surface density D (P). Each pit 23 is composed of a plurality of facets like the pit 21 and corresponds to the high dislocation area 15 e of the main surface 15 a of the gallium nitride substrate 15. The pits 21 (23) do not have the same opening size and depth, and the sizes and depths are different from each other.

  As shown in FIG. 2B, a gallium nitride based semiconductor region is subsequently formed. On the gallium nitride film 17, an active region 25 having a quantum well structure, a p-type gallium nitride based semiconductor layer 27, and a p-type contact layer 29 are grown in this order. As a result, the epitaxial substrate E2 is provided.

  As shown in FIG. 2C, the first electrode film 31 for the anode is formed on the p-type contact layer 29, and the second electrode film 33 for the cathode is formed on the back surface of the gallium nitride substrate 15. 15b. As a result, a substrate product 35 is provided. The substrate product 35 is cut to produce a large number of semiconductor chips.

  In one modification of the present embodiment, as shown in FIG. 4A, a gallium nitride film 37 is grown on the main surface 15a of the gallium nitride substrate 15 at a growth temperature of 1050 degrees Celsius or higher. The ratio (D (P) / D (H)) of the pit surface density D (P) to the high dislocation area surface density D (H) is larger than zero and smaller than 0.4. Thereby, the epitaxial substrate E3 is provided. Since the gallium nitride film is grown on the main surface of the group III nitride substrate at a growth temperature of 1050 degrees Celsius or higher, the surface density of pits generated due to the high dislocation area on the surface of the group III nitride substrate substrate is reduced. it can. As a result, the pit surface density D (P) is reduced to about 0 <(D (P) / D (H)) <0.4. Prior to the growth of the gallium nitride film 37, it is preferable to grow an AlXGa1-XN film (0 <X ≦ 1) 19.

  As shown in FIG. 4B, a gallium nitride based semiconductor region is formed. For this formation, an active region 25 having a quantum well structure, a p-type gallium nitride based semiconductor layer 27 and a p-type contact layer 29 are grown on the gallium nitride film 37 in this order. As a result, an epitaxial substrate E4 is provided. As shown in FIG. 4C, a first electrode film 31 for the anode is formed on the p-type contact layer 29, and a second electrode film 33 for the cathode is formed on the gallium nitride substrate 15. The back surface 15b is formed. The substrate product 41 is cut to produce a large number of semiconductor chips.

Example 1
As described below, a blue light-emitting diode is fabricated by metal organic vapor phase epitaxy using trimethylgallium, trimethylaluminum, trimethylindium, ammonia, silane, and cyclopentadienylmagnesium as raw materials. An n-type GaN (0001) substrate having a dislocation area surface density D (H) of 900 cm −2 is placed on a susceptor, and the pressure of the metal organic vapor phase growth apparatus is controlled to 30 kPa. Ammonia (NH3) and hydrogen (H2) are supplied. Pre-cleaning is performed for 10 minutes at a substrate temperature of 1050 degrees Celsius. Thereafter, the substrate temperature is raised to 1130 degrees Celsius and the pressure of the metal organic vapor phase epitaxy apparatus is increased to 101 kPa. Trimethylgallium, trimethylaluminum, ammonia, and silane are supplied to a metal organic vapor phase growth apparatus to grow an n-type Al0.12Ga0.88N film having a thickness of 50 nm. Next, a gallium nitride buffer film having a thickness of 2 micrometers is grown at a growth rate of 4 μm / h at a substrate temperature of 1100 degrees Celsius and a pressure of 101 kPa. Thereafter, the substrate temperature is lowered to 800 degrees Celsius to grow a light emitting layer having a three-cycle multiple quantum well structure (InGaN barrier layer: 15 nm, InGaN well layer: 3 nm). The substrate temperature is raised to 1050 degrees Celsius, and trimethylaluminum, trimethylgallium, ammonia, and cyclopentadienylmagnesium are supplied to the metalorganic vapor phase growth apparatus to grow a 20 nm thick Mg-doped Al0.12Ga0.88N film. To do. Thereafter, trimethylgallium, ammonia, and cyclopentadienylmagnesium are supplied to the metalorganic vapor phase growth apparatus to grow a p-type GaN film having a thickness of 150 nm. Thereby, an epitaxial substrate having an LED epitaxial structure is obtained.

  When the surface of this epitaxial substrate was observed with a differential interference microscope, there was a pit having a diameter of about 3 μm corresponding to the position of the high dislocation area of the GaN substrate, and the pit surface density D (P) was 400 cm−2. is there. Therefore, D (P) / D (H) = 0.44.

  A semitransparent anode electrode is formed on the p-type GaN film of the epitaxial substrate, and a cathode electrode is formed on the back surface of the GaN substrate. When a continuous current is applied to a blue light emitting diode of a 350 μm square light emitting diode bare chip, the blue light emitting diode exhibits a light output of 4 mW at a current value of 20 mA and a wavelength of 450 nm. On the other hand, when a continuous current is applied to a blue light emitting diode of a 2 mm square light emitting diode bare chip, the leaky current-voltage characteristics shown in FIG. 5 are exhibited. A leaky blue light emitting diode does not emit light.

(Example 2)
An n-type GaN (0001) substrate having a dislocation area surface density D (H) of 900 cm −2 is subjected to preliminary cleaning at a substrate temperature of 1050 degrees Celsius for 10 minutes, and then at a substrate temperature of 1050 degrees Celsius and a pressure of 101 kPa. An n-type Al0.12Ga0.88N film having a thickness of 50 nm is grown. Next, a gallium nitride buffer film having a thickness of 2 micrometers is grown at a growth rate of 9 μm / h while maintaining a pressure of 101 kPa at a substrate temperature of 1130 degrees Celsius. Subsequent steps are the same as those in the first embodiment. When the surface of the completed epitaxial substrate having the LED epitaxial structure was observed with a differential interference microscope, pits having a diameter of about 3 μm were present at locations corresponding to the positions of the high dislocation areas of the substrate, and the pit surface density D (P ) Is 12 cm−2. Therefore, D (P) / D (H)) = 0.013.

  A semitransparent anode electrode is formed on the p-type GaN film of the epitaxial substrate, and a cathode electrode is formed on the back surface of the GaN substrate. When a continuous current is applied to a blue light emitting diode of a 2 mm square light emitting diode bare chip, the blue light emitting diode exhibits a light output of 4 mW at a current value of 20 mA and a wavelength of 450 nm. When a continuous current is applied to a blue light emitting diode of a 2 mm square light emitting diode bare chip, good current-voltage characteristics as shown in FIG. 6 are exhibited. The bare-chip blue light-emitting diode exhibits a light output of 100 mW at a current value of 500 mA and a wavelength of 450 nm.

(Example 3)
In the fabrication of the light emitting diode shown in Example 2, n-type GaN layers are formed at several growth rates. FIG. 7 is a drawing showing the relationship between the growth rate and the pit diameter. Referring to FIG.
Growth rate Pit diameter 2.2 μm / h 5 μm or less 4.2 μm / h 3 μm or less 9 μm / h 2 μm or less, and the film formation temperature is 1100 degrees Celsius.
If the growth rate is 3 μm / h or more, the pit diameter formed on the surface of the gallium nitride film can be 5 μm or less even when the film formation rate and the variation in pit diameter are taken into consideration. Therefore, the size of the pit generated due to the high dislocation region appearing on the surface of the gallium nitride substrate can be reduced. Gallium nitride can be deposited on the main surface of the gallium nitride substrate at a growth rate of 3 micrometers / hour or more to form a gallium nitride film having a maximum pit size of 5 micrometers or less.

  FIG. 8 is a drawing showing the relationship between the growth rate and the ratio (D (P) / D (H)). If the growth rate exceeds 3 μm / h, (D (P) / D (H)) can be less than 0.8.

  FIG. 9A, FIG. 9B, and FIG. 9C are drawings showing micrographs of the surface of the gallium nitride film. Each film thickness is 2 micrometers. These drawings show that the pit size decreases when the deposition rate is changed to 2.2 μm / h, 4.2 μm / h, and 9 μm / h.

FIG. 10 is a drawing showing the relationship between the growth temperature and the pit diameter. Referring to FIG.
Growth rate Pit diameter 1030 degrees Celsius 5 μm or less 1100 degrees Celsius 3 μm or less 1130 degrees Celsius 2130 μm or less If the growth temperature exceeds 1030 degrees Celsius, the pit diameter formed on the surface of the gallium nitride film can be reduced to 5 μm or less even when the film forming temperature and the variation in pit diameter are taken into consideration. Therefore, the size of the pit generated due to the high dislocation region appearing on the surface of the gallium nitride substrate can be reduced. Gallium nitride can be deposited on the main surface of the gallium nitride substrate at a growth temperature of 1050 degrees Celsius or higher to form a gallium nitride film having a maximum pit size of 5 micrometers or less.

  FIG. 11 is a drawing showing the relationship between the growth temperature and the ratio (D (P) / D (H)). If the growth temperature exceeds 1100 degrees Celsius, (D (P) / D (H)) can be made less than 0.4.

  12 (A) and 12 (B) are drawings showing micrographs of the surface of the gallium nitride film. Each film thickness is 2 micrometers. These drawings show that when the film formation temperature is changed to 1100 degrees Celsius and 1130 degrees Celsius at the film formation speed of 9 μm / h, the size of the pits is reduced.

  FIGS. 13A and 13B are micrographs of the surface of the gallium nitride film. Each film thickness is 2 micrometers. These drawings show that when the film formation temperature is changed to 1030 degrees Celsius and 1100 degrees Celsius at the film formation speed of 4.2 μm / h, the size of the pits is reduced.

FIG. 14 is a drawing showing the relationship between the thickness of the gallium nitride film and the pit diameter. Referring to FIG.
Thickness of gallium nitride film Pit diameter 2 μm 2 μm or less 6 μm 5 μm or less 9 μm 8 μm or less The film forming temperature is 1130 degrees Celsius, and the film forming speed is 9 μm / h. According to the results of FIG. 14, the pit diameter increases as the thickness of the gallium nitride film increases. The preferred thickness of the gallium nitride layer is 6 micrometers or less. If the thickness of the gallium nitride layer exceeds 6 micrometers, the pit size exceeds 5 micrometers. Moreover, if the thickness of the gallium nitride layer is 0.5 micrometers or more, good LED characteristics can be obtained.

  FIG. 15 is a drawing showing the relationship between the thickness of the gallium nitride film and the ratio (D (P) / D (H)). Even when the gallium nitride film is thickened, the ratio (D (P) / D (H)) does not substantially change. The deposition temperature is 1130 degrees Celsius, the deposition rate is 9 μm / h, and the pressure is 101 kilopascals.

  FIG. 16A, FIG. 16B, and FIG. 16C are drawings showing micrographs of the surface of a gallium nitride film. Each film formation rate is 9 μm / h. These drawings show that the pit size increases as the film thickness increases to 2 μm, 6 μm, and 9 μm.

  FIG. 17 is a drawing showing the relationship between the ratio (D (P) / D (H)) and the yield of light-emitting diodes (2 mm square). The anode electrode is provided on the entire surface of the contact layer, and the cathode electrode is provided on the entire back surface of the gallium nitride supporting base. Referring to FIG. 17, when the ratio (D (P) / D (H)) exceeds 0.4, the yield is substantially zero. If the ratio (D (P) / D (H)) is 0.3 or less, the yield exceeds a practical level. Further, when (D (P) / D (H)) is 0.01 or less, the yield is good.

(Second Embodiment)
FIG. 18 is a drawing showing a nitride semiconductor device according to the second embodiment. The nitride semiconductor element 51 includes a group III nitride support base such as a gallium nitride support base 53, a gallium nitride based semiconductor region 55, a first electrode 57, and a second electrode 59. Since the nitride semiconductor device 51 is a semiconductor chip formed by dividing a semiconductor product produced by growing a plurality of epitaxial films on the gallium nitride substrate shown in FIG. Similar to the main surface of the gallium nitride substrate 15, the main surface 53a of the base 53 includes a plurality of high dislocation areas and a low dislocation area surrounding the high dislocation area. Greater than defect density. Further, the high dislocation areas are distributed at the defect surface density D (H) on the main surface 53a. The first electrode 57 is provided on the gallium nitride based semiconductor region 55. The second electrode 59 is provided on the back surface 53 b of the gallium nitride support base 53. The thickness of the gallium nitride based semiconductor region 55 is T micrometers.

  On the uppermost surface 55a of the gallium nitride based semiconductor region 55, pits having a pit surface density D (P) that is smaller than the defect area surface density D (H) are formed. Each pit corresponds to a high dislocation area on the main surface 53 a of the gallium nitride support base 53. The gallium nitride based semiconductor region 55 includes a gallium nitride layer 61 provided on the gallium nitride support base 53. Therefore, the size of the pits on the surface 55a is not less than 1 micrometer and not more than 10 micrometers, and the depth of the pits on the surface 55a is not less than 0.1 micrometers and not more than T micrometers. It is.

  In the manufacture of the nitride semiconductor element 51, the surface of the gallium nitride layer 61 of the gallium nitride based semiconductor region 55 is formed on the surface of the support base 53 (substrate 15) as shown in FIGS. 3B and 3C. Pits resulting from the high dislocation area are formed. It is also possible to deposit gallium nitride under film forming conditions so that the pits are not formed. However, although the crystal quality of gallium nitride deposited under such conditions is acceptable, it is not very good. In a vertical nitride semiconductor device in which a current flows from one of the first and second electrodes to the other across the gallium nitride support base 53 and the gallium nitride based semiconductor region 55, all the formed pits are formed on the nitride semiconductor device 51. The inventor has found that the nitride semiconductor device exhibits a desired range of characteristics if the size and depth are as follows, without deteriorating the characteristics. That is, the size of pits on the surface 55a is in the range of 1 to 10 micrometers, and the depth of the pits on the surface 55a is in the range of 0.1 to T micrometers.

  As shown in FIG. 18, the gallium nitride support base 53 includes a large number of high dislocation regions 53c. Due to some of these high dislocation regions 53c, the surface 55a of the gallium nitride based semiconductor region 55 (in this embodiment, the surface of the uppermost contact layer) has corresponding pits (not shown in FIG. 18). Not) appears. FIG. 19 is a schematic diagram showing pits P1, P2, and P3 formed on the surface 55a of the gallium nitride based semiconductor region 55. FIG. High defect areas HD1, HD2 and HD3 are located on the surface of the gallium nitride support base 53. The pits P1, P2, and P3 are respectively associated with dislocation groups TD1, TD2, and TD3 extending from the high defect areas HD1, HD2, and HD3 so as to sew in the gallium nitride based semiconductor region 55. As shown in the figure, the size Dia and the depth Dep of the pits P1, P2, and P3 are various.

  If the pit size Dia on the surface 55a is 10 micrometers or less, the nitride semiconductor device exhibits characteristics in a desired range. If the pit size Dia on the surface 55a is 1 micrometer or more, the crystal quality is good. If the depth Dep of the pits P on the surface 55a is 0.1 micrometers or more, the crystal quality is good. If the depth Dep of the pits P on the surface 55a is equal to or smaller than the thickness of the gallium nitride based semiconductor region 55, the nitride semiconductor element exhibits a desired range of characteristics.

  If the gallium nitride film is forcibly grown under the condition of “reduced pressure” that embeds the pits, the crystal quality deteriorates. In other words, the crystal quality of the gallium nitride layer 61 that realizes the pits P having the size Dia and the depth Dep is better than the crystal quality of the gallium nitride layer formed under the film formation conditions so that the pits are not formed. It is. In addition, when the pit size and depth are in the above ranges, the influence on the characteristics of the nitride semiconductor device 51 is small.

  In a preferred embodiment, an n-type AlXGa1-XN (0 <X ≦ 1) layer 63 is provided between the n-type gallium nitride support base 53 and the n-type gallium nitride layer 61. Since AlGaN also grows on contaminants adhering to the surface of the gallium nitride substrate, the surface morphology of the AlGaN layer 63 is good. Therefore, a suitable base for the growth of the n-type gallium nitride layer 61 can be provided.

  The nitride semiconductor element 51 has a structure that can be used as a light-emitting diode. As shown in FIG. 18, the light-emitting region 65 provided on the gallium nitride layer 61 and the p provided on the light-emitting region 65 are provided. And a p-type contact layer 69 provided on the p-type gallium nitride semiconductor layer 67. The light emitting region 65 includes a well layer 65a and a barrier layer 65b. The first electrode 57 is, for example, a translucent electrode, and can be provided so as to cover the entire surface of the p-type contact layer 69. A pad electrode 71 is provided on the first electrode 57.

  In the nitride semiconductor device manufactured using the film formation conditions described with reference to FIG. 8, the ratio of the pit surface density D (P) to the defect area surface density D (H) (D (P) / D ( H)) is greater than zero and less than 0.8. According to D (P) / D (H) in this range, the nitride semiconductor device exhibits good current-voltage characteristics.

  Further, in the nitride semiconductor device manufactured using the film forming conditions described with reference to FIG. 11, the ratio (D (P) / D (H)) of the pit surface density D (P) is less than zero. Greater than 0.4. According to D (P) / D (H) in this range, the nitride semiconductor device exhibits good current-voltage characteristics.

  As described with reference to FIG. 14, if the maximum size P of the pits P on the surface 55a is 5 micrometers or less, the characteristics of the nitride semiconductor element 51 are not significantly affected by the pits in this range. As described with reference to FIG. 14, the thickness of the gallium nitride layer 61 is preferably 6 micrometers or less. If the thickness of the gallium nitride layer exceeds 6 micrometers, the size of the pits increases with increasing film thickness. Moreover, if the thickness of the gallium nitride layer is 0.5 micrometers or more, the LED characteristics are good.

  In a nitride semiconductor device using a gallium nitride support in which high dislocation areas are distributed on the substrate surface, if the pit surface density D (P) is less than 800 cm −2, the chip area is 0.1225 mm 2 or less (one side is 350 μm or less). The nitride semiconductor device (corresponding to the size) exhibits good characteristics and realizes a practical yield. If the pit surface density D (P) is less than 800 cm −2 and the chip area is 0.1225 mm 2 or less, an element that does not include any pits can be obtained.

  In a nitride semiconductor device using a gallium nitride support in which high dislocation areas are distributed on the substrate surface, if the pit surface density D (P) is less than 25 cm −2, the chip area is 4 mm 2 or less (the size of one side is 2 mm or less). The nitride semiconductor device corresponding to (2) exhibits good characteristics and achieves a practical yield. If the pit surface density D (P) is less than 25 cm −2 and the chip area is 4 mm 2 or less, an element including no pits can be obtained.

  The nitride semiconductor device is not limited to a semiconductor light emitting device such as a light emitting diode. FIG. 20A is a drawing showing a modification of the nitride semiconductor device according to the second embodiment. The Schottky diode 81 includes a group III nitride support base such as the gallium nitride support base 53, a gallium nitride based semiconductor region 85, a first electrode (Schottky electrode) 87, and a second electrode 89 (ohmic electrode). The thickness of the gallium nitride based semiconductor region 85 is T micrometers, and the gallium nitride based semiconductor region 85 can include the GaN layer 61 and, if necessary, the AlGaN layer 63.

  FIG. 20B is a drawing showing another modification of the nitride semiconductor device according to the second embodiment. The pn junction diode 91 includes a group III nitride support base 53 such as a gallium nitride support base 53, a gallium nitride based semiconductor region 95, a first electrode 97 (ohmic electrode), and a second electrode 99 (ohmic electrode). Prepare. The thickness of the gallium nitride based semiconductor region 95 is T micrometers, and the gallium nitride based semiconductor region 95 can include a GaN layer 61 and a p-type gallium nitride based semiconductor layer 93, and if necessary, an AlGaN layer. 63 can be included. The p-type gallium nitride based semiconductor layer 93 can be, for example, a p-type GaN layer.

(Example 3)
A Schottky diode is manufactured by metal organic vapor phase epitaxy as follows. An n-type GaN (0001) substrate having a dislocation area surface density D (H) of 900 cm −2 is placed on a susceptor, and the pressure of the metal organic vapor phase growth apparatus is controlled to 30 kPa. Ammonia (NH3) and hydrogen (H2) are supplied. Pre-cleaning is performed for 10 minutes at a substrate temperature of 1050 degrees Celsius. Thereafter, the substrate temperature is raised to 1130 degrees Celsius and the pressure of the metal organic vapor phase epitaxy apparatus is increased to 101 kPa. Trimethylgallium, trimethylaluminum, ammonia, and silane are supplied to a metal organic vapor phase growth apparatus to grow an n-type Al0.12Ga0.88N film having a thickness of 50 nm. Next, a gallium nitride buffer film having a substrate temperature of 1130 degrees Celsius and a pressure of 101 kPa and a 5 × 10 15 cm −3 carrier concentration and a thickness of 3 μm is grown at a growth rate of 4 μm / h. Thereby, an epitaxial substrate having an LED epitaxial structure is obtained.

  An ohmic electrode (cathode) is formed on the back surface of the GaN substrate, and a Schottky electrode (anode) is formed on the n-type GaN film of the epitaxial substrate. Prior to the formation of the ohmic electrode and the Schottky electrode, an epitaxial substrate is formed for about 1 minute at room temperature using an HCl solution. The ohmic electrode is formed on the entire back surface of the GaN substrate after organic cleaning, and the structure of the ohmic electrode is Ti / Al / Ti / Au (29 nm / 100 nm / 20 nm / 300 nm), and these metal films are deposited by EB vapor deposition. Deposit by the method. After forming the ohmic electrode, alloying is performed at 600 degrees Celsius for about 1 minute. As the Schottky electrode, a 500 nm gold film is deposited on the GaN epitaxial film by resistance heating vapor deposition. The Schottky electrode is, for example, a circle having a diameter of 800 micrometers. The semiconductor element manufactured in this way is referred to as Sample A.

  Next, sample B is prepared. An n-type GaN (0001) substrate having a dislocation area surface density D (H) of 900 cm −2 is placed on a susceptor, and the pressure of the metal organic vapor phase growth apparatus is controlled to 30 kPa while ammonia is added to the metal organic vapor phase growth apparatus. (NH3) and hydrogen (H2) are supplied. Pre-cleaning is performed for 10 minutes at a substrate temperature of 1050 degrees Celsius. Thereafter, the substrate temperature of 1130 degrees Celsius and the pressure of the metal organic chemical vapor deposition apparatus are increased to 101 kPa. Trimethylgallium, trimethylaluminum, ammonia, and silane are supplied to a metal organic vapor phase growth apparatus to grow an n-type Al0.12Ga0.88N film having a thickness of 50 nm. Next, a gallium nitride buffer film having a 5 × 10 15 cm −3 carrier concentration and a thickness of 3 μm is grown at a growth rate of 9 μm / h at a substrate temperature of 1130 degrees Celsius and a pressure of 101 kPa. Thereby, an epitaxial substrate having an LED epitaxial structure is obtained. Similar to sample A, an ohmic electrode and a Schottky electrode are prepared.

  The reverse direction IV characteristic of sample A indicates that the Schottky diode is leaky, but the reverse direction IV characteristic of sample B is good.

  Many semiconductor devices have a structure in which a gallium nitride semiconductor film is provided on a group III nitride supporting substrate. Although not described with reference to the drawings, the nitride semiconductor device can be a MIS vertical field effect transistor, a vertical insulated gate bipolar transistor, or the like in addition to the semiconductor device described in the second embodiment. The nitride semiconductor element includes at least one of a light emitting diode, a Schottky diode, a pn junction diode, a MIS vertical field effect transistor, and a vertical insulated gate bipolar transistor.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. The present invention is not limited to the specific configuration disclosed in the present embodiment. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

FIG. 1A illustrates a method for manufacturing a nitride semiconductor device. FIG. 1B is an enlarged view of the group III nitride substrate in the broken line shown in FIG. 2A, 2B, and 2C are views for explaining a method of manufacturing a nitride semiconductor device. FIG. 3A shows the distribution of high dislocation areas on the surface of the gallium nitride substrate. FIGS. 3B and 3C are diagrams showing the distribution of pits on the surface of the gallium nitride film formed on the substrate shown in FIG. 4 (A), 4 (B), and 4 (C) are diagrams illustrating a modification of the method for manufacturing a nitride semiconductor device. FIG. 5 is a diagram showing a leaky current-voltage characteristic (Example 1) of a blue light emitting diode (Example 1) of a 2 mm square LED bare chip. FIG. 6 is a drawing showing good current-voltage characteristics of a blue light emitting diode (Example 2) of a 2 mm square light emitting diode bare chip. FIG. 7 is a drawing showing the relationship between the growth rate and the pit diameter. FIG. 8 is a drawing showing the relationship between the growth rate and the ratio (D (P) / D (H)). FIG. 9A, FIG. 9B, and FIG. 9C are drawings showing micrographs of the surface of the gallium nitride film. FIG. 10 is a diagram showing the relationship between the growth temperature and the pit diameter. FIG. 11 is a drawing showing the relationship between the growth temperature and the ratio (D (P) / D (H)). 12 (A) and 12 (B) are drawings showing micrographs of the surface of the gallium nitride film. 13A and 13B are drawings showing micrographs of the surface of a gallium nitride film. FIG. 14 is a drawing showing the relationship between the thickness of the gallium nitride film and the pit diameter. FIG. 15 is a drawing showing the relationship between the thickness of the gallium nitride film and the ratio (D (P) / D (H)). FIG. 16A, FIG. 16B, and FIG. 16C are drawings showing micrographs of the surface of a gallium nitride film. FIG. 17 is a drawing showing the relationship between the ratio (D (P) / D (H)) and the yield of light-emitting diodes (2 mm square). FIG. 18 is a drawing showing a nitride semiconductor device according to the second embodiment. FIG. 19 is a schematic diagram showing various pits formed on the surface of the gallium nitride based semiconductor region. FIG. 20A is a drawing showing a modification of the nitride semiconductor device according to the second embodiment. FIG. 20B is a drawing showing another modification of the nitride semiconductor device according to the second embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Film-forming apparatus, 13 ... Susceptor, 15 ... Gallium nitride substrate, 15c ... High dislocation region, 15d ... Low dislocation region, 15e ... First area, 15f ... Second area, 17 ... Gallium nitride film, 19 ... AlXGa1-XN film, 21, 23 ... pit, 25 ... active region, 27 ... p-type gallium nitride based semiconductor layer, 29 ... p-type contact layer, E1, E2, E3, E4 ... epitaxial substrate, 31 ... first electrode Film, 33 ... second electrode film, 35 ... substrate product, 37 ... gallium nitride film, 51 ... nitride semiconductor element, 53 ... gallium nitride support base, 55 ... gallium nitride based semiconductor region, 57 ... first electrode 59, second electrode, 61, gallium nitride layer, HD1, HD2, HD3, high defect area, P1, P2, P3, pit, TD1, TD2, TD3, dislocation group, Dia, pit size. , Dep ... depth of pit, 63 ... AlXGa1-XN layer, 65 ... light emitting region, 67 ... p-type gallium nitride semiconductor layer, 69 ... p-type contact layer, 71 ... pad electrode, 81 ... Schottky diode, 91 ... pn Junction diode

Claims (14)

A method of manufacturing a nitride semiconductor device, comprising:
Providing a group III nitride substrate having a main surface including a plurality of high dislocation areas and a low dislocation area surrounding the high dislocation area, wherein the defect density in the high dislocation area is larger than the defect density in the low dislocation area The high dislocation areas are distributed with a defect area surface density D (H) on the main surface,
And a step of growing a gallium nitride film on the principal surface of the group III nitride substrate at a growth rate of 3 micrometers / hour or more, and the surface of the gallium nitride film has pits distributed at a pit surface density D (P). And a ratio (D (P) / D (H)) of the pit surface density D (P) to the defect area surface density D (H) is larger than zero and smaller than 0.8. . A method of manufacturing a nitride semiconductor device, comprising:
Preparing a group III nitride substrate having a main surface including a high dislocation area and a low dislocation area surrounding the high dislocation area, the defect density in the high dislocation area being greater than the defect density of the low dislocation area, High dislocation areas are distributed with a defect area surface density D (H) on the main surface,
A step of growing a gallium nitride film on the main surface of the group III nitride substrate at a growth temperature of 1050 degrees Celsius or higher, and the surface of the gallium nitride film has pits distributed at a pit surface density D (P) The ratio (D (P) / D (H)) of the pit surface density D (P) to the defect area surface density D (H) is greater than zero and less than 0.4. . A method of manufacturing a nitride semiconductor device, comprising:
Preparing a group III nitride substrate having a main surface including a high dislocation area and a low dislocation area surrounding the high dislocation area, the defect density in the high dislocation area being greater than the defect density of the low dislocation area, High dislocation areas are distributed with a defect area surface density D (H) on the main surface,
And gallium nitride is deposited on the main surface of the group III nitride substrate at a growth rate of 3 micrometers / hour or more to form a pit nitride film having a pit size of 5 micrometers or less. Method. A method of manufacturing a nitride semiconductor device, comprising:
Preparing a group III nitride substrate having a main surface including a high dislocation area and a low dislocation area surrounding the high dislocation area, the defect density in the high dislocation area being greater than the defect density of the low dislocation area, High dislocation areas are distributed with a defect area surface density D (H) on the main surface,
Depositing gallium nitride on the main surface of the group III nitride substrate at a growth temperature of 1050 degrees Celsius or higher to form a gallium nitride film having a maximum pit size of 5 micrometers or less. .   The method according to any one of claims 1 to 4, wherein the gallium nitride film has a thickness of 6 micrometers or less. The method further comprises a step of growing an Al _X Ga _1-X N film (0 <X ≦ 1) on the main surface of the group III nitride substrate prior to the growth of the gallium nitride film. Item 6. The method according to any one of Items 1 to 5. A group III nitride supporting substrate having a main surface including a plurality of high dislocation areas and a low dislocation area surrounding the high dislocation area, and a back surface opposite to the main surface;
A gallium nitride based semiconductor region comprising a gallium nitride layer provided on the III nitride support substrate;
A first electrode provided on the gallium nitride based semiconductor region;
A second electrode provided on the back surface of the group III nitride support substrate,
The defect density in the high dislocation area is larger than the defect density in the low dislocation area, and the high dislocation area is distributed at the defect surface density D (H) in the main surface,
The thickness of the gallium nitride based semiconductor region is T micrometers;
The surface of the uppermost layer of the gallium nitride based semiconductor region has pits distributed at a pit surface density D (P) smaller than the defect area surface density D (H),
The size of the pits on the surface ranges from 1 micrometer to 10 micrometers;
The nitride semiconductor device according to claim 1, wherein the depth of the pits on the surface is in a range of 0.1 micrometers or more and T micrometers or less.   The ratio (D (P) / D (H)) of the pit surface density D (P) to the defect area surface density D (H) is larger than zero and smaller than 0.8. The described nitride semiconductor device.   The ratio (D (P) / D (H)) of the pit surface density D (P) to the defect area surface density D (H) is larger than zero and smaller than 0.4. The described nitride semiconductor device.   The nitride semiconductor device according to any one of claims 7 to 9, wherein the maximum size of the pits on the surface is 5 micrometers or less. The pit surface density D (P) is greater than zero and less than 800 cm ⁻² ;
10. The nitride semiconductor device according to claim 7, wherein a chip area of the nitride semiconductor device is 0.1225 square millimeters or less. The pit surface density D (P) is greater than zero and less than 25 cm ⁻² ;
The nitride semiconductor device according to any one of claims 7 to 9, wherein a chip area of the nitride semiconductor device is 4 square millimeters or less.   The nitride semiconductor device according to any one of claims 7 to 12, wherein the gallium nitride layer has a thickness of 6 micrometers or less. The Al _X Ga _1-X N layer (0 <X <1) provided between the Group III nitride supporting base and the gallium nitride layer is further provided. A nitride semiconductor device according to claim 1.

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