JP2002253755A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine having excellent recyclability since a lot of parts are usable versatilely, and also are hardly criminally altered. SOLUTION: A main control board 1 is constituted to be divided into the first board 1a provided with a memory part for storing a control program and a CPU for executing the control program and the second board 1b for receiving a control command from the first board 1a and transmitting information from a game panel to the first board. In the first board 1a, an unused terminal among the output terminals of address decoders 20 and 21 is connected directly or indirectly to a connector CN1. In the second board 1b, a connector CN2 corresponding to the output terminal of an unused address decoder is connected to the ground through a protection resistor (r).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine such as a pachinko machine, a spinning-type game machine, an arrangement ball machine, a sparrow ball game machine and the like, and more particularly, to a game machine excellent in recyclability and less likely to be tampered with. It is about.

[0002]

2. Description of the Related Art Among popular entertainment devices, pachinko machines and the like are widely and generally popular as prizes that can be obtained if they are lucky or more. In this pachinko machine, various characters appear on a liquid crystal screen or the like, and the progress of the game is exciting.

[0003] Players who enjoy such gaming machines generally tend to always desire new game characteristics. Therefore, in the gaming hall, new models are successively introduced to meet the expectations of the players. Therefore, a gaming machine such as a pachinko machine is actually removed from a gaming hall within a relatively short period of time regardless of its durability.

[0004]

Therefore, how to dispose of a gaming machine to be removed from a game hall is a major problem. Considering that disposal and incineration require a considerable cost, all the game halls need to be disposed of. Can not expect proper processing. Therefore, it is necessary for a game machine maker to tackle the problem of recycling game machines from the front, and it is necessary to construct a reliable recycling system and complete easily recyclable equipment in terms of equipment design. That is, the circuit design should be designed so as to provide new models having different game characteristics one after another and to respond to the demands of players, and to include many parts that can be used for general purposes in consideration of recyclability. However, the gaming machine must not be easily remodeled because of its recyclability.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a gaming machine which includes many parts which can be used for general purposes, has excellent recyclability, and is difficult to be tampered with. I do.

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a lottery for selectively generating a first state which is advantageous to a player and a second state which is disadvantageous for a player. In a gaming machine that controls a game operation based on a result of the lottery, a main control circuit 1 that mainly implements a game operation in accordance with a control program stored in a memory, and receives a control command from the main control circuit 1. Sub-control circuits 2 to 5 which operate by
Transmits a control command from the first substrate 1a including a memory unit storing a control program and a CPU for executing the control program, and transmits information received from the outside to the first substrate 1a. It is divided into a second substrate 1b and a plurality of substrates. It is preferable that the sub-control circuit in the present invention includes a payout control circuit for realizing a payout operation of the game medium.

Further, according to the present invention, a lottery for selectively generating a first state which is advantageous to the player and a second state which is disadvantageous for the player is performed, and the game operation is controlled based on the result of the lottery. The gaming machine includes a main control circuit 5 that mainly performs a payout operation according to a control program stored in a memory, and a sub-control circuit 7 that operates in response to a command signal from the main control circuit. The main control circuit 5 includes a first substrate including a memory unit that stores a control program and a CPU that executes the control program, and receives a command signal from the first substrate, and transmits information received from the outside to the first substrate. It is composed of a plurality of substrates divided into a second substrate to be transmitted. In the embodiment, the main control circuit and the sub-control circuit of the present invention are mounted on a payout control board and a firing control board.

In any case, according to the first or second aspect of the present invention, since the main control circuit is composed of a plurality of substrates (including the case of three or more), if the control program is rewritten, the first A new gaming machine can be realized without changing the circuit configuration of the board. That is, the first substrate can be used irrespective of the model change, so that the first substrate can be recycled.

In the above invention, in the first substrate,
Of the output terminals of the address decoder, unused terminals are also directly or indirectly connected to the first board connector terminal CN1, and in the second board, the second board connector terminal C
It is preferable that an input terminal of N2 corresponding to an output terminal of the unused address decoder is connected to the ground directly or through a protection element. In this case, an illegal game operation using an unused terminal can be prevented.

[0010] The protection element is preferably a fixed resistor, and the resistance value of the protection element is the first resistance connected to the protection element.
The minimum value is set in consideration of the maximum rated current of the circuit element on the substrate side. In this case, even if the program on the first substrate side runs away, the elements on the first substrate side will not be damaged.

It is preferable that a part of the output signal of the address decoder is supplied to the gate circuit G1 so as to be output to the first substrate connector CN1 in accordance with the data write operation of the CPU. Similarly, a signal that changes in accordance with the data reading operation of the CPU is supplied to the first board connector, and a part of the output signal of the address decoder is directly supplied to the first board connector CN1. Is preferred.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in more detail with reference to embodiments. FIG. 1 is a circuit configuration diagram illustrating a control system of the pachinko machine according to the present embodiment. This pachinko machine has a main control board 1 consisting of two boards, a symbol control board 2, a voice control board 3, a lamp control board 4, and a payout control board 5 as main components, It is composed of a computer circuit including a CPU, a ROM, and a RAM. The main control board 1 includes a first board 1a and a second board 1b, and is a part that mainly controls a game operation. The other control boards 2 to 5 are configured to receive a control command from the main control board 1 (specifically, the second board 1b) and implement a predetermined game operation.

The symbol control board 2 is a board for driving the LCD monitor 8. For example, when a game ball enters a winning opening, the symbol control board 2 is driven in accordance with a control command from the main control board 1.
The contents of the screen of the CD monitor 8 are variably displayed. The voice control board 3 and the lamp control board 4 are respectively connected to the main control board 1
According to the control command from the player, the game operation is audibly or visually raised.

The payout control board 5 operates in accordance with the control command from the main control board 1, and receives a switch input such as a prize ball counting switch to realize the payout of a predetermined number of prize balls. Note that the payout control board 5 also receives information from an out-of-supply detection switch, a lower tray switch, a ball lending counting switch, and the like. Further, the payout control board 5 outputs a command signal (a firing permission signal) to the firing board 7, and the firing control board 7 has a function of firing a game ball in response to an operation of the player. . In FIG. 1, the power supply board 6 is a part that receives AC 24 V and supplies a DC voltage to each unit of the apparatus.

FIG. 2 shows the internal configuration of the main control board 1. As illustrated, the main control board 1 is configured by connecting a first board 1a and a second board 1b by connectors CN1 and CN2 and a cable CBL. The first substrate 1a receives a DC voltage from the power supply substrate 6 and supplies it to each unit. A reset circuit unit 11 for generating a Maskable Interrupt (Signalable Interrupt) signal, a CPU circuit unit 12 including a CPU, a ROM, a RAM, and other ICs, and a decode circuit unit 13 for decoding an address signal and generating a chip select signal CS. ing.

The second board 1b has a function of transmitting a control command received from the first board 1a to each of the control boards 2 to 5,
It has a function of transmitting a switch signal from a winning opening, a tulip or the like arranged on the game board to the first substrate 1a. For this reason, the second board 1b has an output port circuit section 14 for outputting control data from the first board 1a to the other control boards 2 to 5, and an input for receiving data from various game components arranged on the game board. It comprises a port circuit section 15, an output drive circuit section 16 which is an output drive interface section, and a switch input circuit section 17 which is an input interface section with switches.

FIG. 3 shows the output section of the decode circuit section 13 and the second section.
3 illustrates an input unit of the substrate 1b. First substrate 1
a is terminated at the connector CN1 through the address decoders 20, 21 and a number of OR gates G1... G1. The address decoders 20 and 21 are, for example, HD74
It is an HC 138P (3-8 line decoder), and the lower three bits AB0 to AB2 of the address bus of the CPU are connected to the selection input terminal ABC. Further, the chip select signal CS generated by the first substrate 1a is supplied to the enable terminal G2B.

The input to the enable terminals G1 and G2A is 2
In this case, the address decoders AB3 and AB4 of the address bus are supplied to the address decoder 20, and the address buses AB4 and AB3 of the address bus are supplied to the address decoder 21.
Are supplied. Therefore, the voltage levels of the lower 5 bits of the address bus are LHLLL to LH
If it is HHH, the decoder 20 functions and the corresponding bits of Y0 to Y7 become L level. On the other hand, the voltage level of the lower 5 bits of the address bus is HLLLLL to HLLL.
If it is HHH, the decoder 21 functions and the corresponding bits of Y0 to Y7 become L level.

The output signals of the address decoders 20 and 21 are used as chip select signals in the second substrate 1b, and some of the chip select signals CS _{0 to} CS _n-1.
Is supplied to the OR gate G1 together with the XWR signal,
The output of the gate G1 is supplied to the connector CN1 as the chip select signal CS ₀ ~CS _n-1 for the output port.

In the case of this embodiment, the second substrate 1b is actually used.
Although less than N chip select signals are required,
By rewriting the control program, the first substrate 1
In order to use a for general purpose, the maximum number of chip
Connect signal CS₀~ CS_n-1Is output. What
The XWR signal indicates that the data bus is a write cycle.
Signal indicating that the
Select signal CS ₀~ CS_n-1Indicates that the CPU
When the power command (OUT command) is executed,
Will change to a bell.

The remaining chip select signals CS _{n to} CS _m generated by the address decoders 20 and 21 are transmitted to the second substrate 1
b is directly supplied to the connector CN1 as a chip select signal for the input port. All of the chip select signals CS _{n to} CS _m are also transferred to the second substrate 1.
Although not used in b, the maximum number of chip select signals CS _{n to} CS _m is intentionally output in order to use the first substrate 1a for general purpose by rewriting the control program.

A data bus (not shown) is connected to the connector CN1 so that 8-bit data can be exchanged with the second board 1b. The RD signal is also output to the connector CN1 in order to activate the bus buffer 23 when the CPU executes a data input command (IN command) or the like.

On the second substrate 1b, a number of D-type flip-flops 22 are provided as output ports, and a number of bus buffers 23 are provided as input ports. The D-type flip-flop 22 is, for example, an HD74H
C273P, a D input terminal D8-D1 receives a signal on the data bus, and a clock terminal CK
Receiving chip select signal CS _i for output ports generated in the substrate 1a. Here, the D-type flip-flop 22 reads the data of the D input terminals D8 to D1 when the signal of the clock terminal CK rises,
Chip select signal C
Because S _i falls, in accordance with the timing, the data first substrate 1a has outputted the D-type flip-flop 2
2 will be read.

The bus buffer 23 is, for example, TC74H
C541AP. This bus buffer 23 includes G1,
When both the G2 input terminals become L level, YA8-YA1
The data of the input terminal is output to the Y8-Y1 output terminal. The G1 input terminal has a connector C
Through N2, CN1, the chip select signal CS _j for the input ports are supplied. Further, the G2 terminal is connected to the RD from the first substrate 1a through the connectors CN2 and CN1.
A signal is being supplied. Therefore, the chip select signal CS _{j is} synchronized with the execution of the IN instruction or the like by the CPU.
Falls, the G1 and G2 input terminals are both at the L level, so that the output value of the bus buffer 23 changes at this timing. Since there is a connection cable connected to the data bus between the connectors CN2 and CN1, the output of the bus buffer 23 is read by the CPU.

The data input / output operation is performed as described above. This embodiment is also characterized by a method of terminating unused terminals. As described above, in this embodiment, even if the circuit configuration of the second substrate 1b is changed according to the type of the pachinko machine, the first substrate 1a is used for general purpose, and therefore the maximum number of chip select signals CS ₀ ~CS _n-1 and CS _n ~C
_Sm is output.

For this reason, an unused chip select signal may be generated. All terminals corresponding to the unused chip select signal are dropped to the ground via the protection resistor r on the second substrate side 1b. Like that. Here, the value of the protection resistor r is set to a value that is equal to or less than the maximum rated current even when an H-level voltage is output from the corresponding element (the OR gate G1 or the decoder 21 in this example) on the first substrate 1a side. Is set to Therefore, even if the CPU runs away on the first substrate side 1a and an H level voltage is output from the OR gate G1 or the decoder 21, there is no risk that these ICs may be damaged.

It is preferable that the minimum value of the resistance of the protection resistor is selected so that a voltage lower than the threshold level can always be output. The first
In the case where a current limiting element or circuit is built in the corresponding element on the substrate 1a side, without using the protection resistor r,
It is preferable that all terminals corresponding to unused chip select signals are directly connected to the ground.

As described above, in this embodiment, since the terminal corresponding to the unused chip select signal is connected to the ground directly or through the minimum protection resistor, the game is performed using the unused chip select signal. It is not possible to illegally operate the machine to obtain an unfair prize ball. For example, if the terminal corresponding to the unused chip select signal is open or pulled up, the unauthorized modification program is executed on the first substrate 1a, and the unused chip select signal is connected to the connector. It is possible that another illegal board is received from the CN 2 and an illegal command is sent to the payout control board 5. However, with the configuration of the present embodiment, such an illegal act is practically impossible. That is, the terminal corresponding to the unused chip select signal is grounded directly or through a minimum protection resistor, and cannot output an H-level signal. Therefore, the protection resistor is formed by leaving a scratch on the second substrate. Unless excluded, the above illegal activities cannot be realized.

Although the embodiments of the present invention have been described above, the specific description is not particularly intended to limit the present invention. For example, the circuit configuration of the first substrate can be changed as appropriate, and the CPU circuit unit may be configured with a plurality of ICs or a one-chip microcomputer. In the embodiment, the chip select signal has been described. However, it is preferable that unused signals transmitted between the first substrate and the second substrate are similarly terminated. Although a D-type flip-flop is illustrated as an output port and a bus buffer is illustrated as an input port, it is needless to say that other circuit configurations may be employed.

[0030]

As described above, according to the present invention,
It is possible to realize a gaming machine that is improved to include many parts that can be used for general purposes and that is difficult to be illegally modified.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a pachinko machine according to an embodiment.

FIG. 2 is a block diagram illustrating a circuit configuration of a main control board.

FIG. 3 is a block diagram showing the circuit configuration of a main control board in more detail.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Main control circuit (main circuit board) 2 Sub-control circuit 1a 1st board 1b 2nd board

Claims (6)

[Claims] 1. A gaming machine which performs a lottery for selectively generating a first state which is advantageous to a player and a second state which is disadvantageous for a game, and controls a game operation based on the result of the lottery. A main control circuit 1 that mainly implements a game operation in accordance with a control program stored in a memory, and a sub-control circuit 2 that operates in response to a control command from the main control circuit 1
The main control circuit 1 includes: a first substrate 1a including a memory unit that stores a control program and a CPU that executes the control program; and a control board that receives a control command from the first substrate 1a. A gaming machine comprising a plurality of substrates divided into a second substrate 1b for transmitting information received from the outside to a first substrate 1a. 2. A gaming machine which performs a lottery for selectively generating a first state which is advantageous to a player and a second state which is disadvantageous for a game, and controls a game operation based on the result of the lottery. A main control circuit that mainly performs a payout operation in accordance with a control program stored in a memory; and a sub-control circuit that operates in response to a command signal from the main control circuit. A first substrate including a memory unit for storing a control program and a CPU for executing the control program; and a second substrate for receiving command signals from the first substrate and transmitting information received from the outside to the first substrate. A gaming machine characterized by comprising a plurality of substrates divided into a plurality of substrates. 3. In the first board, output terminals of the address decoder are directly or indirectly connected to the first board connector terminal CN1, including unused terminals, and in the second board, 3. The gaming machine according to claim 1, wherein an input terminal corresponding to an output terminal of the unused address decoder among the second board connector terminals CN2 is connected to a ground directly or through a protection element. 4. The protection element is a fixed resistor, and a resistance value thereof is set to a minimum value in consideration of a maximum rated current of a circuit element on a first substrate connected to the protection element. Item 3. The gaming machine according to Item 3. 5. The gate circuit G1 according to claim 3, wherein a part of the output signal of the address decoder is supplied to the first substrate connector CN1 in accordance with a data write operation of the CPU. Gaming machine. 6. A signal which changes in accordance with a data read operation of a CPU is supplied to the first board connector,
The gaming machine according to any one of claims 3 to 5, wherein a part of the output signal of the address decoder is directly supplied to the first board connector CN1.