JP2002237469A - Method for forming metal gate of semiconductor element - Google Patents
Method for forming metal gate of semiconductor elementInfo
- Publication number
- JP2002237469A JP2002237469A JP2001393197A JP2001393197A JP2002237469A JP 2002237469 A JP2002237469 A JP 2002237469A JP 2001393197 A JP2001393197 A JP 2001393197A JP 2001393197 A JP2001393197 A JP 2001393197A JP 2002237469 A JP2002237469 A JP 2002237469A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- film
- source
- metal
- metal film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 81
- 239000002184 metal Substances 0.000 title claims abstract description 81
- 238000000034 method Methods 0.000 title claims abstract description 68
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 230000004888 barrier function Effects 0.000 claims abstract description 26
- 238000000151 deposition Methods 0.000 claims abstract description 20
- 230000008021 deposition Effects 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 230000003647 oxidation Effects 0.000 claims abstract description 8
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims description 9
- 239000010937 tungsten Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- SDTMFDGELKWGFT-UHFFFAOYSA-N 2-methylpropan-2-olate Chemical compound CC(C)(C)[O-] SDTMFDGELKWGFT-UHFFFAOYSA-N 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 239000002243 precursor Substances 0.000 claims description 3
- 238000010926 purge Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- -1 tungsten nitride Chemical class 0.000 claims description 3
- 229910015275 MoF 6 Inorganic materials 0.000 claims description 2
- 229910010037 TiAlN Inorganic materials 0.000 claims description 2
- 238000000231 atomic layer deposition Methods 0.000 claims 4
- 238000000663 remote plasma-enhanced chemical vapour deposition Methods 0.000 claims 3
- 229910019001 CoSi Inorganic materials 0.000 claims 1
- 241001663154 Electron Species 0.000 claims 1
- 229910005883 NiSi Inorganic materials 0.000 claims 1
- 229910010038 TiAl Inorganic materials 0.000 claims 1
- 229910008484 TiSi Inorganic materials 0.000 claims 1
- 230000005284 excitation Effects 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 238000006731 degradation reaction Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 119
- 229910052814 silicon oxide Inorganic materials 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 10
- 239000000463 material Substances 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000001976 improved effect Effects 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000197 pyrolysis Methods 0.000 description 2
- MNWRORMXBIWXCI-UHFFFAOYSA-N tetrakis(dimethylamido)titanium Chemical compound CN(C)[Ti](N(C)C)(N(C)C)N(C)C MNWRORMXBIWXCI-UHFFFAOYSA-N 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 101100454433 Biomphalaria glabrata BG01 gene Proteins 0.000 description 1
- 229910019044 CoSix Inorganic materials 0.000 description 1
- 108010063256 HTLV-1 protease Proteins 0.000 description 1
- 229910003855 HfAlO Inorganic materials 0.000 description 1
- 101000650817 Homo sapiens Semaphorin-4D Proteins 0.000 description 1
- 229910021193 La 2 O 3 Inorganic materials 0.000 description 1
- 102100027744 Semaphorin-4D Human genes 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 229910008486 TiSix Inorganic materials 0.000 description 1
- 229910007875 ZrAlO Inorganic materials 0.000 description 1
- 229910006501 ZrSiO Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 229910052953 millerite Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229960005235 piperonyl butoxide Drugs 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000003949 trap density measurement Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体素子の金属ゲ
ート形成方法に関し、特にゲート絶縁膜の特性低下を防
止することが可能な半導体素子の金属ゲート形成方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a metal gate of a semiconductor device, and more particularly to a method of forming a metal gate of a semiconductor device capable of preventing deterioration of characteristics of a gate insulating film.
【０００２】[0002]
【従来の技術】周知の如く、ＭＯＳＦＥＴにおけるゲー
ト絶縁膜の材料としては、熱酸化によるシリコン酸化膜
ＳｉＯ2が、ゲートの材料としてはポリシリコン膜が主
に用いられてきた。ところで、半導体素子の集積度が増
加するにつれて、ゲートの線幅は勿論、ゲート絶縁膜の
膜厚減少が共に要求されている。しかし、ゲート絶縁膜
の材料としてシリコン酸化膜が用いられる場合、ゲート
絶縁膜の膜厚が薄すぎるとと、前記ゲート絶縁膜を介し
てダイレクトトンネリング(direct tunneling)による漏
洩電流が大きくなるため、結果として素子特性が不安定
になる。2. Description of the Related Art As is well known, a silicon oxide film SiO 2 formed by thermal oxidation has been mainly used as a material of a gate insulating film in a MOSFET, and a polysilicon film has been mainly used as a material of a gate. By the way, as the degree of integration of semiconductor elements increases, not only the line width of the gate but also the thickness of the gate insulating film must be reduced. However, when a silicon oxide film is used as the material of the gate insulating film, if the thickness of the gate insulating film is too small, the leakage current due to direct tunneling through the gate insulating film (direct tunneling) increases, and as a result, As a result, the device characteristics become unstable.
【０００３】例えば、現在量産中のＤＲＡＭ及び論理素
子のゲート絶縁膜としてシリコン酸化膜を７０ｎｍテク
ノロジー(technology)素子に適用するに際して、ＤＲＡ
Ｍの場合には３０〜３５Å程度の厚さが、論理素子の場
合には１３〜１５Å程度の厚さが予想されるところ、ゲ
ートポリデプレション(gate poly depletion)によって
増加するキャパシタ成分が３〜８Å程度までとなり、１
５〜３０Å程度のゲート酸化膜の占める電気的な厚さ
（Ｔｅｆｆ）を減少させるには困難であった。For example, when a silicon oxide film is applied to a 70-nm technology device as a gate insulating film of a DRAM and a logic device currently mass-produced, a DRA is used.
In the case of M, a thickness of about 30 to 35 ° is expected, and in the case of a logic element, a thickness of about 13 to 15 ° is expected. However, a capacitor component which increases due to gate poly depletion is 3 to 35 °. Up to about 8Å
It has been difficult to reduce the electrical thickness (Teff) occupied by the gate oxide film of about 5 to 30 °.
【０００４】従って、かかる問題を克服するための方法
の一環として、最近はシリコン酸化膜より相対的に誘電
率の高い高誘電物質をゲート絶縁膜の材料として用いる
研究が行われている。また、ポリゲートデプレションを
最小化するためにポリゲートの代わりに金属ゲートを利
用しようとする研究が行われている。Therefore, as a part of a method for overcoming such a problem, recently, a study has been conducted using a high dielectric substance having a higher dielectric constant than a silicon oxide film as a material of a gate insulating film. In addition, research has been conducted to use a metal gate instead of a poly gate to minimize poly gate depletion.
【０００５】前記金属ゲートの場合、ゲート用金属膜と
ゲート絶縁膜との間にはバリヤ金属としてＴｉＮまたは
ＷＮ膜が介在され、ゲート用金属膜上にはエッチングマ
スクとして用いるためのハードマスク膜が配置される。In the case of the metal gate, a TiN or WN film as a barrier metal is interposed between the gate metal film and the gate insulating film, and a hard mask film for use as an etching mask is formed on the gate metal film. Be placed.
【０００６】ところが、従来の技術によってシリコン酸
化膜材質のゲート絶縁膜上に金属ゲートを形成する場合
には、次のようにゲート絶縁膜の特性の低下が生ずると
いう問題点がある。However, when a metal gate is formed on a gate insulating film made of a silicon oxide film by a conventional technique, there is a problem that the characteristics of the gate insulating film deteriorate as follows.
【０００７】通常、ゲート用金属膜の蒸着はスパッタリ
ング(sputtering)またはＣＶＤ工程によって行われる
が、この際、前記ゲート用金属膜、特にバリヤ金属膜を
ゲート酸化膜上に直接蒸着する場合、前記ゲート絶縁膜
の界面特性及び絶縁特性の低下が生ずる。Usually, the deposition of the gate metal film is performed by sputtering or a CVD process. In this case, when the gate metal film, particularly, the barrier metal film is directly deposited on the gate oxide film, the gate metal film is deposited. The interface characteristics and insulating characteristics of the insulating film are reduced.
【０００８】図１ａ及び図１ｂは従来の技術によってス
パッタリングを用いてシリコン酸化膜からなるゲート絶
縁膜上に直接バリヤ金属膜としてＴｉＮまたはＷＮ膜を
使用し、ゲート用金属膜としてタングステン（Ｗ）膜を
順次蒸着した場合におけるＭＯＳキャパシタのＣ-Ｖ(Ca
pacitance-Voltage)曲線を示すグラフである。FIGS. 1A and 1B show a conventional technique in which a TiN or WN film is directly used as a barrier metal film on a gate insulating film made of a silicon oxide film by sputtering, and a tungsten (W) film is used as a gate metal film. Are sequentially deposited, the CV (Ca
3 is a graph showing a pacitance-voltage curve.
【０００９】同図に示すように、シリコン酸化膜からな
るゲート絶縁膜上にバリヤ金属膜（ＴｉＮまたはＷＮ）
とタングステン膜を連続して蒸着する場合、後続の熱工
程が行われていない状態では、Ｃ-Ｖ特性が蒸着物質
（ＴｉＮまたはＷＮ）及びスパッタリング法(IMP, coll
imated, conventional)に大きく拘ることなく、ハンプ
(hump)とヒステリシス(hysteresis)によって１Ｅ１２／
ｅＶ-ｃｍ2程度の過度なインタフェーストラップ密度(i
nterface trap density)と１Ｅ１２／ｃｍ2程度の酸化
物トラップチャージ(oxide trap charge)が現れる。こ
れにより、酸化物ディフェクトチャージがハイレベルに
なり、ゲート絶縁膜自体の損傷は勿論、基板との界面に
おいて望ましくない損傷を生じさせる。As shown in FIG. 1, a barrier metal film (TiN or WN) is formed on a gate insulating film made of a silicon oxide film.
In the case where a tungsten film is continuously deposited, a CV characteristic is determined by a deposition material (TiN or WN) and a sputtering method (IMP, coll) when a subsequent thermal process is not performed.
imated, conventional)
(Hump) and hysteresis (1E12 /
Excessive interface trap density of eV-cm 2 (i
An oxide trap charge of about 1E12 / cm 2 appears. As a result, the oxide defect charge becomes high level, causing not only damage to the gate insulating film itself but also undesirable damage at the interface with the substrate.
【００１０】一方、前述した損傷は８００℃以上の高温
熱工程によってある程度治癒することができるが、完璧
なゲート絶縁膜の損傷回復は期待することができない。
特に、高温の熱工程を行わなければならないという工程
上の短所、及びゲート絶縁膜の電気的の厚さ（Ｔｅｆ
ｆ）が増加するという短所がある。On the other hand, the above-mentioned damage can be healed to some extent by a high-temperature heating step of 800 ° C. or more, but complete recovery of the damage of the gate insulating film cannot be expected.
In particular, a disadvantage in that a high-temperature thermal process must be performed, and the electrical thickness of the gate insulating film (Tef)
f) has the disadvantage of increasing.
【００１１】図２ａ及び図２ｃは６５０℃の高温でＴｉ
Ｃｌ4＋ＨＮ3の熱分解方式で蒸着されたＴｉＮ金属ゲー
トにおけるＣ-Ｖ曲線を示すグラフである。FIGS. 2a and 2c show the results at high temperatures of 650 ° C.
4 is a graph showing a CV curve of a TiN metal gate deposited by a thermal decomposition method of Cl 4 + HN 3 .
【００１２】同図に示すように、蒸着後のＭＯＳトラン
ジスタの特性は、スパッタリング法によって蒸着された
ものより相対的に良好である。しかし、後続する熱工程
の後、ゲート絶縁膜の電気的厚さ（Ｔｅｆｆ）の増加と
酸化物トラップチャージの増加、即ちヒステリシスの増
加によってＧＯＩ(Gate Oxide Integrity)の特性劣化が
来され、特にＭＯＳキャパシタトランジスタの製造時に
無視できない特性劣化が生ずる虞がある。As shown in FIG. 1, the characteristics of the MOS transistor after the deposition are relatively better than those deposited by the sputtering method. However, after a subsequent thermal process, an increase in the electrical thickness (Teff) of the gate insulating film and an increase in the oxide trap charge, that is, an increase in the hysteresis, degrade the characteristics of GOI (Gate Oxide Integrity). There is a possibility that characteristic degradation that cannot be ignored during the production of the capacitor transistor may occur.
【００１３】[0013]
【発明が解決しようとする課題】従って、本発明は、か
かる問題点を解決するためのもので、その目的はゲート
絶縁膜の特性低下を防止することが可能な金属ゲート形
成方法を提供することにある。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method of forming a metal gate capable of preventing a deterioration in characteristics of a gate insulating film. It is in.
【００１４】[0014]
【課題を解決するための手段】上記目的を達成するため
に、本発明の金属ゲート形成方法は、アクティブ領域を
限定するトレンチ型の素子分離膜が備えられたシリコン
基板を提供する段階と、前記シリコン基板の表面上に熱
酸化工程によってゲート絶縁膜を形成する段階と、前記
ゲート絶縁膜上にバリヤ金属膜とゲート用金属膜を順次
蒸着する段階と、前記ゲート用金属膜、バリヤ金属膜及
びゲート絶縁膜をパターニングする段階とを含み、前記
バリヤ金属膜とゲート用金属膜の蒸着は原子層成長(Ato
mic layer deposition：ＡＬＤ)工程、またはリモート
プラズマＣＶＤ工程で行うことを特徴とする。In order to achieve the above object, a method of forming a metal gate according to the present invention comprises the steps of providing a silicon substrate provided with a trench type element isolation film defining an active region; Forming a gate insulating film on the surface of the silicon substrate by a thermal oxidation process, sequentially depositing a barrier metal film and a gate metal film on the gate insulating film; and forming the gate metal film, the barrier metal film and Patterning a gate insulating film, wherein the deposition of the barrier metal film and the gate metal film is performed by atomic layer growth (Ato).
(mic layer deposition: ALD) process or a remote plasma CVD process.
【００１５】本発明によれば、バリヤ金属膜とゲート用
金属膜をＡＬＤ工程またはリモートプラズマＣＶＤ工程
で蒸着するため、前記膜の蒸着過程中に発生する虞のあ
るゲート絶縁膜の損傷を最大限抑制することができる。According to the present invention, since the barrier metal film and the gate metal film are deposited by the ALD process or the remote plasma CVD process, damage to the gate insulating film which may occur during the deposition process of the film is minimized. Can be suppressed.
【００１６】[0016]
【発明の実施の形態】以下、本発明を添付図に基づいて
詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
【００１７】図３ａ乃至図３ｃは本発明の実施例による
金属ゲート形成方法を説明するための各工程別断面図で
ある。FIGS. 3A through 3C are cross-sectional views illustrating a method of forming a metal gate according to an embodiment of the present invention.
【００１８】図３ａを参照すると、シリコン基板１を用
意し、前記シリコン基板１の所定の領域にアクティブ領
域を限定するトレンチ型の素子分離膜２を形成する。こ
の際、前記素子分離膜２は公知のＬＯＣＯＳ工程で形成
することも可能である。前記シリコン基板１の表面上に
熱酸化工程によって厚さ１０〜４０Åのシリコン酸化膜
からなるゲート絶縁膜３を形成する。この際、前記熱酸
化工程は６５０〜９００℃のファーネス(furnace)で湿
式（Ｈ2／Ｏ2）または乾式（Ｏ2）方式で行うことが好
ましい。Referring to FIG. 3A, a silicon substrate 1 is prepared, and a trench type element isolation film 2 for defining an active region is formed in a predetermined region of the silicon substrate 1. At this time, the device isolation film 2 can be formed by a known LOCOS process. A gate insulating film 3 made of a silicon oxide film having a thickness of 10 to 40 ° is formed on the surface of the silicon substrate 1 by a thermal oxidation process. In this case, the thermal oxidation process is preferably performed in a furnace at 650 to 900 ° C. by a wet (H 2 / O 2 ) or dry (O 2 ) method.
【００１９】一方、前記ゲート絶縁膜３として前記熱酸
化工程によるシリコン酸化膜の代わりに、Ａｌ2Ｏ3、Ｔ
ａ2Ｏ5、ＴｉＯ2、ＺｒＯ2、ＨｆＯ2、Ｚｒ-シリケー
ト、Ｈｆ-シリケート、Ｌａ2Ｏ3、及び３次元系混合絶
縁膜（ＺｒＡｌＯ、ＨｆＡｌＯ、ＺｒＳｉＯ4、ＨｆＳ
ｉＯ4）の中から選択されたいずれかの高誘電絶縁膜を
形成することも可能である。また、前記高誘電絶縁膜の
蒸着の前に超薄膜(ultra thin)のシリコン酸化膜を形成
することも可能である。しかも、前記高誘電絶縁膜をゲ
ート絶縁膜として用いる場合、その特性改善のために、
酸素、窒素又は非活性雰囲気で１０〜３００秒間の急速
熱工程、或いは１０〜１００分間のファーネス工程を用
いてアニーリングを行うことができると共に、ＵＶ-オ
ゾン処理を行うこともできる。On the other hand, instead of the silicon oxide film formed by the thermal oxidation step as the gate insulating film 3, Al 2 O 3 , T
a 2 O 5 , TiO 2 , ZrO 2 , HfO 2 , Zr-silicate, Hf-silicate, La 2 O 3 , and three-dimensional mixed insulating film (ZrAlO, HfAlO, ZrSiO 4 , HfS
It is also possible to form any high dielectric insulating film selected from iO 4 ). It is also possible to form an ultra-thin silicon oxide film before depositing the high dielectric insulating film. Moreover, when the high dielectric insulating film is used as a gate insulating film, to improve its characteristics,
Annealing can be performed using a rapid heating process for 10 to 300 seconds or a furnace process for 10 to 100 minutes in an oxygen, nitrogen or inert atmosphere, and UV-ozone treatment can also be performed.
【００２０】また、図示してはいないが、前記ゲート絶
縁膜３の形成の前、トレンチ構造でキャパシタを形成す
ることもでき、この際の誘電膜としてはＯＮ膜、Ｔａ2
Ｏ5膜、Ａｌ2Ｏ3膜、ＢＳＴ膜及びＳＢＴ膜の中から選
択されるいずれかを用いることができる。Although not shown, a capacitor having a trench structure can be formed before the gate insulating film 3 is formed. In this case, an ON film, Ta 2
Any one selected from an O 5 film, an Al 2 O 3 film, a BST film and an SBT film can be used.
【００２１】図３ｂを参照すると、前記ゲート絶縁膜３
上にバリヤ金属膜４とゲート用金属膜５を順次蒸着し、
前記ゲート用金属膜５上にハードマスク膜６を蒸着す
る。ここで、前記バリヤ金属膜４とゲート用金属膜５
は、金属浸透(metal penetration)または注入(implanta
tion)のような効果を加えないで、高温熱分解方式でな
い蒸着工程、例えばＡＬＤ工程またはリモートプラズマ
ＣＶＤ工程を使用するのが好ましい。Referring to FIG. 3B, the gate insulating film 3 is formed.
A barrier metal film 4 and a gate metal film 5 are sequentially deposited thereon,
A hard mask film 6 is deposited on the gate metal film 5. Here, the barrier metal film 4 and the gate metal film 5 are used.
Means metal penetration or injection (implanta
It is preferable to use a deposition process that is not a high-temperature pyrolysis method, such as an ALD process or a remote plasma CVD process, without adding an effect as described above.
【００２２】ここで、前記ＡＬＤ工程は１５０〜３５０
℃でサイクリックドージング(cyclic dosing)またはパ
ージング(purging)による蒸着が可能なので、ゲート絶
縁膜３と基板１間の界面及び前記ゲート絶縁膜３自体の
特性劣化を防止することができる。前記ＡＬＤ工程の
際、前駆体(precursor)をパージングする物質として、
Ｎ2、ＮＨ3またはＮＤ3のいずれかを使用し、温度５０
〜５５０℃（より好ましくは５０〜４５０℃）、圧力
０.０５〜３Ｔｏｒｒの条件で行うことが好ましい。Here, the ALD process is performed at 150 to 350.
Since deposition by cyclic dosing or purging can be performed at a temperature of ° C., the interface between the gate insulating film 3 and the substrate 1 and the characteristic deterioration of the gate insulating film 3 itself can be prevented. At the time of the ALD step, as a substance for purging a precursor (precursor),
Using either N 2 , NH 3 or ND 3 , at a temperature of 50
550 ° C. (more preferably 50 ° C. to 450 ° C.) and a pressure of 0.05 to 3 Torr.
【００２３】前記リモートプラズマＣＶＤ工程は、遠距
離でプラズマを形成して薄膜を蒸着するため、前記ＡＬ
Ｄ工程と同一の効果を得ることができる。前記リモート
プラズマＣＶＤ工程の際、プラズマソースとしてＥＣＲ
(Electron cyclotron Resonance)を使用し、周波数を
２.０〜９ＧＨｚとし、プラズマ励起ガスとしてＨｅ、
Ａｒ、ＫｒまたはＸｅを使用することが好ましい。ま
た、前記リモートプラズマＣＶＤ工程の際、Ｔｉのよう
な金属ソースのチャンバー内への注入はウェーハの付近
から噴射し、Ｎのソースはプラズマの付近で励起させて
ウェーハの付近に導入されるようにする。In the remote plasma CVD process, a plasma is formed at a long distance to deposit a thin film.
The same effect as in the step D can be obtained. In the remote plasma CVD process, ECR is used as a plasma source.
(Electron cyclotron Resonance), the frequency was 2.0 to 9 GHz, and He,
It is preferred to use Ar, Kr or Xe. In the remote plasma CVD process, a metal source such as Ti is injected into the chamber from the vicinity of the wafer, and the N source is excited near the plasma to be introduced near the wafer. I do.
【００２４】一方、前記バリヤ金属膜４は、ＴｉＮ、Ｔ
ｉＡｌＮ、ＴａＮ、ＭｏＮ及びＷＮからなる群より選択
されるいずれか一つで形成され、その厚さは５０〜５０
０Åにするのが好ましい。また、前記ゲート用金属膜５
はＷ、Ｔａ、Ａｌ、ＴｉＳｉｘ、ＣｏＳｉｘ及びＮｉＳ
ｉｘの中から選択されるいずれか一つで形成し、或いは
ポリシリコン、タングステン窒化膜及びタングステン膜
の積層構造(poly-Si/WN/W)で形成し、その厚さは３００
〜１,５００Å程度とするのが好ましい。前記ハードマ
スク膜６はシリコン酸化膜ＳｉＯ2、シリコン窒化膜Ｓ
ｉ3Ｎ4またはシリコン窒酸化膜ＳｉＯＮで形成し、３０
０〜２,０００Å程度の厚さにする。On the other hand, the barrier metal film 4 is made of TiN, T
iN, TaN, MoN, and WN.
Preferably, it is 0 °. The gate metal film 5
Are W, Ta, Al, TiSix, CoSix and NiS
ix, or a stacked structure of polysilicon, tungsten nitride film and tungsten film (poly-Si / WN / W), the thickness of which is 300
It is preferable that the angle be about 1,500 °. The hard mask film 6 includes a silicon oxide film SiO 2 and a silicon nitride film S
formed of i 3 N 4 or silicon oxynitride film SiON,
The thickness is about 0 to 2,000 mm.
【００２５】前記において、ＡＬＤ工程及び／またはリ
モートプラズマＣＶＤ工程でバリヤ金属膜、例えばＴｉ
Ｎの蒸着時には、ＴｉのソースとしてＴｉＣｌ4、ＴＤ
ＥＡＴまたはＴＤＭＡＴのいずれか一つを使用し、Ｎの
ソースとしてはＮ2、ＮＨ3またはＮＤ3のいずれか一つ
を使用する。また、バリヤ金属膜としてＴｉＡｌＮを蒸
着する場合、ＴｉのソースとしてはＴｉＣｌ4、ＴＤＥ
ＡＴまたはＴＤＭＡＴのいずれか一つを使用し、Ｎのソ
ースとしてはＮ2、ＮＨ3またはＮＤ3のいずれか一つを
使用し、ＡｌのソースとしてはＡｌＣｌ3またはＴＭＡ
[Ａｌ(ＣＨ3)3]を使用する。しかも、バリヤ金属膜とし
てＴａＮを蒸着する場合、ＴａのソースとしてはＴａＣ
ｌ4またはＴａ tert-butoxide（タート−ブトキシド）
を使用し、ＮのソースとしてはＮ2、ＮＨ3またはＮＤ3
のいずれか一つを使用する。また、バリヤ金属膜として
ＭｏＮを蒸着する場合、ＭｏのソースとしてはＭｏＣｌ
4、ＭｏＦ6またはＭｏ tert-butoxide（タート−ブトキ
シド）を使用し、ＮのソースとしてはＮ2、ＮＨ3または
ＮＤ3のいずれか一つを使用する。バリヤ金属膜として
ＷＮを蒸着する場合、ＷのソースとしてはＷＦ6または
ＷＣｌ4を使用し、ＮのソースとしてはＮ2、ＮＨ3また
はＮＤ3のいずれか一つを使用する。In the above, a barrier metal film such as Ti is used in the ALD process and / or the remote plasma CVD process.
During the deposition of N, TiCl 4 , TD
One of EAT or TDMAT is used, and one of N 2 , NH 3 and ND 3 is used as a source of N. When TiAlN is deposited as a barrier metal film, TiCl 4 , TDE
One of AT or TDMAT is used, one of N 2 , NH 3 or ND 3 is used as a source of N, and AlCl 3 or TMA is used as a source of Al.
[Al (CH 3 ) 3 ] is used. Moreover, when TaN is deposited as a barrier metal film, TaC is used as a Ta source.
l 4 or Ta tert-butoxide (Start - butoxide)
And the source of N is N 2 , NH 3 or ND 3
Use any one of When MoN is deposited as a barrier metal film, the source of Mo is MoCl.
4 , MoF 6 or Mo tert-butoxide is used, and one of N 2 , NH 3 and ND 3 is used as a source of N. When WN is deposited as a barrier metal film, WF 6 or WCl 4 is used as a source of W, and any one of N 2 , NH 3 or ND 3 is used as a source of N.
【００２６】図３ｃを参照すると、公知のフォトリソグ
ラフィ工程で前記ハードマスク膜６をパターニングす
る。その後、エッチングマスクとしてパターニングされ
たハードマスク膜６を用いたエッチング工程によって前
記ゲート用金属膜５、バリヤ膜４及びゲート絶縁膜３を
連続的にエッチングし、本発明による金属ゲート１０を
形成する。Referring to FIG. 3C, the hard mask film 6 is patterned by a known photolithography process. Thereafter, the gate metal film 5, the barrier film 4 and the gate insulating film 3 are successively etched by an etching process using a patterned hard mask film 6 as an etching mask to form a metal gate 10 according to the present invention.
【００２７】このような工程によって形成される本発明
の金属ゲート１０は、バリヤ金属膜４を含んだゲート用
金属膜５がＡＬＤ工程またはリモートプラズマＣＶＤ工
程で蒸着されることに起因して、シリコン酸化膜からな
るゲート絶縁膜３の特性低下を防止することができる。The metal gate 10 of the present invention formed by the above-described process is characterized in that the gate metal film 5 including the barrier metal film 4 is deposited by the ALD process or the remote plasma CVD process. It is possible to prevent the characteristics of the gate insulating film 3 made of an oxide film from being lowered.
【００２８】一方、前述した実施例では、典型的なゲー
ト形成工程、即ちゲート絶縁膜とゲート用導電膜を蒸着
した後パターニングすることによりゲートを形成する工
程について説明したが、犠牲ゲートの形成及び除去によ
ってゲート形成領域を限定した後、前記ゲート形成領域
に金属ゲートを形成するダマシン(damascene)工程にも
適用可能であり、特にバリヤ金属膜トゲート用金属膜の
蒸着にＡＬＤ工程またはリモートプラズマＣＶＤ工程を
用いる本発明の方法を、ダマシン工程を用いたゲート形
成工程に適用する場合、より向上した効果を得ることが
できる。On the other hand, in the above-described embodiment, a typical gate forming step, that is, a step of forming a gate by depositing a gate insulating film and a conductive film for a gate and then patterning the same, has been described. After the gate formation region is limited by the removal, the present invention can be applied to a damascene process of forming a metal gate in the gate formation region. In the case where the method of the present invention is applied to a gate forming step using a damascene process, more improved effects can be obtained.
【００２９】[0029]
【発明の効果】以上述べたように、本発明は、金属ゲー
トを形成するが、バリヤ金属膜とゲート用金属膜の蒸着
をＡＬＤ工程またはリモートプラズマＣＶＤ工程で行う
ことにより、ゲート絶縁膜の特性低下を防止することが
できるから、金属ゲートの特性は勿論のこと、素子の特
性を向上させることができる。さらに、前記ＡＬＤ工程
及びリモートプラズマＣＶＤ工程はステップカバレージ
(step coverage)に優れるから、それ自体で工程上の利
点がある。従って、高速／高密度素子の製造に極めて有
利に適用することができる。As described above, according to the present invention, the metal gate is formed. By depositing the barrier metal film and the metal film for the gate by the ALD process or the remote plasma CVD process, the characteristics of the gate insulating film can be improved. Since the lowering can be prevented, not only the characteristics of the metal gate but also the characteristics of the element can be improved. Further, the ALD process and the remote plasma CVD process are step coverage.
(step coverage), there is an advantage in the process itself. Therefore, it can be very advantageously applied to the production of high-speed / high-density elements.
【００３０】その他、本発明はその要旨から離脱しない
範囲内で、様々に変更して実施することができる。In addition, the present invention can be variously modified and implemented without departing from the gist thereof.
【図１】(a)及び(b)はそれぞれ、従来の技術によってス
パッタリングを用いてシリコン酸化膜上に直接ＴｉＮま
たはＷＮ膜とＷ膜を蒸着した場合におけるＣ-Ｖ曲線を
示すグラフである。FIGS. 1A and 1B are graphs showing CV curves when a TiN or WN film and a W film are directly deposited on a silicon oxide film by sputtering using a conventional technique.
【図２】(a)乃至(c)はそれぞれ、従来の技術によって６
５０℃でＴｉＣｌ4＋ＮＨ3の熱分解方式で蒸着されたＴ
ｉＮ金属ゲートにおけるＣ-Ｖ曲線を示すグラフであ
る。FIGS. 2 (a) to 2 (c) each show 6 figures according to a conventional technique.
T deposited by pyrolysis of TiCl 4 + NH 3 at 50 ° C.
It is a graph which shows the CV curve in an iN metal gate.
【図３】(a)乃至(c)はそれぞれ、本発明の実施例による
金属ゲート形成方法を説明するための各工程別断面図で
ある。FIGS. 3A to 3C are cross-sectional views for explaining a method of forming a metal gate according to an embodiment of the present invention.
１ シリコン基板 ２ 素子分離膜 ３ ゲート絶縁膜 ４ バリヤ金属膜 ５ ゲート用金属膜 ６ ハードマスク膜 １０ 金属ゲート DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation film 3 Gate insulating film 4 Barrier metal film 5 Metal film for gate 6 Hard mask film 10 Metal gate
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 29/78 (72)発明者 林 寛 容 大韓民国 京畿道 水原市 八達邑 霊通 洞 ファンコルマウルジョッコンアパート メント 139−1001 Ｆターム(参考） 4M104 BB01 BB02 BB17 BB18 BB20 BB21 BB25 BB30 BB31 BB32 BB33 BB36 CC05 FF18 GG09 GG14 GG16 5F083 AD01 AD15 GA09 GA27 JA02 JA03 JA06 JA12 JA13 JA14 JA35 JA36 JA39 JA40 NA01 PR12 PR21 PR22 PR34 PR40 5F140 AA00 AA01 AA39 AB09 AC32 AC33 BA01 BD01 BD05 BD11 BD12 BD13 BE07 BE09 BE13 BE17 BE18 BE19 BE20 BF04 BF10 BF11 BF15 BF17 BF18 BF20 BF21 BF27 BG01 BG27 BG28 BG36 BG39 CB01 CB04──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification code FI Theme Court ゛ (Reference) H01L 29/78 (72) Inventor Hiroshi Hayashi Republic of Korea Condominium 139-1001 F-term (reference) 4M104 BB01 BB02 BB17 BB18 BB20 BB21 BB25 BB30 BB31 BB32 BB33 BB36 CC05 FF18 GG09 GG14 GG16 5F083 AD01 AD15 GA09 GA27 JA02 JA03 JA06 JA12 JA13 PR14 5F140 AA00 AA01 AA39 AB09 AC32 AC33 BA01 BD01 BD05 BD11 BD12 BD13 BE07 BE09 BE13 BE17 BE18 BE19 BE20 BF04 BF10 BF11 BF15 BF17 BF18 BF20 BF21 BF27 BG01 BG27 BG28 BG36 BG39 CB01 CB04
Claims (12)
素子分離膜が備えられたシリコン基板を提供する段階
と、 前記シリコン基板の表面上に熱酸化工程によってゲート
絶縁膜を形成する段階と、 前記ゲート絶縁膜上にバリヤ金属膜とゲート用金属膜を
順次蒸着する段階と、 前記ゲート用金属膜、バリヤ金属膜及びゲート絶縁膜を
パターニングする段階とを含み、 前記バリヤ金属膜とゲート用金属膜の蒸着は原子層成長
（ＡＬＤ）工程及び／またはリモートプラズマ化学気相
成長（ＲＰＣＶＤ）工程で行うことを特徴とする半導体
素子の金属ゲート形成方法。Providing a silicon substrate provided with a trench-type device isolation film defining an active region; forming a gate insulating film on a surface of the silicon substrate by a thermal oxidation process; A step of sequentially depositing a barrier metal film and a gate metal film on an insulating film; and a step of patterning the gate metal film, the barrier metal film and the gate insulating film. A method of forming a metal gate for a semiconductor device, wherein the deposition is performed by an atomic layer deposition (ALD) process and / or a remote plasma enhanced chemical vapor deposition (RPCVD) process.
ファーネスで湿式（Ｈ2／Ｏ2）または乾式（Ｏ2）方式
で行うことを特徴とする請求項１記載の半導体素子の金
属ゲート形成方法。2. The metal gate of claim 1, wherein the thermal oxidation process is performed in a wet (H 2 / O 2 ) or dry (O 2 ) mode at a furnace temperature of 650 to 900 ° C. Forming method.
Ｎ、ＴａＮ、ＭｏＮ及びＷＮからなる群より選択される
いずれか一つであることを特徴とする請求項１記載の半
導体素子の金属ゲート形成方法。3. The barrier metal film is formed of TiN, TiAl.
2. The method according to claim 1, wherein the metal gate is selected from the group consisting of N, TaN, MoN, and WN.
体をパージングする物質としてＮ2、ＮＨ3またはＮＤ3
の中からいずれか一つを使用し、温度５０〜４５０℃、
圧力０.０５〜３Ｔｏｒｒの条件で行うことを特徴とす
る請求項１記載の半導体素子の金属ゲート形成方法。4. An atomic layer deposition (ALD) step, wherein N 2 , NH 3 or ND 3 is used as a substance for purging a precursor.
Using any one of the temperature of 50 ~ 450 ℃,
2. The method according to claim 1, wherein the method is performed under a pressure of 0.05 to 3 Torr.
ＰＣＶＤ）工程は、プラズマソースとしてＥＣＲ(Elect
ron Cyclotron Resonance)を使用し、周波数を２.０〜
９ＧＨｚとし、プラズマ励起ガスとしてＨｅ、Ａｒ、Ｋ
ｒまたはＸｅを使用することを特徴とする請求項１記載
の半導体素子の金属ゲート形成方法。5. The remote plasma enhanced chemical vapor deposition (R)
In the PCVD (Electro-Chemical Vapor Deposition) process, ECR (Elect
ron Cyclotron Resonance) and change the frequency to 2.0
9 GHz, He, Ar, K as plasma excitation gas
2. The method of claim 1, wherein r or Xe is used.
てはＴｉＣｌ4、ＴＤＥＡＴまたはＴＤＭＡＴのいずれ
か一つを使用し、ＮのソースとしてはＮ2、ＮＨ3または
ＮＤ3のいずれか一つを使用することを特徴とする請求
項３記載の半導体素子の金属ゲート形成方法。6. When depositing TiN, any one of TiCl 4 , TDEAT or TDMT is used as a source of Ti, and any one of N 2 , NH 3 or ND 3 is used as a source of N. 4. The method according to claim 3, wherein the metal gate is used.
としてはＴｉＣｌ4、ＴＤＥＡＴまたはＴＤＭＡＴのい
ずれか一つを使用し、ＡｌのソースとしてはＡｌＣ3、
ＴＭＡ[Ａｌ(ＣＨ3)3]を使用し、ＮのソースとしてはＮ
2、ＮＨ3またはＮＤ3のいずれか一つを使用することを
特徴とする請求項３記載の半導体素子の金属ゲート形成
方法。7. When depositing TiAlN, any one of TiCl 4 , TDEAT, and TDDMA is used as a Ti source, and AlC 3 ,
TMA [Al (CH 3 ) 3 ] is used, and the source of N is N
2, NH 3 or a metal gate formation method of a semiconductor device according to claim 3, wherein the use of any one of the ND 3.
てはＴａＣｌ4、またはＴａ tert-butoxideを使用し、
ＮのソースとしてはＮ2、ＮＨ3またはＮＤ3のいずれか
一つを使用することを特徴とする請求項３記載の半導体
素子の金属ゲート形成方法。8. When TaN is deposited, TaCl 4 or Ta tert-butoxide is used as a Ta source.
Metal gate formation method of a semiconductor device according to claim 3, wherein the as the N source that uses any one of N 2, NH 3 or ND 3.
てはＭｏＣｌ4、ＭｏＦ6、またはＭｏ tert-butoxideを
使用し、ＮのソースとしてはＮ2、ＮＨ3またはＮＤ3の
いずれか一つを使用することを特徴とする請求項３記載
の半導体素子の金属ゲート形成方法。9. During the deposition of MoN, MoCl 4 , MoF 6 , or Mo tert-butoxide is used as a source of Mo, and one of N 2 , NH 3, or ND 3 is used as a source of N. 4. The method according to claim 3, wherein the metal gate is used.
はＷＦ6またはＷＣｌ4を使用し、ＮのソースとしてはＮ
2、ＮＨ3またはＮＤ3のいずれか一つを使用することを
特徴とする請求項３記載の半導体素子の金属ゲート形成
方法。10. The method according to claim 10, wherein WF 6 or WCl 4 is used as a source of W and N is used as a source of N during the deposition of WN.
2, NH 3 or a metal gate formation method of a semiconductor device according to claim 3, wherein the use of any one of the ND 3.
ｌ、ＴｉＳｉX、ＣｏＳｉX及びＮｉＳｉXの中から選択
されるいずれか一つであることを特徴とする請求項１記
載の半導体素子の金属ゲート形成方法。11. The gate metal film is made of W, Ta, A.
2. The method as claimed in claim 1, wherein the metal gate is selected from the group consisting of l, TiSi x , CoSi x and NiSi x .
タングステン窒化膜及びタングステン膜の積層構造から
なることを特徴とする請求項１記載の半導体素子の金属
ゲート形成方法。12. The gate metal film is polysilicon,
2. The method according to claim 1, wherein the metal gate has a stacked structure of a tungsten nitride film and a tungsten film.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2000-85582 | 2000-12-29 | ||
| KR1020000085582A KR20020056260A (en) | 2000-12-29 | 2000-12-29 | Method for forming metal gate of semiconductor devoie |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002237469A true JP2002237469A (en) | 2002-08-23 |
Family
ID=19703940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001393197A Pending JP2002237469A (en) | 2000-12-29 | 2001-12-26 | Method for forming metal gate of semiconductor element |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7157359B2 (en) |
| JP (1) | JP2002237469A (en) |
| KR (1) | KR20020056260A (en) |
| CN (1) | CN1180458C (en) |
| TW (1) | TW516131B (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003009390A1 (en) * | 2001-07-10 | 2003-01-30 | Sony Corporation | Mis type transistor and its manufacturing method |
| JP2006019693A (en) * | 2004-06-30 | 2006-01-19 | Hynix Semiconductor Inc | Gate structure of semiconductor memory device |
| JP2006024894A (en) * | 2004-07-05 | 2006-01-26 | Samsung Electronics Co Ltd | Semiconductor device having high dielectric constant-gate insulating film, and manufacturing method of the same |
| JP2006097100A (en) * | 2004-09-30 | 2006-04-13 | Tri Chemical Laboratory Inc | Film deposition material, film deposition method and element |
| JP2006097101A (en) * | 2004-09-30 | 2006-04-13 | Tri Chemical Laboratory Inc | Film deposition material, film deposition method and element |
| JP2007158065A (en) * | 2005-12-06 | 2007-06-21 | Nec Electronics Corp | Semiconductor device and manufacturing method thereof |
| JP2008518487A (en) * | 2004-11-02 | 2008-05-29 | インテル コーポレイション | Method of manufacturing a semiconductor device having a high dielectric constant gate dielectric layer and a silicide gate electrode |
| JP2008529274A (en) * | 2005-01-26 | 2008-07-31 | フリースケール セミコンダクター インコーポレイテッド | Metal gate transistor for CMOS process and manufacturing method thereof |
| JP2014078734A (en) * | 2005-07-20 | 2014-05-01 | Applied Materials Inc | Gate electrode structures and methods of manufacture |
| JP2014187104A (en) * | 2013-03-22 | 2014-10-02 | Hitachi Kokusai Electric Inc | Semiconductor device manufacturing method, substrate processing apparatus, semiconductor device, program and storage medium |
Families Citing this family (87)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6974766B1 (en) | 1998-10-01 | 2005-12-13 | Applied Materials, Inc. | In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application |
| US6551929B1 (en) | 2000-06-28 | 2003-04-22 | Applied Materials, Inc. | Bifurcated deposition process for depositing refractory metal layers employing atomic layer deposition and chemical vapor deposition techniques |
| US7405158B2 (en) | 2000-06-28 | 2008-07-29 | Applied Materials, Inc. | Methods for depositing tungsten layers employing atomic layer deposition techniques |
| US7964505B2 (en) | 2005-01-19 | 2011-06-21 | Applied Materials, Inc. | Atomic layer deposition of tungsten materials |
| US6936538B2 (en) | 2001-07-16 | 2005-08-30 | Applied Materials, Inc. | Method and apparatus for depositing tungsten after surface treatment to improve film characteristics |
| US7732327B2 (en) | 2000-06-28 | 2010-06-08 | Applied Materials, Inc. | Vapor deposition of tungsten materials |
| US7101795B1 (en) | 2000-06-28 | 2006-09-05 | Applied Materials, Inc. | Method and apparatus for depositing refractory metal layers employing sequential deposition techniques to form a nucleation layer |
| US6511911B1 (en) | 2001-04-03 | 2003-01-28 | Advanced Micro Devices, Inc. | Metal gate stack with etch stop layer |
| US6596643B2 (en) * | 2001-05-07 | 2003-07-22 | Applied Materials, Inc. | CVD TiSiN barrier for copper integration |
| US6849545B2 (en) * | 2001-06-20 | 2005-02-01 | Applied Materials, Inc. | System and method to form a composite film stack utilizing sequential deposition techniques |
| US7211144B2 (en) | 2001-07-13 | 2007-05-01 | Applied Materials, Inc. | Pulsed nucleation deposition of tungsten layers |
| JP2005518088A (en) | 2001-07-16 | 2005-06-16 | アプライド マテリアルズ インコーポレイテッド | Formation of tungsten composite film |
| US8110489B2 (en) | 2001-07-25 | 2012-02-07 | Applied Materials, Inc. | Process for forming cobalt-containing materials |
| US20090004850A1 (en) | 2001-07-25 | 2009-01-01 | Seshadri Ganguli | Process for forming cobalt and cobalt silicide materials in tungsten contact applications |
| US9051641B2 (en) | 2001-07-25 | 2015-06-09 | Applied Materials, Inc. | Cobalt deposition on barrier surfaces |
| US8026161B2 (en) | 2001-08-30 | 2011-09-27 | Micron Technology, Inc. | Highly reliable amorphous high-K gate oxide ZrO2 |
| US7049226B2 (en) * | 2001-09-26 | 2006-05-23 | Applied Materials, Inc. | Integration of ALD tantalum nitride for copper metallization |
| TW589684B (en) | 2001-10-10 | 2004-06-01 | Applied Materials Inc | Method for depositing refractory metal layers employing sequential deposition techniques |
| US6916398B2 (en) * | 2001-10-26 | 2005-07-12 | Applied Materials, Inc. | Gas delivery apparatus and method for atomic layer deposition |
| US7780785B2 (en) | 2001-10-26 | 2010-08-24 | Applied Materials, Inc. | Gas delivery apparatus for atomic layer deposition |
| US7081271B2 (en) | 2001-12-07 | 2006-07-25 | Applied Materials, Inc. | Cyclical deposition of refractory metal silicon nitride |
| US6767795B2 (en) * | 2002-01-17 | 2004-07-27 | Micron Technology, Inc. | Highly reliable amorphous high-k gate dielectric ZrOXNY |
| US7175713B2 (en) | 2002-01-25 | 2007-02-13 | Applied Materials, Inc. | Apparatus for cyclical deposition of thin films |
| US6911391B2 (en) | 2002-01-26 | 2005-06-28 | Applied Materials, Inc. | Integration of titanium and titanium nitride layers |
| US6893984B2 (en) * | 2002-02-20 | 2005-05-17 | Micron Technology Inc. | Evaporated LaA1O3 films for gate dielectrics |
| US6833161B2 (en) | 2002-02-26 | 2004-12-21 | Applied Materials, Inc. | Cyclical deposition of tungsten nitride for metal oxide gate electrode |
| US6972267B2 (en) | 2002-03-04 | 2005-12-06 | Applied Materials, Inc. | Sequential deposition of tantalum nitride using a tantalum-containing precursor and a nitrogen-containing precursor |
| JP2003282873A (en) * | 2002-03-22 | 2003-10-03 | Sony Corp | Semiconductor device and its fabricating method |
| US7279432B2 (en) | 2002-04-16 | 2007-10-09 | Applied Materials, Inc. | System and method for forming an integrated barrier layer |
| US7160577B2 (en) | 2002-05-02 | 2007-01-09 | Micron Technology, Inc. | Methods for atomic-layer deposition of aluminum oxides in integrated circuits |
| US7205218B2 (en) | 2002-06-05 | 2007-04-17 | Micron Technology, Inc. | Method including forming gate dielectrics having multiple lanthanide oxide layers |
| JP4643884B2 (en) | 2002-06-27 | 2011-03-02 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| US7221586B2 (en) | 2002-07-08 | 2007-05-22 | Micron Technology, Inc. | Memory utilizing oxide nanolaminates |
| US7186385B2 (en) | 2002-07-17 | 2007-03-06 | Applied Materials, Inc. | Apparatus for providing gas to a processing chamber |
| US6921702B2 (en) | 2002-07-30 | 2005-07-26 | Micron Technology Inc. | Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics |
| US7199023B2 (en) * | 2002-08-28 | 2007-04-03 | Micron Technology, Inc. | Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed |
| US7101813B2 (en) | 2002-12-04 | 2006-09-05 | Micron Technology Inc. | Atomic layer deposited Zr-Sn-Ti-O films |
| US7262133B2 (en) * | 2003-01-07 | 2007-08-28 | Applied Materials, Inc. | Enhancement of copper line reliability using thin ALD tan film to cap the copper line |
| US7019351B2 (en) * | 2003-03-12 | 2006-03-28 | Micron Technology, Inc. | Transistor devices, and methods of forming transistor devices and circuit devices |
| US7183186B2 (en) | 2003-04-22 | 2007-02-27 | Micro Technology, Inc. | Atomic layer deposited ZrTiO4 films |
| US7316950B2 (en) * | 2003-04-22 | 2008-01-08 | National University Of Singapore | Method of fabricating a CMOS device with dual metal gate electrodes |
| US7049192B2 (en) * | 2003-06-24 | 2006-05-23 | Micron Technology, Inc. | Lanthanide oxide / hafnium oxide dielectrics |
| KR100543207B1 (en) * | 2003-06-30 | 2006-01-20 | 주식회사 하이닉스반도체 | Method for fabricating gate-electrode of semiconductor device using hardmask |
| US6927136B2 (en) * | 2003-08-25 | 2005-08-09 | Macronix International Co., Ltd. | Non-volatile memory cell having metal nano-particles for trapping charges and fabrication thereof |
| US20050252449A1 (en) | 2004-05-12 | 2005-11-17 | Nguyen Son T | Control of gas flow and delivery to suppress the formation of particles in an MOCVD/ALD system |
| US8399934B2 (en) * | 2004-12-20 | 2013-03-19 | Infineon Technologies Ag | Transistor device |
| US7241686B2 (en) * | 2004-07-20 | 2007-07-10 | Applied Materials, Inc. | Atomic layer deposition of tantalum-containing materials using the tantalum precursor TAIMATA |
| US7601649B2 (en) | 2004-08-02 | 2009-10-13 | Micron Technology, Inc. | Zirconium-doped tantalum oxide films |
| US7081421B2 (en) | 2004-08-26 | 2006-07-25 | Micron Technology, Inc. | Lanthanide oxide dielectric layer |
| US7588988B2 (en) | 2004-08-31 | 2009-09-15 | Micron Technology, Inc. | Method of forming apparatus having oxide films formed using atomic layer deposition |
| US7494939B2 (en) | 2004-08-31 | 2009-02-24 | Micron Technology, Inc. | Methods for forming a lanthanum-metal oxide dielectric layer |
| KR100575887B1 (en) * | 2004-11-08 | 2006-05-03 | 주식회사 하이닉스반도체 | Method for forming capacitor of semiconductor device |
| US7235501B2 (en) | 2004-12-13 | 2007-06-26 | Micron Technology, Inc. | Lanthanum hafnium oxide dielectrics |
| US7560395B2 (en) | 2005-01-05 | 2009-07-14 | Micron Technology, Inc. | Atomic layer deposited hafnium tantalum oxide dielectrics |
| WO2007078306A1 (en) * | 2005-03-28 | 2007-07-12 | Massachusetts Institute Of Technology | HIGH K-GATE OXIDE TFTs BUILT ON TRANSPARENT GLASS OR TRANSPARENT FLEXIBLE POLYMER SUBSTRATE |
| US7687409B2 (en) | 2005-03-29 | 2010-03-30 | Micron Technology, Inc. | Atomic layer deposited titanium silicon oxide films |
| US7390756B2 (en) | 2005-04-28 | 2008-06-24 | Micron Technology, Inc. | Atomic layer deposited zirconium silicon oxide films |
| US7662729B2 (en) | 2005-04-28 | 2010-02-16 | Micron Technology, Inc. | Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer |
| US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
| KR100655658B1 (en) * | 2005-07-26 | 2006-12-08 | 삼성전자주식회사 | Gate electrode structure and method of manufacturing the gate electrode structure, and semiconductor transistor having the gate electrode structure and method of manufacturing the semiconductor transistor |
| US8110469B2 (en) | 2005-08-30 | 2012-02-07 | Micron Technology, Inc. | Graded dielectric layers |
| TW200737307A (en) | 2005-11-04 | 2007-10-01 | Applied Materials Inc | Apparatus and process for plasma-enhanced atomic layer deposition |
| US7709402B2 (en) | 2006-02-16 | 2010-05-04 | Micron Technology, Inc. | Conductive layers for hafnium silicon oxynitride films |
| US7798096B2 (en) | 2006-05-05 | 2010-09-21 | Applied Materials, Inc. | Plasma, UV and ion/neutral assisted ALD or CVD in a batch tool |
| US20080050879A1 (en) * | 2006-08-23 | 2008-02-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of forming metal-containing gate structures |
| US7582549B2 (en) | 2006-08-25 | 2009-09-01 | Micron Technology, Inc. | Atomic layer deposited barium strontium titanium oxide films |
| US7605030B2 (en) | 2006-08-31 | 2009-10-20 | Micron Technology, Inc. | Hafnium tantalum oxynitride high-k dielectric and metal gates |
| US7521379B2 (en) | 2006-10-09 | 2009-04-21 | Applied Materials, Inc. | Deposition and densification process for titanium nitride barrier layers |
| US7759237B2 (en) | 2007-06-28 | 2010-07-20 | Micron Technology, Inc. | Method of forming lutetium and lanthanum dielectric structures |
| US7678298B2 (en) | 2007-09-25 | 2010-03-16 | Applied Materials, Inc. | Tantalum carbide nitride materials by vapor deposition processes |
| US8017183B2 (en) * | 2007-09-26 | 2011-09-13 | Eastman Kodak Company | Organosiloxane materials for selective area deposition of inorganic materials |
| US7824743B2 (en) | 2007-09-28 | 2010-11-02 | Applied Materials, Inc. | Deposition processes for titanium nitride barrier and aluminum |
| US7732872B2 (en) * | 2007-10-25 | 2010-06-08 | International Business Machines Corporation | Integration scheme for multiple metal gate work function structures |
| US7911008B2 (en) * | 2007-10-25 | 2011-03-22 | International Business Machines Corporation | SRAM cell having a rectangular combined active area for planar pass gate and planar pull-down NFETS |
| US7741217B2 (en) * | 2007-10-25 | 2010-06-22 | International Business Machines Corporation | Dual workfunction silicide diode |
| US7659158B2 (en) | 2008-03-31 | 2010-02-09 | Applied Materials, Inc. | Atomic layer deposition processes for non-volatile memory devices |
| US8491967B2 (en) | 2008-09-08 | 2013-07-23 | Applied Materials, Inc. | In-situ chamber treatment and deposition process |
| US20100062149A1 (en) | 2008-09-08 | 2010-03-11 | Applied Materials, Inc. | Method for tuning a deposition rate during an atomic layer deposition process |
| US8146896B2 (en) | 2008-10-31 | 2012-04-03 | Applied Materials, Inc. | Chemical precursor ampoule for vapor deposition processes |
| CN101740369B (en) * | 2008-11-19 | 2011-12-07 | 中国科学院微电子研究所 | Method for preparing metallic metal nitride film |
| CN102315117B (en) * | 2010-06-30 | 2013-05-22 | 中国科学院微电子研究所 | Etching method for Mo base/TaN metal grid lamination structure |
| CN102956450B (en) * | 2011-08-16 | 2015-03-11 | 中芯国际集成电路制造(北京)有限公司 | Method for manufacturing semiconductor devices |
| KR20140003154A (en) * | 2012-06-29 | 2014-01-09 | 에스케이하이닉스 주식회사 | Method for manufacturing semiconductor device |
| CN102842620A (en) * | 2012-09-11 | 2012-12-26 | 京东方科技集团股份有限公司 | Thin film transistor and manufacturing method thereof as well as array substrate and display device |
| KR20210055148A (en) | 2019-11-06 | 2021-05-17 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the same |
| CN113690178A (en) * | 2021-08-23 | 2021-11-23 | 长江先进存储产业创新中心有限责任公司 | Method for manufacturing metal conductive structure |
| CN116454132A (en) * | 2022-01-06 | 2023-07-18 | 长鑫存储技术有限公司 | Semiconductor structure and manufacturing method thereof |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH065852A (en) | 1992-06-23 | 1994-01-14 | Oki Electric Ind Co Ltd | Mosfet and manufacture thereof |
| JP3336747B2 (en) * | 1994-06-09 | 2002-10-21 | ソニー株式会社 | Method for forming insulating film, method for manufacturing semiconductor device, and semiconductor device |
| JPH09143699A (en) | 1995-11-24 | 1997-06-03 | Nissin Electric Co Ltd | Treatment of base material and device therefor |
| US5923056A (en) * | 1996-10-10 | 1999-07-13 | Lucent Technologies Inc. | Electronic components with doped metal oxide dielectric materials and a process for making electronic components with doped metal oxide dielectric materials |
| US6197683B1 (en) | 1997-09-29 | 2001-03-06 | Samsung Electronics Co., Ltd. | Method of forming metal nitride film by chemical vapor deposition and method of forming metal contact of semiconductor device using the same |
| US5907780A (en) * | 1998-06-17 | 1999-05-25 | Advanced Micro Devices, Inc. | Incorporating silicon atoms into a metal oxide gate dielectric using gas cluster ion beam implantation |
| KR100275738B1 (en) | 1998-08-07 | 2000-12-15 | 윤종용 | Method for producing thin film using atomatic layer deposition |
| KR20000015134A (en) * | 1998-08-27 | 2000-03-15 | 윤종용 | GATE ELECTRODE HAVING TiN ELECTRODE LAYER AND METHOD THEREOF |
| JP2000091269A (en) | 1998-09-10 | 2000-03-31 | Fujitsu Ltd | Manufacture of semiconductor device |
| JP3945043B2 (en) | 1998-10-12 | 2007-07-18 | ソニー株式会社 | Method for forming metal nitride film and method for manufacturing electronic device |
-
2000
- 2000-12-29 KR KR1020000085582A patent/KR20020056260A/en not_active Application Discontinuation
-
2001
- 2001-12-24 TW TW090132016A patent/TW516131B/en not_active IP Right Cessation
- 2001-12-26 JP JP2001393197A patent/JP2002237469A/en active Pending
- 2001-12-26 US US10/036,156 patent/US7157359B2/en not_active Expired - Lifetime
- 2001-12-28 CN CNB011447869A patent/CN1180458C/en not_active Expired - Lifetime
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003009390A1 (en) * | 2001-07-10 | 2003-01-30 | Sony Corporation | Mis type transistor and its manufacturing method |
| JP4573653B2 (en) * | 2004-06-30 | 2010-11-04 | 株式会社ハイニックスセミコンダクター | Method for manufacturing gate structure of semiconductor memory device |
| JP2006019693A (en) * | 2004-06-30 | 2006-01-19 | Hynix Semiconductor Inc | Gate structure of semiconductor memory device |
| JP2006024894A (en) * | 2004-07-05 | 2006-01-26 | Samsung Electronics Co Ltd | Semiconductor device having high dielectric constant-gate insulating film, and manufacturing method of the same |
| JP4591917B2 (en) * | 2004-09-30 | 2010-12-01 | 株式会社トリケミカル研究所 | Method for forming conductive molybdenum nitride film |
| JP2006097101A (en) * | 2004-09-30 | 2006-04-13 | Tri Chemical Laboratory Inc | Film deposition material, film deposition method and element |
| JP2006097100A (en) * | 2004-09-30 | 2006-04-13 | Tri Chemical Laboratory Inc | Film deposition material, film deposition method and element |
| JP4592373B2 (en) * | 2004-09-30 | 2010-12-01 | 株式会社トリケミカル研究所 | Method for forming conductive molybdenum nitride gate electrode film |
| JP2008518487A (en) * | 2004-11-02 | 2008-05-29 | インテル コーポレイション | Method of manufacturing a semiconductor device having a high dielectric constant gate dielectric layer and a silicide gate electrode |
| JP2008529274A (en) * | 2005-01-26 | 2008-07-31 | フリースケール セミコンダクター インコーポレイテッド | Metal gate transistor for CMOS process and manufacturing method thereof |
| JP4685882B2 (en) * | 2005-01-26 | 2011-05-18 | フリースケール セミコンダクター インコーポレイテッド | Semiconductor device and manufacturing method thereof |
| JP2014078734A (en) * | 2005-07-20 | 2014-05-01 | Applied Materials Inc | Gate electrode structures and methods of manufacture |
| JP2007158065A (en) * | 2005-12-06 | 2007-06-21 | Nec Electronics Corp | Semiconductor device and manufacturing method thereof |
| JP2014187104A (en) * | 2013-03-22 | 2014-10-02 | Hitachi Kokusai Electric Inc | Semiconductor device manufacturing method, substrate processing apparatus, semiconductor device, program and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20020056260A (en) | 2002-07-10 |
| CN1180458C (en) | 2004-12-15 |
| US20020086507A1 (en) | 2002-07-04 |
| US7157359B2 (en) | 2007-01-02 |
| CN1363949A (en) | 2002-08-14 |
| TW516131B (en) | 2003-01-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2002237469A (en) | Method for forming metal gate of semiconductor element | |
| US20060205143A1 (en) | DRAM with high K dielectric storage capacitor and method of making the same | |
| KR100545706B1 (en) | Semiconductor device manufacturing method | |
| US7564114B2 (en) | Semiconductor devices and methods of manufacture thereof | |
| US20020001906A1 (en) | Method of manufacturing a gate in a semiconductor device | |
| US8039337B2 (en) | Nonvolatile memory device with multiple blocking layers and method of fabricating the same | |
| KR20060100092A (en) | Method for manufacturing a semiconductor device | |
| US7112486B2 (en) | Method for fabricating semiconductor device by using radical oxidation | |
| US6514841B2 (en) | Method for manufacturing gate structure for use in semiconductor device | |
| CN100386842C (en) | Method to control interfacial properties for capacitors using a metal flash layer | |
| KR100543207B1 (en) | Method for fabricating gate-electrode of semiconductor device using hardmask | |
| KR100671722B1 (en) | Tungsten silicide nitride as an electrode for tantalum pentoxide devices | |
| US6800907B2 (en) | Method for fabricating semiconductor device | |
| KR100555541B1 (en) | Forming method for cobalt silicide layer and manufacturing method for semiconductor device using the forming method | |
| TWI739176B (en) | Forming method of structure in semiconductor device for modifying effective oxide thickness | |
| US20020079588A1 (en) | Semiconductor device and method for manufacturing the same | |
| KR100384848B1 (en) | Method for fabricating semiconductor device | |
| KR100611386B1 (en) | Method For Treating The High Temperature Of Tantalium Oxide Capacitor | |
| KR20060058813A (en) | Method for forming a gate oxide layer in non-volatile memory device and method for forming a gate pattern including the same | |
| JP3563288B2 (en) | Method for manufacturing semiconductor device | |
| KR20060032919A (en) | Chemical vapor deposition methods of forming an ohmic layer and a barrier metal layer in a semiconductor device using plasma | |
| KR20010004045A (en) | method of forming gate insulating layer for semiconductor device | |
| KR20060013283A (en) | Method for manufacturing a capacitor of a semiconductor device | |
| KR20040001882A (en) | Method for forming ruthenium and method for fabricating capacitor using the same | |
| KR20050099113A (en) | Method for forming a cylindrical capacitor in a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20040407 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20050427 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20050510 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20050810 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20060207 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060511 |
|
| A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20060627 |
|
| A912 | Re-examination (zenchi) completed and case transferred to appeal board |
Free format text: JAPANESE INTERMEDIATE CODE: A912 Effective date: 20060721 |