KR20010004045A - method of forming gate insulating layer for semiconductor device - Google Patents

method of forming gate insulating layer for semiconductor device Download PDF

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KR20010004045A
KR20010004045A KR1019990024630A KR19990024630A KR20010004045A KR 20010004045 A KR20010004045 A KR 20010004045A KR 1019990024630 A KR1019990024630 A KR 1019990024630A KR 19990024630 A KR19990024630 A KR 19990024630A KR 20010004045 A KR20010004045 A KR 20010004045A
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gate insulating
insulating film
film
forming
semiconductor device
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KR100380275B1 (en
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김정호
김현수
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김영환
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/301—Assembling printed circuits with electric components, e.g. with resistor by means of a mounting structure

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE: A gate insulating film forming method of a semiconductor device is to ensure a thickness of a gate insulating film corresponding to a super high integration by using materials having a high inductance, and prevent an interface trap between a substrate and the gate insulating film and a reaction of a polysilicon film and the gate insulating film. CONSTITUTION: A method of forming a gate insulating film of a semiconductor device comprises the steps of: providing a semiconductor substrate(11) with an active region defined by a field oxide film; forming a gate insulating film(13) on the whole surface of the semiconductor substrate by an insulating film having a high inductance; thermal processing the gate insulating film; and forming a barrier nitride film(14) on the surface of the thermal processed gate insulating film. The gate insulating film is formed of an Al2O3 film. Also, the gate insulating film is formed at a thickness of 30-60 angstroms by an atom layer epitaxy process. The thermal processing is progressed under the temperature of 600-900 deg.C for 30-60 seconds.

Description

반도체 소자의 게이트 절연막 형성방법{method of forming gate insulating layer for semiconductor device}A method of forming a gate insulating layer of a semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 Al2O3와 같은 높은 유전율을 갖는 물질을 이용한 초고집적 반도체 소자의 게이트 절연막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming a gate insulating film of an ultra-high density semiconductor device using a material having a high dielectric constant such as Al 2 O 3 .

반도체 소자의 고집적화에 따른 디자인룰의 감소에 의해 게이트 산화막의 두께가 얇아지고 있다. 최근에는 30Å이하의 두께로 게이트 산화막을 형성하는 기술이 연구되고 있으나, 게이트 산화막의 물리적 두께가 30 내지 40Å인 경우에는 직접터털링(direct tunneling)등에 의해 누설전류가 야기되기 때문에, 40Å 이하로 게이트 산화막 두께를 낮추는데 어려움이 있다.The thickness of the gate oxide film is reduced due to the reduction of design rules due to the high integration of semiconductor devices. Recently, a technique of forming a gate oxide film with a thickness of 30 mA or less has been studied. However, when the physical thickness of the gate oxide film is 30 to 40 mA, a leakage current is caused by direct tunneling or the like. It is difficult to reduce the oxide film thickness.

즉, 상기한 직접터널링은 게이트 산화막의 물리적 두께와 밀접한 관계가 있으므로, 이러한 직접터널링을 방지하기 위하여, 최근에는 유전율이 높은 물질을 이용하여 게이트 산화막의 물리적 두께를 증가시키면서 전기적인 두께를 30 내지 40Å으로 유지하는 기술이 제시되었다.That is, since the direct tunneling is closely related to the physical thickness of the gate oxide film, in order to prevent such direct tunneling, an electrical thickness of 30 to 40 kΩ is increased while increasing the physical thickness of the gate oxide film using a material having a high dielectric constant. The technique to keep as was presented.

그러나, 상기한 유전율이 높은 물질은 대부분 유기소오스(orgainc source)를 사용하여 증착되어 증착후 탄소를 함유하기 때문에, 게이트 산화막과 실리콘 기판 사이의 계면에서 계면 트랩현상이 발생되어 누설전류를 야기시킨다. 또한, 게이트 형성을 위하여 상기한 유전율이 높은 물질로 이루어진 게이트 산화막 상에 폴리실리콘막을 증착하게 되면, 게이트 산화막 내의 산소와 실리콘이 반응하여 실리콘 산화막이 형성되어 게이트 산화막의 유효 산화막 두께가 증가된다. 또한 듀얼 게이트 (dual gate)의 p형 게이트 형성시 B 이온의 침투(penetration)문제가 야기되어 게이트 산화막의 절연특성이 저하된다.However, since the high dielectric constant materials are mostly deposited using an organic source (orgainc source) to contain carbon after deposition, an interface trap phenomenon occurs at the interface between the gate oxide film and the silicon substrate to cause leakage current. In addition, when the polysilicon film is deposited on the gate oxide film made of a material having a high dielectric constant for forming the gate, oxygen and silicon in the gate oxide film react to form a silicon oxide film, thereby increasing the effective oxide film thickness of the gate oxide film. In addition, the formation of a p-type gate of a dual gate causes a problem of penetration of B ions, thereby lowering the insulating characteristic of the gate oxide layer.

따라서, 본 발명은 상기한 종래의 해결하기 위한 것으로서, 유전율이 높은 물질을 이용하여 초고집적화에 대응하는 게이트 절연막 두께를 확보하면서, 기판과의 계면트랩 현상 및 게이트용 폴리실리콘막과의 반응을 방지할 수 있는 반도체 소자의 게이트 절연막 형성방법을 제공함에 그 목적이 있다.Therefore, the present invention is to solve the above-described conventional, by using a high dielectric constant material to ensure the gate insulating film thickness corresponding to the ultra-high integration, while preventing the interface trap phenomenon with the substrate and the reaction with the polysilicon film for the gate It is an object of the present invention to provide a method for forming a gate insulating film of a semiconductor device.

도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 게이트 절연막 형성방법을 설명하기 위한 단면도.1A to 1C are cross-sectional views illustrating a method of forming a gate insulating film of a semiconductor device according to an embodiment of the present invention.

(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

11 : 반도체 기판 12 : 필드 산화막11: semiconductor substrate 12: field oxide film

13 : 게이트 절연막 14 : 배리어 질화막13 gate insulating film 14 barrier nitride film

상기한 본 발명의 목적을 달성하기 위하여, 본 발명에 따라 필드 산화막에 의해 액티브 영역이 정의된 반도체 기판을 제공하고, 기판 전면에 유전율이 높은 절연막으로 게이트 절연막을 형성한다. 그런 다음, 게이트 절연막을 열처리하고, 게이트 절연막 표면 상에 배리어 질화막을 형성한다.In order to achieve the above object of the present invention, a semiconductor substrate in which an active region is defined by a field oxide film according to the present invention is provided, and a gate insulating film is formed of an insulating film having a high dielectric constant on the entire surface of the substrate. Then, the gate insulating film is heat-treated, and a barrier nitride film is formed on the gate insulating film surface.

본 실시예에서, 게이트 절연막은 Al2O3막으로 30 내지 60Å의 두께로 원자층 에피택시 공정으로 형성한다. 또한, 열처리는 N2O 개스를 이용한 급속열처리로 800 내지 900℃의 온도에서 30 내지 60초 동안 진행한다. 또한, 배리어 질화막은 게이트 절연막의 표면을 질화처리하여 AlN막 또는 AlON막으로 형성하고, 질화처리는 NH3개스를 이용한 급속열처리로 진행한다.In this embodiment, the gate insulating film is formed by an atomic layer epitaxy process with an Al 2 O 3 film having a thickness of 30 to 60 kPa. In addition, the heat treatment is a rapid heat treatment using N 2 O gas for 30 to 60 seconds at a temperature of 800 to 900 ℃. In addition, the barrier nitride film is formed of an AlN film or an AlON film by nitriding the surface of the gate insulating film, and the nitriding is performed by rapid heat treatment using NH 3 gas.

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

도 1a 내지 도 1c는 본 발명의 실시예에 따른 반도체 소자의 게이트 절연막 형성방법을 설명하기 위한 단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a gate insulating film of a semiconductor device according to an embodiment of the present invention.

도 1a를 참조하면, 실리콘을 포함하는 반도체 기판(11) 상에 필드 산화막(12)을 형성하여 필드 산화막(12) 사이에 액티브 영역을 정의하고, 액티브 영역의 표면을 HF로 시트-오프(sheet off)하여 자연산화막(미도시)을 제거한다.Referring to FIG. 1A, a field oxide layer 12 is formed on a semiconductor substrate 11 including silicon to define an active region between the field oxide layers 12, and the surface of the active region is sheet-off with HF. off) to remove the native oxide film (not shown).

도 1b를 참조하면, 기판 전면에 원자층 에피택시(Atomic Layer Epitaxy; ALE) 공정으로 높은 유전율을 갖는 물질, 바람직하게 Al2O3막을 30 내지 60Å의 두께로 증착하여 게이트 절연막(13)을 형성한다. 즉, Al2O3는 열산화막 2 내지 3배 정도 큰 유전상수를 갖으므로, 게이트 절연막(13)의 물리적 두께를 2배정도 두껍게 증착하는 것이 가능하고, 증착후 소정의 탄소를 함유하게 된다.Referring to FIG. 1B, a gate dielectric layer 13 is formed by depositing a material having a high dielectric constant, preferably an Al 2 O 3 layer, having a thickness of 30 to 60 Å on an entire surface of an substrate by an atomic layer epitaxy (ALE) process. do. That is, since Al 2 O 3 has a dielectric constant about 2 to 3 times larger than the thermal oxide film, the physical thickness of the gate insulating film 13 can be deposited about twice as thick, and after deposition, it contains a predetermined carbon.

그리고 나서, Al2O3막으로 이루어진 게이트 절연막(13)을 N2O 개스를 이용하여 급속열처리(Rapid Thermal Processing; RTP)한다. 바람직하게, RTP는 800 내지 900℃의 온도에서 30 내지 60초 동안 진행한다. 이때, N2O 개스가 열분해되어 활성화산소가 생성되어 Al2O3막의 탄소가 제거될 뿐만 아니라 Al2O3막의 결정화 (crystallization)가 이루어져서, 기판(11)과 게이트 절연막(13)의 계면에서 계면트랩현상이 방지되고 누설전류 특성이 향상된다. 또한, 상기한 바와 같은 단시간의 RTP에 의해 열적버젯(thermal budget)이 감소되는 효과가 있다.Thereafter, the gate insulating film 13 made of the Al 2 O 3 film is subjected to Rapid Thermal Processing (RTP) using N 2 O gas. Preferably, the RTP runs for 30 to 60 seconds at a temperature of 800 to 900 ° C. At this time, the N 2 O gas is pyrolyzed to generate activated oxygen to remove carbon of the Al 2 O 3 film as well as to crystallize the Al 2 O 3 film, thereby at the interface between the substrate 11 and the gate insulating film 13. Interface trapping is prevented and leakage current characteristics are improved. In addition, there is an effect that the thermal budget is reduced by the short time RTP as described above.

도 1c를 참조하면, 게이트 절연막(13) 표면을 질화처리(nitridation)하여 게이트 절연막(13) 표면 상에 AlN막 또는 AlON막과 같은 배리어 질화막(14)을 형성한다. 바람직하게, 상기 질화처리는 NH3개스를 이용한 RTP로 진행한다. 즉, 이러한 배리어 질화막(14)에 의해 이후 게이트용 폴리실리콘막의 반응을 방지될 뿐만 아니라, p형 게이트 형성에 따른 B이온의 침투가 방지되어 게이트 절연막(13)의 절연특성이 향상된다.Referring to FIG. 1C, a barrier nitride film 14 such as an AlN film or an AlON film is formed on the gate insulating film 13 by nitriding the surface of the gate insulating film 13. Preferably, the nitriding proceeds with RTP using NH 3 gas. That is, the barrier nitride film 14 not only prevents the reaction of the gate polysilicon film later, but also prevents the penetration of B ions due to the p-type gate formation, thereby improving the insulating property of the gate insulating film 13.

상기한 본 발명에 의하면, 열산화막보다 유전상수가 큰 Al2O3막을 이용하여 게이트 절연막을 형성하므로 게이트 절연막의 물리적 두께를 2배정도 두껍게 증착하는 것이 가능하고, Al2O3막의 증착후 N2O 개스를 이용하여 RTP를 진행하여 Al2O3막에 함유된 탄소를 제거함으로써, 기판과 게이트 절연막의 계면트랩현상이 방지되고 누설전류특성이 향상된다. 또한, 게이트 절연막 상부에 배리어 질화막을 형성함으로써, 게이트용 폴리실리콘막과의 반응이 방지될 뿐만 아니라, p형 게이트 형성에 따른 B이온의 침투가 방지되어 절연특성이 향상된다.According to the present invention described above, since the gate insulating film is formed by using an Al 2 O 3 film having a higher dielectric constant than the thermal oxide film, it is possible to deposit the thickness of the gate insulating film about twice as thick, and after deposition of the Al 2 O 3 film, N 2. By performing RTP using O gas to remove carbon contained in the Al 2 O 3 film, the interface trap between the substrate and the gate insulating film is prevented and the leakage current characteristic is improved. In addition, by forming a barrier nitride film on the gate insulating film, the reaction with the gate polysilicon film is not only prevented, but also the penetration of B ions due to the p-type gate formation is prevented to improve the insulating properties.

또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (8)

필드 산화막에 의해 액티브 영역이 정의된 반도체 기판을 제공하는 단계;Providing a semiconductor substrate having an active region defined by a field oxide film; 상기 기판 전면에 유전율이 높은 절연막으로 게이트 절연막을 형성하는 단계;Forming a gate insulating film with an insulating film having a high dielectric constant on the entire surface of the substrate; 상기 게이트 절연막을 열처리하는 단계; 및Heat-treating the gate insulating film; And 상기 열처리된 게이트 절연막 표면 상에 배리어 질화막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.Forming a barrier nitride film on the heat-treated gate insulating film surface. 제 1 항에 있어서, 상기 게이트 절연막은 Al2O3막으로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.The method of claim 1, wherein the gate insulating film is formed of an Al 2 O 3 film. 제 1 항 또는 제 2 항에 있어서, 게이트 절연막은 30 내지 60Å의 두께로 원자층 에피택시 공정으로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.The method for forming a gate insulating film of a semiconductor device according to claim 1 or 2, wherein the gate insulating film is formed by an atomic layer epitaxy process with a thickness of 30 to 60 kPa. 제 3 항에 있어서, 상기 열처리는 N2O 개스를 이용하여 급속열처리로 진행하는 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.4. The method of forming a gate insulating film of a semiconductor device according to claim 3, wherein the heat treatment is performed by rapid heat treatment using N 2 O gas. 제 4 항에 있어서, 상기 급속열처리는 800 내지 900℃의 온도에서 30 내지 60초 동안 진행하는 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.The method of claim 4, wherein the rapid heat treatment is performed at a temperature of 800 to 900 ° C. for 30 to 60 seconds. 제 3 항에 있어서, 상기 배리어 질화막은 AlN막 또는 AlON막으로 형성하는 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.4. The method of claim 3, wherein the barrier nitride film is formed of an AlN film or an AlON film. 제 6 항에 있어서, 상기 배리어 질화막은 상기 게이트 절연막의 표면을 질화처리하여 형성하는 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.7. The method of claim 6, wherein the barrier nitride film is formed by nitriding a surface of the gate insulating film. 제 7 항에 있어서, 상기 질화처리는 NH3개스를 이용한 급속열처리로 진행하는 것을 특징으로 하는 반도체 소자의 게이트 절연막 형성방법.8. The method of forming a gate insulating film of a semiconductor device according to claim 7, wherein the nitriding treatment is performed by rapid thermal treatment using NH 3 gas.
KR10-1999-0024630A 1999-06-28 1999-06-28 method of forming gate insulating layer for semiconductor device KR100380275B1 (en)

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KR100451507B1 (en) * 2001-12-24 2004-10-06 주식회사 하이닉스반도체 Method for manufacturing semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100451507B1 (en) * 2001-12-24 2004-10-06 주식회사 하이닉스반도체 Method for manufacturing semiconductor device

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