KR0175053B1 - Method of forming a multilayer insulating film of a semiconductor device - Google Patents
Method of forming a multilayer insulating film of a semiconductor device Download PDFInfo
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- KR0175053B1 KR0175053B1 KR1019960014565A KR19960014565A KR0175053B1 KR 0175053 B1 KR0175053 B1 KR 0175053B1 KR 1019960014565 A KR1019960014565 A KR 1019960014565A KR 19960014565 A KR19960014565 A KR 19960014565A KR 0175053 B1 KR0175053 B1 KR 0175053B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02183—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing tantalum, e.g. Ta2O5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
Abstract
반도체장치의 다층 절연막 형성방법이 개시되어 있다. 본 발명은 반도체기판 상에 실리콘질화막을 형성하는 단계와, 상기 실리콘질화막 상에 옥시나이트라이드막을 형성하는 단계와, 상기 옥시나이트라이드막 상에 고유전막을 형성하는 단계와, 상기 고유전막이 안정된 조성비를 갖도록 상기 결과물을 산소가스 및 오존 분위기에서 열처리하는 단계와, 상기 열처리된 고유전막 상에 절연막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체장치의 다층 절연막 형성방법을 제공한다. 본 발명에 의하면, 안정된 조성비를 갖는 고유전막을 포함하는 다층 절연막을 형성할 수 있으므로 산화막 등가두께를 크게 감소시키면서 누설전류 특성을 개선시킬 수 있다. 따라서, 본 발명에 의한 다층 절연막을 트랜지스터의 게이트 절연막으로 사용할 경우 트랜지스터의 전기적 특성을 크게 향상시킬 수 있다.A method of forming a multilayer insulating film of a semiconductor device is disclosed. The present invention provides a method of forming a silicon nitride film on a semiconductor substrate, forming an oxynitride film on the silicon nitride film, forming a high dielectric film on the oxynitride film, and a stable composition ratio of the high dielectric film. And heat-treating the resultant product in an oxygen gas and ozone atmosphere to form an insulating film on the heat-treated high dielectric film. According to the present invention, since a multilayer insulating film including a high dielectric film having a stable composition ratio can be formed, the leakage current characteristic can be improved while greatly reducing the oxide film equivalent thickness. Therefore, when the multilayer insulating film according to the present invention is used as the gate insulating film of the transistor, the electrical characteristics of the transistor can be greatly improved.
Description
제1도는 종래의 다층 절연막 형성방법을 설명하기 위한 단면도이다.1 is a cross-sectional view for explaining a conventional method for forming a multilayer insulating film.
제2도 및 제3도는 본 발명에 따른 다층 절연막 형성방법을 설명하기 위한 단면도들이다.2 and 3 are cross-sectional views illustrating a method of forming a multilayer insulating film according to the present invention.
본 발명은 반도체장치의 다층 절연막 형성방법에 관한 것으로, 특히 탄탈륨 산화막을 포함하는 다층 절연막 형성방법에 관한 것이다.The present invention relates to a method for forming a multilayer insulating film of a semiconductor device, and more particularly, to a method for forming a multilayer insulating film including a tantalum oxide film.
반도체장치가 고집적화되면서 트랜지스터 또는 커패시터의 크기가 평면적으로 점점 작아지고 있다. 이러한 고집적 반도체장치는 소자의 신뢰성과 관련하여 그 동작전압 또한 기존의 5.0V 보다 낮은 전압, 예컨대 3.3V 또는 2.5V.이하의 Vcc 전압을 필요로 한다. 그러나, 이와 같이 동작전압이 낮아지게 되면, 트랜지스터의 경우에 구동전류가 감소하게 된다. 따라서, 트랜지스터로 구성된 반도체장치의 동작속도가 저하된다. 이러한 문제점을 해결하기 위한 방법은 여러 가지가 있으며, 그 중에 하나로 게이트 절연막 두께를 얇게 형성하는 방법을 들 수 있다.As semiconductor devices have been highly integrated, the size of transistors or capacitors has become smaller and smaller. Such a highly integrated semiconductor device requires a voltage lower than the existing 5.0V, for example, a Vcc voltage of 3.3V or 2.5V or less in relation to device reliability. However, when the operating voltage is lowered in this way, the driving current is reduced in the case of the transistor. Therefore, the operation speed of the semiconductor device composed of transistors is reduced. There are various methods for solving this problem, and one of them is a method of forming a thin gate insulating film thickness.
그러나, 게이트 절연막을 산화막만으로 형성할 경우에 현재의 기술로 그 두께를 약 70Å 보다 얇게 형성하기가 매우 어렵다. 이는, 70Å 이하의 두께를 갖는 산화막을 형성할 경우 누설전류가 증가하여 트랜지스터의 전기적 특성을 크게 저하시키기 때문이다. 여기서, 일반적인 누설전류의 한계는 1 펨토암페어(femto ampere)이다. 따라서, 최근에 산화막 및 산화막에 비하여 유전상수가 높은 고유전막이 차례로 적층된 다층 절연막을 게이트 절연막의 일부막으로 사용하므로써 물리적인 두께를 증가시키어 누설전류 특성을 개선시키면서 산화막에 대한 등가두께를 60Å 내지 70Å 정도로 감소시키는 방법이 제안된 바 있다.However, in the case where the gate insulating film is formed only by the oxide film, it is very difficult to form the thickness thinner than about 70 kV by the current technology. This is because when the oxide film having a thickness of 70 kΩ or less is formed, leakage current increases, which greatly reduces the electrical characteristics of the transistor. Here, the limit of general leakage current is 1 femto ampere. Therefore, by using a multilayer insulating film in which a dielectric constant having a higher dielectric constant is sequentially laminated than the oxide film and the oxide film as a part of the gate insulating film, the equivalent thickness of the oxide film is increased from 60 kPa to 60 서 while improving the leakage current characteristics by increasing the physical thickness. A method of reducing to about 70 ms has been proposed.
제1도는 상술한 종래의 다층 절연막을 형성하는 방법을 설명하기 위한 단면도이다. 먼저, 반도체기판(1) 상에 유전상수가 약 3.9인 산화막(3)을 형성한다. 다음에, 상기 산화막(3) 상에 산화막에 비하여 유전상수가 높은 실리콘질화막(5)을 형성한다. 이어서, 도시하지는 않았으나 상기 실리콘질화막(5) 상에 게이트 전극을 도우핑된 폴리실리콘막으로 형성한다. 여기서, 상기 반도체기판(1)은 트랜지스터의 경우에 실리콘 웨이퍼에 해당된다. 따라서, 상기 산화막(3) 및 상기 실리콘질화막(5)은 트랜지스터의 게이트 절연막으로 사용될 수 있다.1 is a cross-sectional view for explaining a method of forming the conventional multilayer insulating film described above. First, an oxide film 3 having a dielectric constant of about 3.9 is formed on the semiconductor substrate 1. Next, a silicon nitride film 5 having a higher dielectric constant than the oxide film is formed on the oxide film 3. Subsequently, although not shown, a gate electrode is formed of a doped polysilicon film on the silicon nitride film 5. Here, the semiconductor substrate 1 corresponds to a silicon wafer in the case of a transistor. Therefore, the oxide film 3 and the silicon nitride film 5 can be used as the gate insulating film of the transistor.
이때, 상기 산화막(3) 두께 및 상기 실리콘질화막(5) 두께의 한계는 각각 25Å 및 70Å 내지 80Å이다. 이는, 상술한 두께보다 더 얇은 두께로 형성할 경우 5 Volt의 전압에서 게이트 절연막을 통하여 흐르는 누설전류가 일반적인 상한선인 1 펨토 암페어(femto ampere:10-15ampere)/㎛2이상의 값을 보이기 때문이다. 따라서, 게이트 절연막을 산화막 및 실리콘질화막으로 가장 얇게 형성할 수 있는 한계를 산화막에 대한 등가두께로 환산해 보면, 다음의 식에 의해 구해질 수 있다.At this time, the limits of the thickness of the oxide film 3 and the thickness of the silicon nitride film 5 are 25 kPa and 70 kPa to 80 kPa, respectively. This is because the leakage current flowing through the gate insulating film at a voltage of 5 Volt when the thickness is thinner than the above-described thickness shows a value of 1 femto ampere ( 10-15 ampere) / μm 2 or more, which is a general upper limit. . Therefore, when the limit for forming the gate insulating film as the thinnest of the oxide film and the silicon nitride film is converted into the equivalent thickness with respect to the oxide film, it can be obtained by the following equation.
Tox eq. =Tox + Tsin(εox/εsin)Tox eq. = Tox + Tsin (εox / εsin)
여기서, Tox eq.는 상기 산화막 및 실리콘질화막이 적층된 다층 절연막을 하나의 산화막으로 환산한 등가두께이고, Tox는 상기 산화막의 물리적 두께이고, Tsin은 상기 실리콘질화막의 물리적 두께이고, εox는 산화막의 유전상수이고, εsin은 실리콘질화막의 유전상수이다.Here, Tox eq. Is an equivalent thickness obtained by converting the multilayer insulating film on which the oxide film and the silicon nitride film are stacked into one oxide film, Tox is the physical thickness of the oxide film, Tsin is the physical thickness of the silicon nitride film, and εox is the oxide film. Dielectric constant, εsin is the dielectric constant of the silicon nitride film.
상기 식에 의하면, 25Å의 산화막과 70Å의 실리콘질화막이 차례로 적층된 다층 절연막을 산화막으로 환산한 등가두께는 산화막의 유전상수 및 실리콘질화막의 유전상수가 각각 3.9 및 7.8일 경우에 약 60Å임을 알 수 있다.According to the above equation, it can be seen that the equivalent thickness obtained by converting the multilayer insulating film in which the 25 Å oxide film and the 70 실리콘 silicon nitride film are sequentially stacked into the oxide film is about 60 에 when the dielectric constant of the oxide film and the dielectric constant of the silicon nitride film are 3.9 and 7.8, respectively. have.
상술한 바와 같이 종래의 다층절연막 형성방법은 산화막에 대한 등가두께를 60Å보다 얇게 형성할 경우 누설전류가 허용치 이상의 값을 보이는 문제점을 가지므로, 산화막 등가두께로 60Å보다 얇은 절연막이 요구되는 초고집적 반도체장치의 트랜지스터의 게이트 절연막을 형성하는 방법으로 적합하지 않다.As described above, the conventional multilayer insulating film forming method has a problem that the leakage current shows a value higher than the allowable value when the equivalent thickness of the oxide film is made thinner than 60 mA, and thus an ultra-high density semiconductor which requires an insulating film thinner than 60 mA by the equivalent thickness of the oxide film. It is not suitable as a method of forming the gate insulating film of the transistor of the apparatus.
따라서, 본 발명의 목적 산화막 등가두께로 60Å보다 얇은 두께를 갖는 트랜지스터의 게이트 절연막을 형성할 수 있는 반도체장치의 다층 절연막 형성방법을 제공하는데 있다.Accordingly, it is an object of the present invention to provide a method for forming a multilayer insulating film of a semiconductor device capable of forming a gate insulating film of a transistor having a thickness smaller than 60 kV in an oxide film equivalent thickness.
상기 목적을 달성하기 위하여 본 발명은,The present invention to achieve the above object,
반도체기판 상에 실리콘질화막을 형성하는 단계;Forming a silicon nitride film on the semiconductor substrate;
상기 실리콘질화막 상에 옥시나이트라이드막을 형성하는 단계;Forming an oxynitride film on the silicon nitride film;
상기 옥시나이트라이드막 상에 고유전막을 형성하는 단계;Forming a high dielectric film on the oxynitride film;
상기 고유전막이 안정된 조성비를 갖도록 상기 결과물을 산소가스 및 오존 분위기에서 열처리하는 단계; 및Heat-treating the resultant product in an oxygen gas and ozone atmosphere so that the high dielectric film has a stable composition ratio; And
상기 열처리된 고유전막 상에 절연막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체장치의 다층 절연막 형성방법을 제공한다.It provides a method for forming a multilayer insulating film of a semiconductor device comprising the step of forming an insulating film on the heat-treated high-k dielectric film.
여기서, 상기 실리콘질화막은 반도체기판을 암모니아 분위기에서 급속열처리하여 형성하는 것이 바람직하다.Here, the silicon nitride film is preferably formed by rapid thermal treatment of the semiconductor substrate in an ammonia atmosphere.
또한, 상기 옥시나이트라이드막은 상기 실리콘질화막을 산소 가스 분위기에서 급속 열처리하여 형성하는 것이 바람직하다.In addition, the oxynitride film is preferably formed by rapid heat treatment of the silicon nitride film in an oxygen gas atmosphere.
또한, 상기 고유전막은 LPCVD 방법에 의한 탄탈륨 산화막으로 형성하는 것이 바람직하다.In addition, the high dielectric film is preferably formed of a tantalum oxide film by the LPCVD method.
또한, 상기 절연막은 CVD 방법에 의한 산화막으로 형성하는 것이 바람직하다.The insulating film is preferably formed of an oxide film by the CVD method.
본 발명에 의하면, 안정된 조성비를 갖는 고유전막을 포함하는 다층 절연막을 형성할 수 있으므로 산화막 등가두께를 크게 감소시키면서 누설전류 특성을 개선시킬 수 있다. 따라서, 본 발명에 의한 다층 절연막을 트랜지스터의 게이트 절연막으로 사용할 경우 트랜지스터의 전기적 특성을 크게 향상시킬 수 있다.According to the present invention, since a multilayer insulating film including a high dielectric film having a stable composition ratio can be formed, the leakage current characteristic can be improved while greatly reducing the oxide film equivalent thickness. Therefore, when the multilayer insulating film according to the present invention is used as the gate insulating film of the transistor, the electrical characteristics of the transistor can be greatly improved.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제2도 및 제3도는 본 발명의 실시예에 따른 다층 절연막을 형성하는 방법을 설명하기 위한 단면도들이다.2 and 3 are cross-sectional views illustrating a method of forming a multilayer insulating film according to an exemplary embodiment of the present invention.
제2도는 실리콘질화막(13), 옥시나이트라이드막(15), 및 고유전막(17)을 차례로 형성하는 단계를 설명하기 위한 단면도이다.2 is a cross-sectional view for explaining the steps of sequentially forming the silicon nitride film 13, the oxynitride film 15, and the high dielectric film 17.
구체적으로, 반도체기판(11)을 800℃ 내지 900℃의 온도와 암모니아 가스 분위기에서 소정의 시간, 예컨대 1분동안 급속열처리하여 반도체기판(11)의 표면에 실리콘질화막(13)을 형성한다. 이때, 실리콘질화막(13)은 약 12Å의 두께로 형성된다. 이어서, 상기 실리콘질화막(13)이 형성된 결과물을 750℃ 내지 850℃의 온도와 산소 가스 분위기에서 급속열처리하여 실리콘질화막(13)상에 옥시나이트라이드막(15)을 형성한다. 여기서, 옥시나이트바이드막(15)은 약 2분간 급속열처리하여 16Å의 두께로 형성하는 것이 바람직하다.Specifically, the silicon nitride film 13 is formed on the surface of the semiconductor substrate 11 by rapidly heat-treating the semiconductor substrate 11 at a temperature of 800 ° C to 900 ° C and ammonia gas atmosphere for a predetermined time, for example, for 1 minute. At this time, the silicon nitride film 13 is formed to a thickness of about 12Å. Subsequently, the oxynitride film 15 is formed on the silicon nitride film 13 by rapidly heat-treating the resultant product on which the silicon nitride film 13 is formed at a temperature of 750 ° C to 850 ° C and an oxygen gas atmosphere. Here, the oxynitide film 15 is preferably formed by a rapid heat treatment for about 2 minutes to a thickness of 16 kPa.
다음에, 상기 결과물 전면에 고유전막(17), 예컨대 탄탈륨 산화막을 400℃ 내지 450℃의 온도와 300mTorr의 압력 분위기에서 타이타늄 에톡사이드(Ta(OC2H5)5)를 주원료로하는 LPCVD 방법으로 형성한다.Next, the high-k dielectric film 17, for example, a tantalum oxide film, on the entire surface of the resultant is a LPCVD method using titanium ethoxide (Ta (OC 2 H 5 ) 5 ) as a main raw material at a temperature of 400 ° C to 450 ° C and a pressure of 300mTorr Form.
여기서, 상기 탄탈륨 산화막은 유전상수가 25 내지 26인 고유전막이며, 90Å 내지 100Å의 두께로 형성하는 것이 바람직하다.Here, the tantalum oxide film is a high dielectric film having a dielectric constant of 25 to 26, and preferably formed in a thickness of 90 kPa to 100 kPa.
제3도는 오존 열처리된 고유전막(17a) 및 산화막(19)을 형성하는 단계를 설명하기 위한 단면도이다. 좀 더 상세히, 상기 고유전막(17)이 형성된 결과물을 오존(O3) 및 산소 가스와 250℃ 내지 350℃의 온도 분위기에서 열처리한다. 이와 같이 오존 열처리를 하는 이유는 제2도에서 CVD 방법으로 형성된 고유전막(17), 즉 탄탈륨 산화막이 탄탈륨 원자에 비하여 산소원자가 부족한 상태의 조성물이므로 산소원자를 충분히 제공하여 안정된 탄탈륨 산화막을 형성하기 위함이다.3 is a cross-sectional view for explaining the steps of forming the ozone heat treated high dielectric film 17a and oxide film 19. In more detail, the resulting high dielectric film 17 is heat-treated with ozone (O 3 ) and oxygen gas in a temperature atmosphere of 250 ℃ to 350 ℃. The reason for this ozone heat treatment is that the high-k dielectric film 17 formed by the CVD method in FIG. 2, that is, the tantalum oxide film is a composition in which oxygen atoms are inferior to the tantalum atoms, so that sufficient oxygen atoms are provided to form a stable tantalum oxide film. to be.
한편, 제1도에서 설명한 실리콘 질화막(13) 및 옥시나이트라이드막(15)은 상기 고유전막(17), 즉 탄탈륨 산화막이 실리콘 기판(11)과 직접 접촉하도록 형성될 경우에 탄탈륨 산화막과 반도체기판, 예컨대 실리콘기판이 후속 열공정시 서로 반응하여 이들 사이의 계면에 산화막 및 탄탈륨막이 형성되는 것을 방지하기 위하여 형성하는 것이다. 이는, 탄탈륨 산화막과 실리콘기판이 서로 반응하여 그들 사이에 산화막 및 탄탈륨막이 형성될 경우 절연막의 실제두께가 증가되면서 누설전류도 증가하는 현상이 발생하기 때문이다.Meanwhile, the silicon nitride film 13 and the oxynitride film 15 described in FIG. 1 are formed of the tantalum oxide film and the semiconductor substrate when the high dielectric film 17, that is, the tantalum oxide film is formed in direct contact with the silicon substrate 11. For example, the silicon substrate is formed in order to prevent the oxide film and the tantalum film from forming at the interface between them by reacting with each other in a subsequent thermal process. This is because when the tantalum oxide film and the silicon substrate react with each other and an oxide film and a tantalum film are formed therebetween, the leakage current also increases as the actual thickness of the insulating film increases.
다음에, 상기 오존 열처리된 고유전막(17a) 상에 절연막(19), 예컨대 산화막을 CVD 방법으로 얇게 형성한다. 여기서, 상기 산화막(19)은 10Å 정도의 두께로 형성하는 것이 바람직하며, 후속공정에 의해 상기 절연막(19) 상에 형성되는 게이트 전극(도시하지 않음) 또는 커패시터의 상부전극(도시하지 않음)과 상기 오존 열처리된 고유전막(17a)이 서로 반응하는 것을 방지하는 역할을 한다. 이어서, 상기 결과물을 산소 분위기에서 어닐링시킨다.Next, an insulating film 19, for example, an oxide film, is thinly formed on the ozone heat treated high dielectric film 17a by the CVD method. Here, the oxide film 19 is preferably formed to a thickness of about 10Å, the gate electrode (not shown) or the upper electrode (not shown) of the capacitor formed on the insulating film 19 by a subsequent process and The ozone heat treated high-k dielectric layer 17a serves to prevent the reaction with each other. The resultant is then annealed in an oxygen atmosphere.
이와 같이 실리콘질화막(13), 옥시나이트라이드막(15), 오존 열처리된 고유전막(17a) 및 절연막(19)이 차례로 적층된 다층 절연막의 산화막에 대한 등가두께를 알아보기 위하여, 앞에서 보여진 식을 이용하여 각각의 절연막을 산화막으로 환산한 두께를 구해보면, 실리콘질화막(13)의 산화막 등가두께는 약 6Å 옥시나이트라이드막(15)의 산화막 등가두께는 16Å 이하, 오존 열처리된 고유전막(17a), 즉 탄탈륨 산화막의 산화막 등가두께는 약 15Å, 그리고 절연막(19), 즉 산화막은 10Å이다. 따라서, 이들 각각의 산화막 등가두께를 모두 합하면 약 47Å이므로, 본 발명에 의한 다층 절연막은 종래의 다층 절연막에 비하여 더욱 얇은 산화막을 형성하는 효과를 갖는다. 이와 같이 본 발명에 의한 다층 절연막을 형성하는 경우에 고유전막, 즉 탄탈륨 산화막 또한 안정된 조성비를 가지므로 우수한 누설전류 특성, 즉 1 펨토 암페어/㎛2이하의 누설전류 특성을 보인다.As described above, in order to determine the equivalent thickness of the oxide film of the multilayer insulating film in which the silicon nitride film 13, the oxynitride film 15, the ozone heat treated high dielectric film 17a, and the insulating film 19 are sequentially stacked, The thickness obtained by converting each insulating film into an oxide film by using the film was obtained. That is, the equivalent thickness of the oxide film of the tantalum oxide film is about 15 GPa, and the insulating film 19, that is, the oxide film is 10 GPa. Therefore, since all of these oxide film equivalent thicknesses are added together, it is about 47 GPa, and the multilayer insulating film according to the present invention has the effect of forming a thinner oxide film as compared with the conventional multilayer insulating film. As described above, in the case of forming the multilayer insulating film according to the present invention, the high dielectric film, that is, the tantalum oxide film also has a stable composition ratio, thereby exhibiting excellent leakage current characteristics, that is, leakage current characteristics of 1 femto ampere / μm 2 or less.
상술한 바와 같이 본 발명의 실시예에 의하면, 탄탈륨산화막과 같은 고유전막을 포함하는 다층 절연막을 50Å 이하의 얇은 산화막 등가두께를 갖도록 형성할 수 있다. 따라서, 본 발명에 의한 다층 절연막을 트랜지스터의 게이트 절연막으로 사용할 경우 초고집적 반도체장치의 트랜지스터의 전기적 특성을 향상시킬 수 있다.As described above, according to the embodiment of the present invention, a multilayer insulating film including a high dielectric film such as a tantalum oxide film can be formed to have a thin oxide film equivalent thickness of 50 kPa or less. Therefore, when the multilayer insulating film according to the present invention is used as the gate insulating film of the transistor, the electrical characteristics of the transistor of the ultra-high density semiconductor device can be improved.
본 발명이 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상내에서 당 분야에서 통상의 지식을 가진자에 의하여 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.
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