JP2002232094A - Multilayer interconnection board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer interconnection board of high workability in assembling process and high accuracy at assembling. SOLUTION: The multilayer interconnection board is provided which is an aggregate of a plurality of chips and where a plurality of identification marks provided to each of interconnection layers are recognized from a surface.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board on which electronic components are mounted.

[0002]

2. Description of the Related Art In recent years, a multilayer wiring board on which electronic components are mounted has been required to be thinner, smaller, more multilayered, more accurate, and the like. In a ceramic or resin system, a multi-layer wiring board, which is a set of a plurality of chips, is aligned with a sheet for each wiring layer by guide pins,
Press-formed, fired or cured and divided into chips. The wiring of the divided chips is recognized, the position is corrected, electronic components are mounted at correction data positions, and sometimes wire bonding is performed.

[0003]

However, mounting electronic components using divided chips is inferior in workability. As the thickness is reduced and the size is reduced, there is a problem that the position is corrected in a short distance in an automatic assembling process, which causes inaccuracy.

[0004]

SUMMARY OF THE INVENTION In a multilayer wiring board which is a set of a plurality of chips and has an opening for mounting a component and a wiring layer, a plurality of recognition marks provided for each wiring layer have a multi-layer wiring structure. This is a multilayer wiring board that can be recognized from the surface of the board. The multi-layer wiring board is an assembly process of recognizing the recognition mark in a state of being a set of a plurality of chips, correcting the position, mounting an electronic component at the correction data position, and performing wire bonding at the correction data position. Therefore, it is possible to provide a multi-layer wiring board that solves the problem that the workability is good and the accuracy is increased because the position is corrected by using a plurality of distant recognition marks.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a multilayer wiring board according to the present invention will be described in detail. The present invention is not limited to the form and the number of layers described below, and a plurality of recognition marks provided simultaneously with the wiring circuit for each wiring layer can be recognized from the surface of the laminated multilayer wiring board. Is a multi-layer wiring board in an aggregated state (sheet state) of chips. (FIGS. 1 and 2
Will be described with reference to FIG. )

The multilayer wiring board is not limited to ceramic, glass, resin, and the like. In the resin-based subtractive method, a wiring circuit is left for each wiring layer by etching, and at the same time, a recognition mark is left, and the wiring layers are aligned with the guide pin holes 6 and laminated by vacuum heating. The resin layer is removed by counterbore processing so that the recognition mark 1-1 can be recognized from the surface, and the recognition window 1-11 is formed.
Before the lamination, the resin of the wiring layer located on the upper surface of the recognition mark position is removed to a greater extent than the recognition mark 1-1, and the recognition window 1-11 is formed and laminated. And a multi-layer wiring board that can be used. In the resin-based additive method, the recognition mark 1-1 is formed at the same time when the wiring circuit is formed in the wiring layer, the resin layer is applied, and the resin at the recognition mark position is removed to a greater extent than the recognition mark to make the recognition window 1-11. To form When a wiring layer is further formed, the recognition mark 2-1 is formed simultaneously with the wiring circuit, a resin layer is applied, and the resin at the position of the recognition mark is removed to a greater extent than the recognition mark to form the recognition window 2-11. A multi-layer wiring board in which the recognition marks of the respective wiring layers can be recognized from the recognition window from the front surface by repeating the required number of times. In the resin system, a multilayer wiring board which is an aggregate of a large number of chips in a sheet state prepared for individual chip formation by a pushback method, a division groove forming method, or the like can be provided.

A ceramic multilayer wiring board is prepared by casting a slurry in which ceramic powder, a sintering aid, an organic binder, a solvent or water, or the like is dispersed on a support with a doctor blade to a predetermined thickness, and then drying the slurry. Step of forming a soft ceramic green sheet having plasticity (doctor blade method), forming guide pin holes 6 and the like on the ceramic green sheet A, and printing and applying a conductive paste to form a first wiring layer (wiring circuit). At the same time, the first layer recognition mark 1-1 is formed. Guide pin hole 6, opening 8, first layer recognition window 1-1 in B ceramic green sheet
1 and the like, and a conductive paste is printed and applied to form the second layer recognition mark 2-1 together with the second wiring layer 3. A guide pin hole 6, an opening 8, a first layer recognition window, a second layer recognition window, and the like are formed in a C ceramic green sheet. A,
The three or more ceramic green sheets of B and C or the number of ceramic green sheets required for the configuration are aligned, heated, pressed and laminated, and the break grooves 5 which can be divided into a plurality of chips later are formed vertically. Formed horizontally and sintered in a nitrogen atmosphere furnace with hydrogen added to form a multi-layer wiring board in a sheet state, in which recognition marks provided for each wiring layer can be recognized from the surface.

The multilayer wiring board manufactured in this manner is an aggregate (sheet state) of a large number of chips, and a recognition mark provided for each wiring layer simultaneously with the formation of the wiring layer is provided on the surface of the multilayer wiring board. Therefore, the position of the recognition mark (generally three) can be recognized, the relationship with the design position can be corrected and calculated, and the electronic component can be assembled based on the corrected calculated value. Workability is good because assembly is performed in a sheet state, which is an aggregate of a large number of chips, and the accuracy of correction calculation values is significantly improved because the distance between a plurality of recognition marks provided in the sheet state is large. By arranging more recognition marks around the multilayer wiring substrate, shrinkage due to sintering of the ceramic and process distortion of the resin substrate can be corrected in a specific direction, and the accuracy is further improved.

[0009]

(Example 1) Alumina ceramic substrate was sintered to give a so-called alumina of 96%, and alumina powder and MgO, SiO ₂ , CaO and TiO ₂ were mixed, and polyvinyl butyral resin and toluene / methanol / ME were mixed.
Add the K mixed solution, mix / pulverize / disperse with a ball mill,
Alumina ceramic green sheets having plasticity were prepared by a doctor blade method. (Thickness 0.3 mm, 0.
2mm)

[0010] 100 * 80mm size to be the first layer,
A back electrode hole 7 and a guide pin hole 6 are formed on a 0.3 mm-thick alumina ceramic green sheet according to design by a punching machine method, and a plurality of first wiring layers 4 and first layer recognition marks (1 mm having a diameter of 0.6 mm) are formed. -1, 1-2, 1
-3 are formed in the peripheral dummy portion) and the end surface electrode (the extraction electrode when a chip of a laminated body is formed, the back surface electrode hole 7).
) Was simultaneously screen-printed and coated with a tungsten paste for an electrode, and dried to obtain a sheet A.

According to the design, a backside electrode hole 7, a guide pin hole 6, an opening 8 and a first layer recognition window (1-11,
Three holes 1-22 and 1-33 are formed at the position of the first layer recognition mark of the first layer by a punching machine method, and a plurality of second wiring layers 3 and second layer recognition marks ( Three 2-1, 2-2, and 2-3 pieces having a diameter of 0.6 mm are formed in the peripheral dummy portion) and an end surface electrode (formed in the back surface electrode hole 7 with an extraction electrode when a laminated chip is formed) is used for the electrode. Sheet B was simultaneously applied by screen printing with a tungsten paste and dried.

According to the design, guide pin holes 6 are formed on a 0.3 mm alumina ceramic green sheet serving as a third layer.
Opening 8, first layer recognition window (1-11, 1-22, 1-3)
3 at the position of the first recognition mark of the first layer and a through-hole having a diameter of 3 mm) and the second recognition window (2-11, 2-22, 2-33)
Were formed by punching machine method at the position of the second layer recognition mark of the second layer to form a sheet C.

The sheet A, the sheet B and the sheet C are positioned and stacked with reference to the guide pin hole 6, and a laminated alumina ceramic green sheet is integrated by heating and pressing (heating temperature: 70 ° C., heating temperature: 70 ° C.). Pressure: 7.06M
Pa, pressurization time: 2 minutes), a tungsten paste is printed and coated by a screen printing method from the upper surface around the chip and dried to form a metallized layer for attaching the lid, and is approximately 0 mm from the upper surface of the laminated alumina ceramic green sheet. .25m
A V-shaped break groove 5 for chip division was formed vertically and horizontally to a depth of m, and a break groove was formed at a position opposite to the break groove 5 from the back surface to a depth of 0.15 mm.
A plurality of vertical and horizontal break grooves surround the chip, and secure a dummy portion around the sheet as a space for enabling a configuration of a recognition mark, a recognition window, a guide pin hole, and the like.

The laminated alumina ceramic green sheet having the break grooves formed therein is sintered in a reducing atmosphere furnace (22% hydrogen, 78% nitrogen, peak temperature 1600 ° C., 120 minutes) to produce a multilayer wiring board made of alumina. Further, in order to prevent oxidation and improve the bonding property, a wiring layer and electrodes on the surface of the multilayer wiring board were subjected to electroless Ni plating and electroless Au plating surface treatment by a usual method to produce a multilayer wiring board. (FIGS. 1 and 2)

In the multilayer wiring board manufactured as described above, the recognition mark provided for each wiring layer can be recognized from each recognition window of the multilayer wiring board, and the mounting and mounting of components can be performed.
For the assembly, read the recognition mark with the recognition camera, correct the target coordinates of the wiring layer that has shrunk and deformed during ceramic sintering with the recognition mark reading data (correct the deviation from the design value), Electronic components can be mounted and assembled for each chip using the corrected data. Further, the lid can be accurately placed and sealed on the chip on which the electronic component is mounted and assembled by using the recognition mark. In addition, individual chips (e.g., 5.0 * 3.2 mm size, 2.5 * 2.0 mm for mounting quartz products,
(7 * 7mm size for semiconductor mounting, etc.). The multilayer wiring board manufactured as described above is in a sheet state (several dozens to hundreds of chips can be formed on one sheet).
The workability of assembly is good. The multilayer wiring board manufactured in this way is further improved in accuracy because the position is corrected by three recognition marks at a distance.
Further, in the present embodiment, although the number of layers is three, the same effect can be achieved even with a multilayer wiring board having more layers.

(Example 2) A back electrode hole 7 and a guide pin hole 6 are formed on a glass epoxy substrate having a thickness of 0.3 mm with an 18 μm thick copper foil bonded on both sides by an NC drill machine according to design, and a back electrode hole is formed. Then, a through hole is formed by an electroless copper plating method and an electrolytic copper plating method, and a pattern that leaves a plurality of first wiring layers 4 and three first layer recognition marks (formed on peripheral dummy portions) is formed by a photo etching method. , Additive method [(approximately 100 μm
Laminated photosensitive resin film, and exposed, cured and peeled according to design, back electrode hole 7, guide pin hole 6,
The resin corresponding to the opening 8 and the first layer recognition window is removed to form an insulating resin layer), (a photoresist film is laminated on the insulating resin layer, and a plurality of second wiring layers 3 and 2 The layer recognition mark and the end surface electrode are formed by exposure, development, and plating)] to form the end surface electrode, the second wiring layer, the second layer recognition mark, and the like, and further, the opening and the first layer recognition window are formed by an additive method. And an insulating resin layer having a second layer recognition window, guide pin holes, and the like. Further, a multilayer wiring board composed of a large number of chips having a size of 7 * 7 mm was manufactured using a mold for pushback. (The sheet design of the present embodiment is slightly different from FIGS. 1 and 2 in that a dummy portion is formed between chips and the position of the back surface electrode hole is formed in the chip area.)

The resin-based multilayer wiring board manufactured as described above is mounted and assembled with each recognition mark as in the first embodiment, so that it can be accurately positioned and sealed, and can be handled in a sheet state. As a result, assembling workability is good and accuracy is further improved.

[0018]

The multilayer wiring board according to the present invention is an aggregate (sheet state) of a large number of chips, and the recognition mark provided simultaneously with the wiring layer for each wiring layer is recognized from the surface of the multilayer wiring board. Therefore, the position of the recognition mark can be recognized, the relationship with the design value can be corrected and calculated, and the electronic component can be assembled based on the corrected calculated value. Workability is good because assembly is performed in a sheet state, which is an aggregate of many chips. Further, since the distance between the plurality of recognition marks provided in the sheet state is large, the accuracy of the correction calculation value is significantly improved.

[0019]

[Brief description of the drawings]

FIG. 1 is a schematic top view showing one embodiment of a multilayer wiring board according to the present invention.

FIG. 2 is a schematic view of an A-A ′ section of FIG. 1;

[0020]

[Explanation of symbols]

 1-1, 1-2, 1-3 First-layer recognition mark 1-11, 1-22, 1-33 First-layer recognition window 2-1, 2-2, 2-3 Second-layer recognition mark 2- 11, 22, 22-33 Second layer recognition window 3 Second wiring layer 4 First wiring layer 5 Break groove 6 Guide pin hole 7 Back electrode hole 8 Opening

Claims (1)

[Claims] 1. A multilayer wiring board, which is a set of a plurality of chips and has an opening for mounting components and a wiring layer, wherein a plurality of recognition marks provided for each wiring layer are arranged from the surface of the multilayer wiring board. A multilayer wiring board characterized by being recognizable.