JP2002231936A - Method of preventing formation of bump on side wall of silicon metal layer of gate electrode and method of manufacturing gate electrode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of preventing the formation of bumps on the side wall of a silicon metal layer of a gate electrode and to provide a method of manufacturing the gate electrode. SOLUTION: The method comprises a step (a) of providing a gate electrode structure formed on a semiconductor substrate, a step (b) of conducting a short- time annealing (RTA) using a mixed gas of a nitrogen gas and a hydrogen gas on the gate electrode structure, and a step (c) of conducting a short-time thermal oxidation on the gate electrode structure. The method comprises a step (a) of providing a chamber and a gate electrode structure formed on a semiconductor substrate, a step (b) of placing the gate electrode structure in the chamber and clearing an oxygen gas from the chamber, a step (c) of conducting a short-time annealing (RTA) on the gate electrode structure, and a step (d) of conducting a short-time thermal oxidation on the gate electrode structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for preventing a bump from being formed on a side wall of a metal silicide layer, and more particularly to a method for preventing a bump from being formed on a side wall of a metal silicide layer of a gate electrode.

[0002]

2. Description of the Related Art As the size of semiconductor components becomes smaller and smaller, the yield rate of semiconductor components often decreases due to problems during semiconductor manufacturing. In particular, in the case of a gate electrode used in a storage unit, the quality and function of a semiconductor component vary considerably depending on the presence or absence of a defect.

FIGS. 1 to 7 show a metal oxide semiconductor field effect transistor (MOSF) used in a conventional storage unit.
3 shows a method for producing ET).

Conventionally, as shown in FIGS. 1 to 7, a method of manufacturing a MOSFET is as follows. First, as shown in FIG. 1, a gate oxide layer 11 is formed on a silicon substrate 10 by a thermal oxidation method.

[0005] Next, as shown in FIG. 2, a polycrystalline silicon layer 12 is formed on the gate oxide layer 11 by a chemical vapor deposition (CVD) method. After that, a high concentration impurity, for example, phosphorus or arsenic is added into the polycrystalline silicon layer 12 by a thermal diffusion method or an ion implantation method 121. This allows
The resistance of this layer as a gate conductive layer is reduced.

Next, as shown in FIG. 3, a tungsten silicon layer 13 and a silicon nitride layer 14 are sequentially deposited on the polycrystalline silicon layer 12 by a CVD method. Here, the silicon nitride layer 14 is used as a mask layer.

Next, as shown in FIG. 4, the silicon nitride layer 14 is patterned by photolithography and dry etching to define a gate electrode area.

Next, as shown in FIG. 5, etching is performed using the silicon nitride layer 14 as a mask layer to form a gate electrode structure 16. The gate electrode structure 16 includes a silicon nitride layer 14, a tungsten silicon layer 13, a polycrystalline silicon layer 12, and a gate oxide layer 11.

Next, as shown in FIG. 6, in order to reduce the resistance of the tungsten silicon layer 13 having a higher resistance, after performing dry etching, a nitrogen gas is fed into the chamber and then annealed for a short time. (RTA). This RTA step can also help repair any damage to the gate electrode 16 or silicon substrate 10 due to a previously performed dry etch. In addition, since a leakage current due to the tip discharge in the gate oxide layer 11 is often generated and the withstand voltage of the gate electrode 16 is reduced, oxygen gas is sent into the chamber after a short annealing, and then a short heat treatment is performed. Oxidation (RTO) must be performed. As a result, the oxide layer 15 is formed on the outer periphery of the gate electrode structure 16, the corners of the gate oxide layer 11 are rounded, and the tip discharge in the gate oxide layer is eliminated.

Next, as shown in FIG. 7, when the spacer 17, the source electrode 18 and the drain electrode 19 are manufactured after the gate electrode structure 16 is completed, the structure of the MOSFET is formed.

[0011]

However, the prior art has the following disadvantages.

As shown in FIG. 6, after performing annealing for a short time, thermal oxidation is performed for a short time in the same chamber. (See FIG. 8). The formation of the bumps 21 is due to the oxygen gas remaining in the chamber, that is, the same treatment is performed on the wafer to be processed this time while the oxygen gas remains in the chamber after a short time oxidizing annealing is performed on the wafer to be previously processed. After a short-time annealing and a short-time thermal oxidation are performed in the chamber, bumps 21 are formed on the wafer to be handled this time. The bump 21 is an oxide composed of an oxide of tungsten and silicon dioxide, which causes a short circuit and lowers the yield of non-defective semiconductor components.

[0013] In order to solve the above problems, it is a main object of the present invention to provide a method for preventing a bump from being formed on a side wall of a metal silicide layer of a gate electrode and a method for manufacturing a gate electrode. It is in.

Another object of the present invention is to provide a method for improving the yield rate of semiconductor components.

Further, the present invention seeks to provide a method for improving the quality and function of a semiconductor component.

[0016]

In order to achieve the above object, the present invention has the following configuration.

According to a first aspect of the present invention, there is provided a method for preventing a bump from being formed on a side wall of a metal silicide layer of a gate electrode, comprising the steps of: (a) providing a gate electrode structure formed on a semiconductor substrate; (B) short-time annealing using a mixed gas containing nitrogen gas and hydrogen gas for the gate electrode structure;
And (c) applying short-time thermal oxidation (RTO) to the gate electrode structure.

According to a second aspect of the present invention, there is provided a method for preventing a bump from being formed on a side wall of a metal silicide layer of a gate electrode, and (a) providing a chamber and a gate electrode structure formed on a semiconductor substrate. (B) placing the gate electrode structure in the chamber and clearing oxygen gas in the chamber; and (c) subjecting the gate electrode structure to short-time annealing (RTA). And (d) applying short-time thermal oxidation (RTO) to the gate electrode structure.

According to a third aspect of the present invention, there is provided the bump generation preventing method according to the first or second aspect, wherein the semiconductor substrate is a silicon substrate.

According to a fourth aspect of the present invention, there is provided the bump generation preventing method according to the first or second aspect, wherein the metal silicide layer is a tungsten silicon layer.

According to a fifth aspect of the present invention, there is provided the bump formation preventing method according to the first or second aspect, wherein the gate electrode structure comprises a gate oxide layer, a polycrystalline silicon layer, and a metal silicide layer. And

The invention according to claim 6 is the bump generation preventing method according to claim 5, wherein the gate electrode structure further includes a silicon nitride layer.

According to a seventh aspect of the present invention, there is provided the bump formation preventing method according to the first aspect, wherein the molar concentration of the hydrogen gas contained in the mixed gas is 5-50% of the mixed gas. Features.

The invention according to claim 8 is the bump formation preventing method according to claim 1, wherein the short-time annealing is performed at 700-950 ° C.

According to a ninth aspect of the present invention, there is provided the bump generation preventing method according to the seventh aspect, wherein the short annealing is performed for 0.5 to 4 minutes.

The invention according to claim 10 is the first invention.
The method according to any of the preceding claims, wherein the short-time thermal oxidation is performed at 950-1200C.

[0027] The invention according to claim 11 is the invention according to claim 1.
0, wherein the short-time thermal oxidation is performed for 1 to 5 minutes.

The invention according to claim 12 is the invention according to claim 2.
The method for preventing bump formation according to the above, wherein the oxygen gas is cleared by feeding nitrogen gas into the chamber.

[0029] Further, the invention according to claim 13 is based on claim 2.
The method for preventing bump formation according to the above, wherein oxygen gas in the chamber is cleared by vacuum suction.

The invention according to claim 14 is the first invention.
14. The bump generation preventing method according to 2 or 13, wherein the oxygen gas is cleared to be 500 ppm or less.

According to a fifteenth aspect of the present invention, there is provided the bump formation preventing method according to the second aspect, wherein the chamber is used for short-time annealing and short-time thermal oxidation processing, and a single wafer is used for each processing. It is characterized in that it is a chamber that only handles.

The invention according to claim 16 is the invention according to claim 2.
The method for preventing bump formation according to the above, wherein the chamber is a chamber used for short-time annealing and short-time thermal oxidation treatment, and capable of handling a set of a plurality of wafers in each treatment. I do.

Further, the invention described in claim 17 is the same as the claim 2.
The method for preventing bump formation according to the above, further comprising a step (c1) of providing a second chamber after the step (c).

The invention according to claim 18 is the first invention.
7. The bump formation preventing method according to claim 7, wherein the short-time thermal oxidation is performed in the second chamber.

According to a nineteenth aspect of the present invention, there is provided a method of manufacturing a gate electrode, comprising: (a) providing a semiconductor substrate;
(B) forming a gate oxide layer on the semiconductor substrate; (c) forming a polycrystalline silicon layer on the gate oxide layer; and (d) forming a metal silicide layer on the polycrystalline silicon layer. Forming; (e) patterning the metal silicide layer, polycrystalline silicon layer and gate oxide layer to form a gate electrode structure; and (f) mixing the gate electrode structure with nitrogen gas and hydrogen gas. Short-time annealing using gas
(G) subjecting the gate electrode structure to thermal oxidation (RTO) for a short time.

The invention according to claim 20 is the first invention.
10. The method for manufacturing a gate electrode according to item 9, wherein the step (c) is performed.
Is (c1) 5A by ion implantation into the polycrystalline silicon layer.
A step of adding a group ion.

The invention according to claim 21 is the first invention.
10. The method for manufacturing a gate electrode according to item 9, wherein the step (e) is performed.
(E1) forming a mask layer on the metal silicide layer, (e2) patterning the mask layer by photolithography and etching to define a gate electrode area, and (e3) performing dry etching. Accordingly, the method includes a step of forming a gate electrode structure.

Further, the invention according to claim 22 is based on claim 2
2. The method for manufacturing a gate electrode according to claim 1, wherein the mask layer is a silicon nitride layer.

The invention according to claim 23 is the first invention.
10. The method for manufacturing a gate electrode according to 9, wherein the molar concentration of hydrogen gas contained in the mixed gas is 5-50% of the mixed gas.

The invention according to claim 24 is the first invention.
10. The method for manufacturing a gate electrode according to 9, wherein the short-time annealing is performed at 700-950 ° C.

The invention according to claim 25 is the second invention.
5. The method of manufacturing a gate electrode according to claim 4, wherein the short-time annealing is performed for 0.5 to 4 minutes.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and operation of an embodiment of the present invention which achieves the above-mentioned objects and solves the problems of the related art will be described in detail with reference to the accompanying drawings.

Embodiment 1 According to the present invention, a mixed gas containing a nitrogen gas and a hydrogen gas is supplied at the stage of applying the short-time annealing (RTA) in the chamber shown in FIG. Here, the content (molar concentration) of the hydrogen gas is 5 to 50% of the mixed gas, but a content of 10% is preferable. On the other hand, short-time annealing is performed under the conditions of a temperature of 700-950 ° C and a time of 0.5-4 minutes.
The optimal conditions are 830 ° C for 1 minute.

Next, oxygen gas is fed into the same chamber to perform short-time thermal oxidation (RTO). The short-time thermal oxidation is performed at a temperature of 950 to 1200 ° C. for a time of 1 to 5 minutes. The optimal conditions are a temperature of 1080 ° C. and a time of 2.5 minutes.

As described above, oxygen gas may remain in the chamber after short-time thermal oxidation of the wafer to be handled last time. In the case of the present invention, a mixed gas containing nitrogen gas and hydrogen gas is used. Since the transfer is performed, the formation of bumps on the side walls of the tungsten silicon layer 13 in the short-time thermal oxidation stage performed later is prevented (see FIG. 10). This is because the hydrogen gas forms a hydrogen gas thin film 31 (see FIG. 9) on the side wall of the gate electrode at the stage of short-time annealing to stabilize the side wall of the gate electrode 16.

Embodiment 2 As described above, conventionally, short-time annealing and short-time thermal oxidation are performed in the same chamber. When the oxygen gas remains, a bump is formed on the side wall of the tungsten silicon layer. In view of this, according to the present invention, before performing annealing for a short time, supply of nitrogen gas or vacuum suction to reduce oxygen gas remaining in the chamber (for example, to reduce the residual amount to 500 ppm or less). To clear). Immediately thereafter, short-term annealing and short-time thermal oxidation are performed. In this embodiment, there is no need to supply hydrogen gas during annealing for a short time in order to prevent the formation of bumps on the side walls of the tungsten silicon layer. Of course, according to the present invention, regardless of whether a single wafer or a set of multiple wafers is treated at one time when performing the short-time annealing and the short-time thermal oxidation, Even in such a chamber, generation of bumps on the side wall of the tungsten silicon layer can be prevented.

Although those skilled in the art can make variations and modifications based on the present invention, the scope of the present invention is in accordance with the appended claims.

[0048]

The present invention is suitable for preventing a bump from being formed on the side wall of the tungsten silicon layer of the gate electrode, and is also suitable for preventing formation of a bump on the side wall of the metal silicide layer of the gate electrode. ADVANTAGE OF THE INVENTION According to this invention, the non-defective product rate of a semiconductor component and the quality and function of a semiconductor component can be improved. Therefore, the present invention is superior to the prior art and has industrial value.

[0049]

[Brief description of the drawings]

FIG. 1 is a diagram showing a conventional manufacturing method (partial stages) of a MOSFET used for a storage unit.

FIG. 2 is a view showing a stage subsequent to the manufacturing stage of the manufacturing method shown in FIG. 1;

FIG. 3 is a view showing a stage subsequent to the manufacturing stage shown in FIG. 2;

FIG. 4 is a view showing a stage subsequent to the manufacturing stage shown in FIG. 3;

FIG. 5 is a view showing a stage subsequent to the manufacturing stage shown in FIG. 4;

FIG. 6 is a view showing a stage subsequent to the manufacturing stage shown in FIG. 5;

FIG. 7 is a view showing a stage subsequent to the manufacturing stage shown in FIG. 6;

8A and 8B are diagrams showing a gate electrode structure according to a conventional manufacturing method, wherein FIG. 8A is a cross-sectional view and FIG. 8B is a top view.

FIG. 9 is a diagram showing stabilization of a gate electrode side wall with hydrogen gas.

FIG. 10 is a diagram showing a gate electrode structure according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Silicon substrate 11 Gate oxide layer 12 Polycrystalline silicon layer 13 Tungsten silicon layer 14 Silicon nitride layer 15 Thermal oxide layer 16 Gate electrode structure 17 Spacer 18 Source electrode 19 Drain electrode 21 Bump 31 Hydrogen gas thin film 121 Ion implantation

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Xu Heng Kai, Taiwan, Hsinchu City, China, China, China

Claims (25)

[Claims] 1. A method for preventing a bump from being formed on a side wall of a metal silicide layer of a gate electrode, comprising: (a) providing a gate electrode structure formed on a semiconductor substrate; and (b) providing the gate electrode. A step of subjecting the structure to a short-time annealing using a mixed gas containing nitrogen gas and hydrogen gas; and (c) a step of performing a short-time thermal oxidation to the gate electrode structure. To prevent bump formation. 2. A method for preventing a bump from being formed on a sidewall of a metal silicide layer of a gate electrode, comprising: (a) providing a chamber and a gate electrode structure formed on a semiconductor substrate; (b) Placing the gate electrode structure in the chamber and clearing oxygen gas in the chamber; (c) subjecting the gate electrode structure to annealing for a short time; A method of preventing the formation of bumps on the side wall of the metal silicide layer of the gate electrode, which comprises performing a short-time thermal oxidation. 3. The method according to claim 1, wherein the semiconductor substrate is a silicon substrate. 4. The method according to claim 1, wherein a bump is formed on a side wall of the metal silicide layer of the gate electrode. 4. The method as claimed in claim 1, wherein the metal silicide layer is a tungsten silicon layer. 5. The method according to claim 1, wherein the gate electrode structure comprises a gate oxide layer, a polycrystalline silicon layer, and a metal silicide layer. . 6. The method as claimed in claim 5, wherein the gate electrode structure further includes a silicon nitride layer. 7. The method according to claim 1, wherein the molar concentration of the hydrogen gas contained in the mixed gas is 5-50% of the mixed gas. Method. 8. The method according to claim 1, wherein the short-time annealing is performed at 700-950 ° C. 9. The implementation time of said short-time annealing is 0.5-4.
8. The method according to claim 7, wherein a bump is formed on the side wall of the metal silicide layer of the gate electrode. 10. The method of claim 1, wherein the short-time thermal oxidation is performed at 950-1200 ° C. 11. The method according to claim 10, wherein the time for performing the short-time thermal oxidation is 1 to 5 minutes. 12. The method according to claim 2, wherein the oxygen gas is cleared by feeding nitrogen gas into the chamber. 13. The method according to claim 2, wherein oxygen gas in the chamber is cleared by vacuum suction. 14. The method according to claim 12, wherein the oxygen gas is cleared so as to be 500 ppm or less. 15. The gate electrode according to claim 2, wherein said chamber is a chamber used for short-time annealing and short-time thermal oxidation processing and handles only a single wafer for each processing. To prevent bump formation on the side wall of the silicide metal layer. 16. The method according to claim 2, wherein said chamber is a chamber used for short-time annealing and short-time thermal oxidation processing, and capable of handling a set of a plurality of wafers in each processing. The method for preventing bump formation on the side wall of the metal silicide layer of the gate electrode according to the above. 17. The method as claimed in claim 2, further comprising, after the step (c), providing a second chamber (c1). Method. 18. The method according to claim 17, wherein the short-time thermal oxidation is performed in the second chamber. 19. A semiconductor device comprising: (a) providing a semiconductor substrate; (b) forming a gate oxide layer on the semiconductor substrate; and (c) forming a polycrystalline silicon layer on the gate oxide layer. (D) forming a metal silicide layer on the polycrystalline silicon layer; (e) patterning the metal silicide layer, the polycrystalline silicon layer and the gate oxide layer to form a gate electrode structure; f) performing a short-time annealing using a mixed gas containing nitrogen gas and hydrogen gas on the gate electrode structure; and (g) performing a short-time thermal oxidation on the gate electrode structure. Production method. 20. The method according to claim 19, wherein the step (c) includes (c1) adding a group 5A ion into the polycrystalline silicon layer by ion implantation. 21. The step (e) comprises: (e1) forming a mask layer on the metal silicide layer; and (e2) patterning the mask layer by photolithography and etching to define a gate electrode area. 20. The method of claim 19, further comprising: (e3) forming a gate electrode structure by dry etching. 22. The method according to claim 21, wherein the mask layer is a silicon nitride layer. 23. The method according to claim 19, wherein the molar concentration of the hydrogen gas contained in the mixed gas is 5-50% of the mixed gas. 24. The method according to claim 19, wherein the short-time annealing is performed at 700-950 ° C. 25. The short annealing time is 0.5 hours.
25. The method of claim 24, wherein the duration is -4 minutes.