JP2002228721A - Semiconductor tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor tester capable of obtaining the expected output waveform in the case of setting a clock open not to output the clock by using a proximity limit relaxing function of the clock. SOLUTION: This semiconductor tester is provided with a gate means for detecting a coincidence with a former logical pattern of the continuous patterns in the case of controlling the generation of clock with two logical patterns and continuously applying the same logical pattern in a continuously generating cycle with a waveform mode DNRZ. The semiconductor tester prohibits the following set pulses or the following reset pulses to relax the proximity limit of the clock, and the clock is not output in the open setting of the clock. A logic circuit for relaxing the proximity limit is provided to output a first set signal or a first reset signal after setting the clock open in the continuous generating cycle.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a waveform mode DNR.
The present invention relates to a semiconductor test apparatus capable of obtaining an expected output waveform even when an open setting for not outputting a clock is performed by using a clock proximity restriction relaxing function in Z.

[0002]

2. Description of the Related Art An example of the prior art will be described with reference to FIGS. First, the outline of the semiconductor test apparatus will be described with reference to the block diagram of FIG. The main parts of the semiconductor test apparatus include a pattern generator 5, a waveform shaper 6,
It comprises a logical comparator 7, a driver DR, and a comparator CP. However, the driver DR and the comparator C
There are many P's corresponding to each pin of the DUT 91 of the device under test, but one is shown for simplicity of the figure.

The pattern generator 5 synchronizes with a basic clock signal to generate a plurality of test patterns PATA / P of logical data.
Generate ATB, test period RATE, and expected value.

[0004] The waveform shaper 6 generates a test signal based on the RATE of the test cycle from the pattern generator 5 and the logic data pattern, and outputs the generated test signal to the driver DR.

The test signal output from the waveform shaper 6 is set to a predetermined logic voltage (VIH, VIL) by the driver DR and applied to the input pin of the DUT 91.

The output signal from the output pin of the DUT 91 is
After comparing the voltages with the comparison voltages (VOH, VOL) of the comparator CP, the voltage is output to the logical comparator 7 as a logical signal.

The logical comparator 7 logically compares a logical output signal of the comparator CP with an expected value from the pattern generator 5 to make a pass / fail judgment.

Next, the configuration and detailed operation of the waveform shaper 6 will be described with reference to FIG. As shown in FIG. 5, the waveform shaper 6 includes a control unit 10 and a delay setting memory 2.
1, 22; delay circuits 31, 32, 33, 34;
Flip-flop 11, AND gates 51, 52, 5
3 and 54, OR gates 61 and 62, and a proximity restriction alleviating unit 12. However, in this embodiment, the A clock (ACLK) is omitted because it is not used.

The control unit 10 performs clock setting and generation control according to a test cycle RATE.

The delay setting memories 21 and 22 are
Each clock data generated and output in the minimum test cycle RAT
It is output as data having a delay time that is an integral multiple of E. For example, when the minimum test period RATE = 8 ns, 8n
, 16 ns,... are output. Also,
The delay clock of the pattern set to open (OPEN) for each clock by the program is not output.

The delay circuits 31, 32, 33 and 34 are circuits for delaying and outputting signals with a delay time shorter than the test cycle.

The RS flip-flop 11 outputs a signal whose waveform is shaped by a set / reset signal of the clock BCLK and the clock CCLK that are ORed by the OR gates 61 and 62.

The proximity restriction alleviating section 12 is constituted by a logic circuit which inhibits the output of the proximity clock pulse and operates at high speed.

Next, the operation of the function of the proximity restriction relaxing unit 12 will be described with reference to FIG. As shown in FIG. 6, the proximity restriction alleviating unit 12 includes flip-flops 41, 43, 4
4 and the gate means 81 to 88 constitute a logic circuit.

The logic data "1" of the pattern PATA is fetched by the flip-flop 41 for each RATE, and the current cycle (this cycle: C-
(PATA) BCLK set signal (B-SET)
Is output via the gate means 81. In addition, “0” of the logical data of the pattern PATA is fetched for each RATE in the flip-flop 41 and becomes a reset signal (B-RST) of BCLK by the current cycle (this cycle: C-PATA) via the gate means 83. Is output.

Similarly, "1" of the logical data of the pattern PATB is fetched by the flip-flop 43 for each RATE and the current cycle (this cycle: C-
PATB) CCLK set signal (C-SET)
Is output through the gate means 85. In addition, “0” of the logical data of the pattern PATB is fetched for each RATE in the flip-flop 43 and becomes a reset signal (C-RST) of CCLK by the current cycle (this cycle: C-PATB) via the gate means 87. Is output.

The logic data “1” or “0” in the previous cycle of the pattern PATB is output from the flip-flop 4.
At 4, the data is captured by the RATE of the previous cycle and output as P-PATB of the previous cycle (Previaus).

The output of the flip-flop 41 is
When the output from the flip-flop 44 and the output from the flip-flop 44 are received by the gate means 82 and the outputs coincide with each other, the output from the flip-flop 41 is inhibited by the gate means 81. That is,
By the gate means 82 and 81, the pattern P of the previous cycle
When the logic of ATB is 1, the pattern PAT of the following main cycle
When A is logic 1, this cycle set (B-SET)
Disable output.

When the logic of the pattern PATB of the previous cycle is 0 and the pattern PATA of the subsequent cycle is logic 0, the reset (B-RST) output of this cycle is prohibited by the gate means 84 and 83.

Similarly, when the logic of the pattern PATA of this cycle is 1 and the pattern PATB of this cycle is logic 1 by the gate means 86 and 85, the set (C-SET) output of this cycle is prohibited.

When the logic of the pattern PATA of this cycle is 0 and the pattern PATB of this cycle is logic 0, the reset (C-RST) output of this cycle is inhibited by the gate means 88 and 87.

Next, the waveform mode of the test signal is set to DNRZ.
(Double Nonreturn to Zero). Here, the waveform mode DNRZ is a waveform that generates two NRZs (Nonreturn to Zero) in one cycle.
For example, during one cycle, patterns PATA and PATB are alternately output, and when the pattern PATA is logic 1, a set signal is output with the clock BCLK, and the pattern PATB is output.
Outputs a set signal with the clock CCLK when is a logic 1. In one cycle, patterns PATA and PATB
Are alternately output, and when the pattern PATA is logic 0, a reset signal is output with the clock BCLK, and the pattern PA
When TB is logic 0, a reset signal is output with the clock CCLK.

Basically, clock generation is performed by logical data pattern control. When different logical data patterns are applied in the same or consecutive cycles, a set clock is generated in all cycles. When the same logic pattern is applied in the cycle that occurs, the waveforms are not separated and the SR flip-flop 11 shown in FIG.

Therefore, when the same logical pattern is continuously applied in successively generated cycles, that is, the second or subsequent set pulse in the case of set, set,... Or reset, reset,. The output of the second and subsequent reset pulses at the time of (2) is prohibited to ease the proximity restriction.

Next, a specific example will be described with reference to the timing chart of FIG. RATE = 8 ns BCLK = 2 ns CCLK = 5 ns Then, the minimum pulse width of set-reset can be output in 3 ns, and in a continuous cycle, 2 is set by the proximity limit relaxation function in set-set or reset-reset.
The pulse output after the third pulse is prohibited.

For example, as shown in FIG. 7, if there is no proximity restriction relaxing function, the pattern PAT
A outputs a reset signal at a timing of 2 ns of BCLK when the logic is 0, and outputs a reset signal at a timing of 5 ns of the CCLK when the logic of the pattern PATB is 0. But,
Since the output of the second reset signal is inhibited in the cycle continuously generated by the proximity restriction relaxing function, the BCLK
The output of the reset signal at timing 2 ns is prohibited (X).

Similarly, the pattern PAT of cycle 1
The output of the third reset signal is also prohibited since the pattern PATA of the cycle 2 generated successively to B is logic 0, so that the output of the reset signal at the timing 2 ns of BCLK is prohibited (X). Then, since the pattern PATB of the next cycle 2 which is generated is logic 1 and the output of the first set signal is not inhibited, the set signal at the timing 5 ns of CCLK is output.

Similarly, the output of the second reset signal is inhibited (X) in the logic 1 of PATA in the next cycle 3.

Next, an operation of an open (OPEN) setting in which a predetermined clock is not output by a program will be described. For example, as shown in FIG. 7, when the B clock is set to be open (BCLK OPEN) in cycle 4, the set signal (B-S) of 2 ns of the B clock is set.
ET) is not output. Therefore, the same cycle 4 CC
5 ns of LK should be output as the first set signal. However, as shown in the output waveform of FIG. 7, the 5 ns of CCLK in the same cycle 4 is the first set signal, but the output is prohibited and is not output because the proximity restriction relaxing function is activated. The expected waveform due to the setting is not output.

[0030]

As described above,
The proximity limit relaxation function of the conventional semiconductor test apparatus has a practical problem that an expected waveform is not output when it is set to open. Therefore, the present invention has been made in view of such a problem, and an object of the present invention is to provide an expected original output even when an open setting in which a clock is not output is performed by using a clock proximity restriction relaxation function in a DNRZ waveform mode. An object of the present invention is to provide a semiconductor test device capable of obtaining a waveform.

[0031]

That is, a first aspect of the present invention, which has been made to achieve the above object, is to control clock generation by two logic patterns, and to generate continuously generated cycles in the waveform mode DNRZ. In the case where the same logic pattern is successively applied, a gate means for detecting coincidence with the previous logic pattern of the continuous pattern is provided, and the second or later set pulse or the second or later reset pulse is output. In a semiconductor test apparatus that prohibits and reduces the proximity restriction of the clock and does not output the clock when the clock is set to open, in a cycle that occurs continuously, the first set signal or the reset signal of the next set signal whose clock is set to open is continuously generated. A first aspect of the present invention is a semiconductor test apparatus characterized by providing a logic circuit for alleviating a proximity limit that can be output.

A second aspect of the present invention, which has been made to achieve the above object, is to control the clock generation by two logic patterns, and to have the same logic pattern in successively generated cycles in the waveform mode DNRZ. A gate means for detecting coincidence with a previous logical pattern of a continuous pattern when applied continuously, providing a second or subsequent set pulse;
Alternatively, in a semiconductor test apparatus which prohibits a reset pulse after the second and relaxes the proximity restriction of the clock and does not output the clock when the clock is set to be open, the second logic pattern of the previous cycle and the first logic pattern of the following main cycle Is set to logic 1 and the clock of the previous cycle is set to be open, prohibition of set output of the present cycle is prohibited, and the second logical pattern of the previous cycle and the first When the logic pattern is logic 0 and the clock of the previous cycle is set to open,
Prohibition of reset output of this cycle is prohibited, and the first logic pattern of this cycle and the second logic pattern of this cycle are logic 1, and the clock of the first logic pattern of this cycle is set to open. The prohibition of set output in this cycle is prohibited, the first logic pattern in this cycle and the second logic pattern in this cycle are logic 0, and the clock of the first logic pattern in this cycle is A gist of the present invention is a semiconductor test apparatus characterized in that a logic circuit for relaxing proximity restriction is provided to prohibit prohibition of reset output in this cycle when the setting is open.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. The outline of the semiconductor test apparatus has been described in the related art, and thus the description is omitted.

Next, the configuration and operation of the waveform shaper 6 of the semiconductor test apparatus of the present invention will be described with reference to FIG.
As shown in FIG. 2, the waveform shaper 6 includes a control unit 10, delay setting memories 21 and 22, delay circuits 31, 32, 3
3, 34, the RS flip-flop 11, AND gates 51, 52, 53, 54, and OR gates 61, 62
And the proximity restriction alleviating unit 13. That is, the present embodiment is different from the related art in that the block of the proximity restriction relaxing unit 13 is different from the conventional one, and that the delay setting memories 21 and 22 supply an open setting signal to the proximity restriction relaxing unit 13.

Next, the operation of the logic circuit of the proximity restriction relaxing unit 13 will be described with reference to FIG. As shown in FIG. 1, the proximity restriction alleviating unit 13 includes a flip-flop 41,
43, 44, 45, 46, 47 and gate means 81 to 8
8 and the inverters 71 and 72 constitute a logic circuit. However, the numbers of the respective gate means 81 to 88 are given the same numbers in correspondence with FIG. 6 of the prior art. Also,
In the present embodiment, the A clock (ACLK) is not used as in the related art, and thus is omitted.

Then, the logic data "1" of the pattern PATA is fetched by the flip-flop 41 for each RATE, and the current cycle (this cycle: C-
(PATA) BCLK set signal (B-SET)
Is output via the gate means 81. In addition, “0” of the logical data of the pattern PATA is fetched for each RATE in the flip-flop 41 and becomes a reset signal (B-RST) of BCLK by the current cycle (this cycle: C-PATA) via the gate unit 83. Is output.

Similarly, "1" of the logical data of the pattern PATB is fetched by the flip-flop 43 for each RATE and the current cycle (this cycle: C-
PATB) CCLK set signal (C-SET)
Is output through the gate means 85. In addition, “0” of the logical data of the pattern PATB is fetched for each RATE in the flip-flop 43 and is provided as a CCLK reset signal (C-RST) by the current cycle (this cycle: C-PATB) via the gate means 87. Is output.

Then, the logic data "1" or "0" of the previous cycle of the pattern PATB is fetched by the flip-flop 44 by the RATE of the previous cycle (Previaus) and output as the P-PATB of the previous cycle.

In addition, B clock open (BCLK O
PEN) as the data of the flip-flop 45, and outputs an output fetched by RATE as gate means 88.
To the gate means 87 via the
1 and the gate means 8
5 given.

Further, B clock open (BCLK
OPEN) signal as flip-flop 46 data, an output fetched by RATE is given to the data of flip-flop 47, and an output fetched by the immediately preceding RATE is given to the gate means 83 via the gate means 84. The signal is inverted by an inverter 72 and given to the gate means 81 via a gate means 82.

Then, the output of the flip-flop 41 is
The output from the flip-flop 44 and the flip-flop 4
7 and the output inverted by the inverter 72 of
The output of the flip-flop 41 is inhibited by the gate means 81. That is, the gate means 82,
81, the logic of the pattern PATB in the previous cycle becomes 1
When the pattern PATA of the subsequent cycle is logic 1 and CCLK of the previous cycle is set to OPEN, prohibition of the set (B-SET) output of this cycle is prohibited.

Further, the gate means 84 and 83 determine that the logic of the pattern PATB in the previous cycle is 0, the pattern PATA in the next cycle is logic 0, and
When CLK is set to OPEN, prohibition of reset (B-RST) output in this cycle is prohibited.

When the logic of the pattern PATA of this cycle is 1 and the pattern PATB following this cycle is logic 1 and the BCLK of this cycle is set to OPEN by the gate means 86 and 85, Prohibition of set (C-SET) output is prohibited.

The logic of the pattern PATA in this cycle is 0, the pattern PATB following this cycle is logic 0, and
When CLK is set to OPEN, prohibition of reset (C-RST) output in this cycle is prohibited.

The waveform mode of the test signal for mitigating the proximity restriction is set to DNRZ (Double Nonreturn to Zero).

Next, with reference to the timing chart of FIG. 3, a description will be given as a specific example of the same setting as the conventional one. However, the operation is the same as the conventional operation except for the cycle of the open setting in which the clock is not output.

For example, as shown in FIG. 3, in cycle 4, the B clock is opened (BCLK OPEN).
When set, the set signal (B-
SET) is not output. In this case, the logic of the pattern PATA in cycle 4 is 1 and the pattern PA in cycle 4 is
TB is logic 1 and BCLK in cycle 4 is OPEN
Since it is set, the set of this cycle 4 (C-SE
T) Output is performed because prohibition of output is not prohibited.

Therefore, even when the clock proximity restriction alleviating function in the waveform mode DNRZ is working, as shown in the output waveform of FIG. 3, 5 ns of CCLK in the same cycle 4 in which the clock BCLK is set to be open is 1 set signal. Second, output can be performed without prohibiting output. In other cases, even when the proximity limit alleviating function operates, in a cycle that occurs continuously, the clock can be output as the first set signal or the first reset signal after the clock is set to be open.

[0049]

The present invention is embodied in the form described above, and has the following effects. That is,
According to the present invention, even if the proximity limit relaxation function in the waveform mode DNRZ is working,
Since it can be output as the first of the next set signal or the first of the reset signal after the clock is set to open, even if the open setting of not outputting the clock is performed by using the clock proximity restriction relaxation function, the expected original signal can be output. There is an effect that an output waveform can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a proximity restriction relaxation unit of a semiconductor test apparatus according to the present invention.

FIG. 2 is a block diagram of a waveform shaper of the semiconductor test device of the present invention.

FIG. 3 is a timing chart of the semiconductor test apparatus of the present invention.

FIG. 4 is a block diagram of a semiconductor test apparatus.

FIG. 5 is a block diagram of a waveform shaper of a conventional semiconductor test device.

FIG. 6 is a circuit diagram of a proximity restriction relaxation unit of a conventional semiconductor test device.

FIG. 7 is a timing chart of a conventional semiconductor test apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Control part 11 RS flip-flop 12, 13 Proximity restriction relaxation part 21, 22 Delay setting memory 31, 32, 33, 34 Delay circuit 41-47 Flip-flop 71, 72 Inverter 81-88 Gate means 91 DUT

Claims (2)

[Claims] 1. When the clock generation is controlled by two logic patterns and the same logic pattern is continuously applied in a continuously generated cycle in the waveform mode DNRZ,
A gate means for detecting coincidence of a continuous pattern with a previous logical pattern is provided, a second or later set pulse or a second or later reset pulse is inhibited to relax clock proximity restriction, and open the clock. In a semiconductor test apparatus that does not output a clock by setting, a logic circuit for alleviating the proximity limit that can be output as the first set signal or the first reset signal of the next set signal whose clock is set to open in a continuously occurring cycle is provided. A semiconductor test apparatus characterized by the following. 2. When the clock generation is controlled by two logic patterns, and in the waveform mode DNRZ, a pattern of the same logic is continuously applied in successively generated cycles,
A gate means for detecting coincidence of a continuous pattern with a previous logical pattern is provided, a second or later set pulse or a second or later reset pulse is inhibited to relax clock proximity restriction, and open the clock. In a semiconductor test apparatus that does not output a clock by setting, when the second logic pattern of the previous cycle and the first logic pattern of the following cycle are logic 1 and the clock of the previous cycle is set to open, The prohibition of set output of a cycle is prohibited, and when the second logical pattern of the previous cycle and the first logical pattern of the subsequent cycle are logic 0 and the clock of the previous cycle is set to be open, Of the reset output of the first cycle of the cycle and the second logic of the cycle
When the logic pattern of this cycle is logic 1 and the clock of the first logic pattern of this cycle is set to open, prohibition of set output of this cycle is prohibited, and the first logic pattern of this cycle and this cycle Is the logic 0 and the clock of the first logic pattern of this cycle is set to open,
A semiconductor test apparatus comprising a logic circuit for alleviating proximity restriction for prohibiting the inhibition of reset output in the cycle.