JP3455303B2 - Test pattern waveform shaping circuit for semiconductor test equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a semiconductor test apparatus, and uses an XOR (exclusive OOR) as a waveform mode for applying an address or data during a device test.
R) The waveform shaping circuit when the waveform mode is set. 2. Description of the Related Art FIG.
1 shows a waveform shaping circuit having a pin multiplexing function of logically ORing the waveforms of two pins 1 and CH2 and outputting the result to pin 1, and when the XOR waveform mode is set. This circuit is
ACLK, BCLK, CCLK and PA
By the T (pattern) signal, the SR flip-flop 33
And a waveform shaping unit 11 that outputs a SET signal and a RESET signal, and controls the RS flip-flop 33 with a SET signal and a RESET signal for each pin,
A pin multiplex 21 for controlling a 1-pin RS flip-flop 33 with an ET signal and a RESET signal; a trailing edge differential pulser 31 for a SET signal for shortening a trailing edge of a pulse output from the pin multiplex 21;
It comprises a trailing edge differential pulser 32 for the ET signal and an RS flip-flop 33 for outputting an XOR waveform. FIG. 4 is a circuit diagram of the above circuit.
This shows how a waveform is generated from three clocks, CLK and CCLK, and PAT, where PAT changes from “0” to “1”.
→ This is the case where it changes to “1”. In this case,
Since the tester cycle time is sufficiently long, the XOR waveform is output without any problem. FIG. 5 shows the same P as in FIG.
FIG. 9 is a timing chart when a tester cycle is shortened in an AT change. In this case, when the same PAT continues, two set pulses or reset pulses approach in adjacent tester cycles. For example, the PAT in FIG.
When “1” continues, when the previous PAT is “1”, C
RESET pulse P1 obtained from CLK, and PA
At T “1”, the RESET pulse P2 obtained from ACLK approaches and these RESET pulses P1, P2
However, the pulse P continues as shown in FIG.
Where the SR flip-flop is to be reset at the timing T1 of the trailing edge of 1, the SR flip-flop is reset at the timing T2 of the trailing edge of the pulse P2, and the XOR waveform is as shown by the dotted line of OUT1 in FIG. The desired place is indicated by a solid line, and a desired XOR waveform cannot be obtained. FIG. 7 is a timing chart when the tester cycle is shortened in the pin multiplex mode. CH1 for the first half and CH for the second half of the tester cycle
2, PAT1 is “0” → “1” → “0”, and PAT2 is “1” → “1” →
It becomes “0”. When viewed as a test cycle, the PAT continues from “0” → “1” → “1” → “1” → “0” → “0”. In the next test cycle, two set pulses or reset pulses approach each other, and in FIG.
“A” and “U” are continuous with the previous pulse, and the SR flip-flop should be set or reset at the trailing edge of the previous pulse. The XOR waveform is shown as OUT1 in FIG.
A portion that should be indicated by a dotted line is indicated by a solid line, and a desired XOR waveform cannot be obtained. The present invention relates to a waveform shaping circuit having a pin multiplex function of a semiconductor test apparatus. When an XOR waveform mode is designated, when a test cycle time is short and the same pattern is continuous, a set signal inputted to an SR flip-flop is provided. And a circuit that can normally generate a reset signal. In order to achieve the above object, the present invention adds the following circuit to a conventional circuit. That is, PAT1 is included in the waveform shaping unit of CH1.
A flip-flop FF11 that receives a signal and an MCLK signal as input and generates a pattern signal of a cycle of interest is provided. Further, there is provided a flip-flop FF12 which receives the output signal of the flip-flop FF11 and the MCLK signal and generates a pattern signal of the immediately preceding cycle. A multiplexer SEL1 is provided, which receives as input the output signal of the flip-flop FF12 and the output signal of the flip-flop FF22 that generates a pattern signal of the cycle immediately before CH2, and selects an output signal with a PINMUX signal. The above flip-flop F
A gate for performing an exclusive OR operation by using the output signal of F11 and the output signal of the multiplexer SEL1 as inputs,
A gate is provided for inhibiting the output of the ACLK1 signal when the output of the gate is logic "0". The PAT is included in the waveform shaping section of CH2.
A flip-flop FF21 that receives two signals and the MCLK signal and generates a pattern signal of a cycle of interest is provided. Further, a flip-flop FF22 is provided which receives the output signal of the flip-flop FF21 and the MCLK signal and generates a pattern signal of the immediately preceding cycle. A multiplexer SEL2 is provided which receives the output signal of the flip-flop FF22 and the output signal of the flip-flop FF11 for generating the pattern signal of the target cycle of CH1 as input, and selects an output signal by a PINMUX signal. The above flip-flop FF
A gate for exclusive-ORing the output signal of the multiplexer 21 and the output signal of the multiplexer SEL2 is provided, and a gate for inhibiting the output of the ACLK2 signal when the output of the gate is logic "0" is provided. In the waveform shaping circuit configured as described above, when PIN multiplex is not specified, PINMU
X becomes logic "0", and each channel performs an exclusive OR operation on the pattern signal of the cycle of interest and the pattern signal of the immediately preceding cycle. When the output is logic "0", ACLK1 and ACLK2 are output, respectively. Ban. That is, for each channel, ACLK1 and ACLK2 are prohibited when the same pattern continues. When pin multiplex is specified, PI
NMUX becomes logic "1". In CH2, the pattern signal of its own cycle of interest and the pattern signal of the cycle of interest of CH1 are exclusive-ORed, and the pattern signal of the cycle of interest of CH2 and the pattern signal of the cycle of interest of CH1 are the same. At this time, ACLK2 is prohibited. In CH1, the pattern signal of its own cycle of interest and the pattern signal of the cycle immediately before CH2 are exclusively ORed, and the pattern signal of the cycle of interest of CH1 and the pattern signal of the cycle immediately before CH2 are the same. At this time, ACLK1 is prohibited. That is,
When the pattern signal of the target cycle of CH1 and the pattern signal of the target cycle of CH2 are the same, ACLK2 is prohibited,
When the pattern signal of the target cycle of CH1 is the same as the pattern signal of the previous cycle of CH2, ACLK1 is prohibited. FIG. 1 shows an example of a circuit configuration of a waveform shaping circuit for inhibiting unnecessary pulses according to the present invention. In this circuit, ACLK
1, BCLK1, CCLK1, ACLK2, BCLK2
, And CCLK2 are clocks that determine each timing edge, PAT1 and PAT2 are XOR waveform patterns, M
CLK is a reference clock. FF11 and FF in FIG.
Reference numeral 21 denotes a flip-flop for retiming PAT1 and PAT2, the outputs of which are CH1 and CH2, respectively.
The pattern of the attention cycle of FIG. FF12 and FF2
2 retiming the output of FF11 and FF12, the output is the pattern one tester cycle before CH1 and CH2, respectively. When the pin multiplex is not specified, PINMUX becomes logic “0”, and each channel has a pattern signal of 1
The pattern signal of the previous cycle is Exclusive.
OR (EOR) signals, ACLK1 and ACLK, respectively
CLK2 is prohibited. For this reason, when the same pattern is continuous, each channel has ACLK1 and ACL
K2 is prohibited. When pin multiplex is specified, PI
NMUX becomes logic "1". In CH2, the pattern signal of its own cycle of interest and the pattern signal of the cycle of interest of CH1 are EORed.
ACLK2 is prohibited. In CH1, the pattern signal of its own cycle of interest and the pattern signal of the cycle immediately before CH2 are EORed. When the pattern signal of the cycle of interest of CH1 and the pattern signal of the cycle immediately before CH2 are the same, ACLK1 Ban. As a result, the signals corresponding to the timings "A", "A", and "U" shown in the timing chart of FIG. 2 are inhibited, and the SET signal input to the SR flip-flop through the trailing edge differential pulser; Unnecessary signals are not generated in the RESET signal. Since the present invention is configured as described above, it has the following effects. That is, when the pin multiplex is not specified, each channel is set to ACLK when the same pattern continues.
1 and ACLK2 are inhibited. Also, when the pin multiplex is specified, when the pattern signal of the target cycle of CH1 and the pattern signal of the target cycle of CH2 are the same,
ACLK2 is inhibited, and when the pattern signal of the target cycle of CH1 and the pattern signal of the cycle immediately before CH2 are the same, ACLK1 is inhibited. As a result, CCL
At the timing when K and ACLK continue, ACLK
, And unnecessary signals are not generated in the SET signal and the RESET signal input to the SR flip-flop through the trailing edge differential pulser. For this reason, a waveform shaping circuit that can normally generate the set signal and the reset signal input to the SR flip-flop even when the test cycle time is shortened is realized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a waveform shaping circuit according to the present invention. FIG. 2 is an example of a timing chart of the present invention. FIG. 3 is a block diagram of a conventional waveform shaping circuit. FIG. 4 is a timing chart when a conventional tester cycle is long. FIG. 5 is a timing chart in the case where a conventional tester cycle is short. FIG. 6 is a waveform diagram showing a state where two pulses approach each other. FIG. 7 is a timing chart when the tester cycle is short in the conventional pin multiplex mode. [Description of Signs] 1 FF11 2 FF12 3 SEL1 4, 5, 9, 10 Gate 6 FF21 7 FF22 8 SEL2 11, 111, 112 Waveform shaping section 21 Pin multiplex 31, 32 Trailing edge differential pulser 33 RS flip-flop

Claims (1)

(1) A waveform shaping circuit having a pin multiplexing function of performing a logical OR operation on two pin waveforms of CH1 and CH2 in one tester cycle and outputting the result to one pin. A flip-flop FF11 (1) is provided in the waveform shaping section (111) to generate a pattern signal of a cycle of interest by inputting the PAT1 signal and the MCLK signal, and the output signal of the flip-flop FF11 (1) and M
A flip-flop FF12 (2) for generating a pattern signal of the immediately preceding cycle with the input of the CLK signal is provided, and the output signal of the flip-flop FF12 (2) and C
The output signal of the flip-flop FF22 (7) that generates the pattern signal of the cycle immediately before H2 is input,
A multiplexer SEL1 (3) for selecting an output signal by a PINMUX signal is provided, and a gate (4) that performs an exclusive OR operation using the output signal of the flip-flop FF11 (1) and the output signal of the multiplexer SEL1 (3) as inputs is provided. When the output of the gate (4) is logic "0", ACLK1
A gate (5) for inhibiting the output of a signal is provided, and a flip-flop FF21 (6) for generating a pattern signal of a cycle of interest using a PAT2 signal and an MCLK signal as input is provided in a waveform shaping unit (112) of CH2. The output signal of the flip-flop FF21 (6) and M
A flip-flop FF22 (7) for generating a pattern signal of the immediately preceding cycle by using the CLK signal as an input; an output signal of the flip-flop FF22 (7) and C
The output signal of the flip-flop FF11 (1) that generates the pattern signal of the target cycle of H1 is input to PI
Multiplexer SE for selecting output signal with NMUX signal
L2 (8), a gate (9) for exclusive-ORing the output signal of the flip-flop FF21 (6) and the output signal of the multiplexer SEL2 (8) as inputs, and an output of the gate (9) Is at logic "0", ACLK2
A test pattern waveform shaping circuit for a semiconductor test apparatus, comprising: a gate (10) for inhibiting signal output.