JP2002223074A - Wiring board with pin and electronic device using the same - Google Patents

Wiring board with pin and electronic device using the same

Info

Publication number
JP2002223074A
JP2002223074A JP2001019609A JP2001019609A JP2002223074A JP 2002223074 A JP2002223074 A JP 2002223074A JP 2001019609 A JP2001019609 A JP 2001019609A JP 2001019609 A JP2001019609 A JP 2001019609A JP 2002223074 A JP2002223074 A JP 2002223074A
Authority
JP
Japan
Prior art keywords
diameter portion
pad
pins
electronic device
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001019609A
Other languages
Japanese (ja)
Inventor
Kenji Nakamura
憲志 中村
Masaaki Harazono
正昭 原園
Koji Nishi
浩二 西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001019609A priority Critical patent/JP2002223074A/en
Publication of JP2002223074A publication Critical patent/JP2002223074A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board having pins with which electronic components mounted thereon can be correctly connected to external electric circuits without allowing lead pins from coming off easily, and an electronic device. SOLUTION: The board is constructed in such a manner that pin attaching pads 2b electrically connected to a wiring conductor 2 are provided on the lower surface of an organic material-based insulating board 1 having the conductor 2 and lead pins 3 each having an approximately disk-like large diameter part 3a on the upper edge part are erected on the pads 2b so that a solder 9 intervenes between the upper edge surface and the side of the each part 3a and the each pad 2b. Formulas 0.05 mm<=T<=0.3 mm and 0.25<=D/T<=1.5 are satisfied where the thickness of the part 3a is T and the distance between the external circumference of the pad 2b and the part 3a is D.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子等の電
子部品を搭載するために用いられるピン付き配線基板お
よびこのピン付き配線基板上に半導体素子等の電子部品
を搭載して成る電子装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board with pins used for mounting electronic components such as semiconductor elements, and an electronic device having electronic components such as semiconductor elements mounted on the wiring board with pins. Things.

【0002】[0002]

【従来の技術】近時、半導体素子等の電子部品を搭載す
るために用いられるピン付き配線基板として、例えばガ
ラス−エポキシ板等から成る絶縁板やエポキシ樹脂等か
ら成る絶縁層を複数層積層して成る絶縁基板の上面から
下面にかけて銅箔から成る複数の配線導体を設けるとと
もにこれらの配線導体の絶縁基板下面に導出した部位に
複数のピン付けパッドを形成し、これらのピン付けパッ
ドに上端部に円板状の径大部を有する略円柱状のリード
ピンをその上端を突き当てて半田付けすることにより立
設して成る有機材料系のピン付き配線基板が採用される
ようになってきている。このような有機材料系のピン付
き配線基板は、セラミック材料系のピン付き配線基板と
比較して軽量であり、かつ配線導体の電気抵抗が小さい
という有利な面を有している。そして、このような有機
材料系のピン付き配線基板においては絶縁基板の上面に
電子部品を搭載するとともに電子部品の電極と配線導体
とを半田バンプやボンディングワイヤ等を介して電気的
に接続した後、電子部品を金属やセラミックから成る蓋
体やポッティング樹脂等から成る封止部材により封止す
ることによって製品としての電子装置となり、この電子
装置においては、絶縁基板下面のリードピンを外部電気
回路基板の配線導体にソケットや半田等を介して接続す
ることにより外部電気回路基板上に実装されるとともに
搭載する電子部品が外部電気回路に電気的に接続される
こととなる。
2. Description of the Related Art Recently, as a wiring board with pins used for mounting electronic parts such as semiconductor elements, for example, an insulating plate made of a glass-epoxy plate or a plurality of insulating layers made of an epoxy resin are laminated. A plurality of wiring conductors made of copper foil are provided from the upper surface to the lower surface of the insulating substrate, and a plurality of pinning pads are formed at portions of these wiring conductors led out to the lower surface of the insulating substrate. An organic material-based pinned wiring board, which is formed by erecting a substantially cylindrical lead pin having a disc-shaped large-diameter portion by abutting the upper end thereof and soldering the pin, has been adopted. . Such an organic material-based wiring board with pins is advantageous in that it is lighter in weight and has a smaller electric resistance of a wiring conductor than a wiring board with pins made of a ceramic material. In such an organic material-based wiring board with pins, the electronic component is mounted on the upper surface of the insulating substrate, and the electrodes of the electronic component and the wiring conductor are electrically connected via solder bumps, bonding wires, and the like. By sealing the electronic components with a lid made of metal or ceramic or a sealing member made of potting resin or the like, an electronic device as a product is obtained. In this electronic device, the lead pins on the lower surface of the insulating substrate are connected to the external electric circuit board. By being connected to the wiring conductor via a socket, solder, or the like, the electronic component mounted on the external electric circuit board is electrically connected to the external electric circuit.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、この有
機材料系のピン付き配線基板およびこれを用いた電子装
置によると、半田とピンおよびピン付けパッドとの接合
力やガラス−エポキシ板やエポキシ樹脂等から成る絶縁
基板とピン付けパッドとの密着力が小さいことから、リ
ードピンを例えば30N程度の力で垂直あるいは斜め方向
に引っ張ると、その力により半田とリードピンやピン付
けパッドとの間で、あるいはピン付けパッドと絶縁基板
との間で剥離が発生してリードピンが絶縁基板から取れ
てしまうことがあり、そのようにリードピンが絶縁基板
から取れてしまうと搭載する電子部品を外部電気回路に
正常に接続することができなくなってしまうという問題
点を有していた。
However, according to the organic material-based wiring board with pins and the electronic device using the same, the bonding strength between solder and pins and pinning pads, glass-epoxy plate, epoxy resin, etc. When the lead pin is pulled vertically or obliquely with a force of, for example, about 30 N, the force between the solder and the lead pin or the pinning pad or the pin Separation may occur between the mounting pad and the insulating substrate, and the lead pins may be removed from the insulating substrate. If the lead pins are removed from the insulating substrate, the electronic components to be mounted are normally connected to the external electric circuit. There was a problem that it became impossible to do.

【0004】本発明は、かかる問題点に鑑み案出された
ものであり、その目的は、50N程度の力でリードピンを
引っ張ったとしてもリードピンが取れることがなく、搭
載する電子部品を外部電気回路に正常に接続することが
できる信頼性の高いピン付き配線基板および電子装置を
提供することにある。
The present invention has been devised in view of the above problems, and has as its object to remove the lead pin even if the lead pin is pulled with a force of about 50 N, and to mount the mounted electronic component on an external electric circuit. It is an object of the present invention to provide a highly reliable wiring board with pins and an electronic device that can be normally connected to the electronic device.

【0005】[0005]

【課題を解決するための手段】本発明のピン付き配線基
板は、配線導体を有する有機材料系の絶縁基板の下面に
配線導体と電気的に接続されたピン付けパッドを設ける
とともにこのピン付けパッドに上端部に略円板状の径大
部を有するリードピンをその径大部の上端面および側面
とピン付けパッドとの間に半田を介在させて立設して成
るピン付き配線基板であって、径大部の厚みをT、ピン
付けパッドの外周縁から径大部までの距離をDとしたと
きに、0.05mm≦T≦0.3mmであり、かつ0.25≦D/
T≦1.5であることを特徴とするものである。
According to the present invention, there is provided a wiring board with pins provided with a pinning pad electrically connected to the wiring conductor on a lower surface of an organic material-based insulating substrate having a wiring conductor. A lead pin having a substantially disk-shaped large-diameter portion at an upper end portion thereof, and having a pin interposed between the upper end surface and the side surface of the large-diameter portion and the pinning pad. When the thickness of the large diameter portion is T and the distance from the outer peripheral edge of the pinning pad to the large diameter portion is D, 0.05 mm ≦ T ≦ 0.3 mm and 0.25 ≦ D /
T ≦ 1.5.

【0006】また、本発明の電子装置は、配線導体を有
する有機材料系の絶縁基板の下面に配線導体と電気的に
接続されたピン付けパッドを設けるとともにこのピン付
けパッドに上端部に略円板状の径大部を有するリードピ
ンをその径大部の上端面および側面とピン付けパッドと
の間に半田を介在させて立設して成るピン付き配線基板
に電子部品を搭載するとともにこの電子部品の電極と配
線導体とを電気的に接続して成る電子装置であって、径
大部の厚みをT、ピン付けパッドの外周縁から径大部ま
での距離をDとしたときに、0.05mm≦T≦0.3mmで
あり、かつ0.25≦D/T≦1.5であることを特徴とする
ものである。
In the electronic device of the present invention, a pinning pad electrically connected to the wiring conductor is provided on a lower surface of an organic material-based insulating substrate having a wiring conductor, and the pinning pad has a substantially circular upper end. The electronic component is mounted on a wiring board with pins formed by erecting a plate-like lead pin having a large-diameter portion with solder interposed between the upper end surface and the side surface of the large-diameter portion and the pinning pad. An electronic device comprising an electrode of a component and a wiring conductor electrically connected, wherein T is the thickness of the large-diameter portion, and D is the distance from the outer peripheral edge of the pinning pad to the large-diameter portion. mm ≦ T ≦ 0.3 mm and 0.25 ≦ D / T ≦ 1.5.

【0007】本発明のピン付き配線基板およびこれを用
いた電子装置によれば、径大部の厚みをT、ピン付けパ
ッドの外周縁から径大部までの距離をDとしたときに、
0.05mm≦T≦0.3mmとし、かつ0.25≦D/T≦1.5と
したことから、半田とリードピンの径大部およびピン付
けパッドとの接合を強固なものとすることができるとと
もにピン付けパッドに印加される応力を小さなものとす
ることができ、その結果、リードピンを絶縁基板に強固
に接合することができる。
According to the pinned wiring board of the present invention and the electronic device using the same, when the thickness of the large diameter portion is T and the distance from the outer peripheral edge of the pinning pad to the large diameter portion is D,
Since 0.05 mm ≤ T ≤ 0.3 mm and 0.25 ≤ D / T ≤ 1.5, it is possible to strengthen the bonding between the solder and the large diameter part of the lead pin and the pinning pad, and to make the pinning pad The applied stress can be reduced, and as a result, the lead pin can be firmly joined to the insulating substrate.

【0008】[0008]

【発明の実施の形態】つぎに、本発明を添付の図面に基
づき詳細に説明する。図1は、本発明を半導体素子を搭
載するためのピン付き配線基板およびこれに半導体素子
を搭載した電子装置に適用した場合の実施の形態の一例
を示す断面図であり、1は絶縁基板、2は配線導体、3
はリードピンである。この絶縁基板1と配線導体2とリ
ードピン3とで本発明のピン付き配線基板が構成され、
これに電子部品としての半導体素子4を搭載することに
より本発明の電子装置が形成される。
Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing an example of an embodiment in which the present invention is applied to a wiring board with pins for mounting a semiconductor element and an electronic device having the semiconductor element mounted thereon, where 1 is an insulating substrate, 2 is a wiring conductor, 3
Is a lead pin. The insulating substrate 1, the wiring conductor 2, and the lead pins 3 constitute a wiring board with pins of the present invention,
The electronic device of the present invention is formed by mounting the semiconductor element 4 as an electronic component on this.

【0009】絶縁基板1は、例えばガラス繊維を縦横に
織り込んだガラス織物にエポキシ樹脂やビスマレイミド
トリアジン樹脂等の熱硬化性樹脂を含浸させて成る板状
の芯体1aの上下面にエポキシ樹脂やビスマレイミドト
リアジン樹脂等の熱硬化性樹脂から成る絶縁層1bをそ
れぞれ複数層ずつ積層して成る有機材料系の多層板であ
り、その上面から下面にかけては銅箔や銅めっき膜等か
ら成る複数の配線導体2が形成されている。
The insulating substrate 1 is made of a glass fabric in which glass fibers are woven vertically and horizontally and impregnated with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. An organic material-based multilayer board formed by laminating a plurality of insulating layers 1b each made of a thermosetting resin such as a bismaleimide triazine resin, and a plurality of layers made of a copper foil, a copper plating film, or the like from the upper surface to the lower surface. The wiring conductor 2 is formed.

【0010】絶縁基板1を構成する芯体1aは、厚みが
0.3〜1.5mm程度であり、その上面から下面にかけて直
径が0.1〜1.0mm程度の複数の貫通孔5を有している。
そして、その上下面および各貫通孔5の内壁には配線導
体2の一部が被着されており、上下面の配線導体2が貫
通孔5を介して電気的に接続されている。
The core 1a constituting the insulating substrate 1 has a thickness.
It has a plurality of through-holes 5 of about 0.3 to 1.5 mm and a diameter of about 0.1 to 1.0 mm from the upper surface to the lower surface.
A part of the wiring conductor 2 is attached to the upper and lower surfaces and the inner wall of each through-hole 5, and the wiring conductors 2 on the upper and lower surfaces are electrically connected through the through-hole 5.

【0011】このような芯体1aは、ガラス織物に未硬
化の熱硬化性樹脂を含浸させたシートを熱硬化させた
後、これに上面から下面にかけてドリル加工を施すこと
により製作される。なお、芯体1a上下面の配線導体2
は、芯体1a用のシートの上下全面に厚みが3〜50μm
程度の銅箔を貼着しておくとともにこの銅箔をシートの
硬化後にエッチング加工することにより所定のパターン
に形成される。また、貫通孔5内壁の配線導体2は、芯
体1aに貫通孔5を設けた後に、この貫通孔5内壁に無
電解めっき法および電解めっき法により厚みが3〜50μ
m程度の銅めっき膜を析出させることにより形成され
る。
The core 1a is manufactured by thermally curing a sheet of glass fabric impregnated with an uncured thermosetting resin and then drilling the sheet from the upper surface to the lower surface. The wiring conductors 2 on the upper and lower surfaces of the core 1a
Has a thickness of 3 to 50 μm on the entire upper and lower surfaces of the sheet for the core 1a.
A predetermined degree of copper foil is adhered, and the copper foil is formed into a predetermined pattern by etching after curing of the sheet. The wiring conductor 2 on the inner wall of the through-hole 5 has a thickness of 3 to 50 μm after the through-hole 5 is formed in the core 1a and the inner wall of the through-hole 5 is formed by electroless plating and electrolytic plating.
It is formed by depositing a copper plating film of about m.

【0012】さらに、芯体1aは、その貫通孔5の内部
にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱
硬化性樹脂から成る樹脂柱6が充填されている。樹脂柱
6は、貫通孔5を塞ぐことにより貫通孔5の直上および
直下に絶縁層1bを形成可能とするためのものであり、
未硬化のペースト状の熱硬化性樹脂を貫通孔5内にスク
リーン印刷法により充填し、これを熱硬化させた後、そ
の上下面を略平坦に研磨することにより形成される。そ
して、この樹脂柱6を含む芯体1aの上下面に絶縁層1
bが積層されている。
Further, the core 1a is filled with a resin column 6 made of a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin inside the through hole 5. The resin pillar 6 is for enabling the insulating layer 1b to be formed directly above and directly below the through hole 5 by closing the through hole 5.
An uncured paste-like thermosetting resin is filled into the through-holes 5 by a screen printing method, and after thermosetting, the upper and lower surfaces are polished to be substantially flat. The insulating layer 1 is formed on the upper and lower surfaces of the core body 1a including the resin column 6.
b is laminated.

【0013】芯体1aの上下面に積層された絶縁層1b
は、それぞれの厚みが20〜60μm程度であり、各層の上
面から下面にかけて直径が30〜100μm程度の複数の貫
通孔7を有している。これらの絶縁層1bは、配線導体
2を高密度に配線するための絶縁間隔を提供するための
ものである。そして、上層の配線導体2と下層の配線導
体2とを貫通孔7を介して電気的に接続することにより
高密度配線を立体的に形成可能としている。このような
絶縁層1bは、厚みが20〜60μm程度の未硬化の熱硬化
性樹脂のフィルムを芯体1a上下面に貼着し、これを熱
硬化させるとともにレーザー加工により貫通孔7を穿孔
し、さらにその上に同様にして次の絶縁層1bを順次積
み重ねることによって形成される。なお、各絶縁層1b
表面および貫通孔7内に被着された配線導体2は、各絶
縁層1bを形成する毎に各絶縁層1bの表面および貫通
孔7内に5〜50μm程度の厚みの銅めっき膜を公知のセ
ミアディティブ法やサブトラクティブ法等のパターン形
成法により所定のパターンに被着させることによって形
成される。
An insulating layer 1b laminated on the upper and lower surfaces of the core 1a
Has a plurality of through holes 7 each having a thickness of about 20 to 60 μm and a diameter of about 30 to 100 μm from the upper surface to the lower surface of each layer. These insulating layers 1b are for providing an insulating interval for wiring the wiring conductors 2 at high density. By electrically connecting the upper layer wiring conductor 2 and the lower layer wiring conductor 2 through the through-hole 7, high-density wiring can be formed three-dimensionally. Such an insulating layer 1b is formed by attaching a film of an uncured thermosetting resin having a thickness of about 20 to 60 μm to the upper and lower surfaces of the core 1a, thermally curing the same, and forming the through holes 7 by laser processing. The insulating layer 1b is formed by successively stacking the next insulating layers 1b in a similar manner. In addition, each insulating layer 1b
The wiring conductor 2 attached on the surface and in the through hole 7 is formed by forming a copper plating film having a thickness of about 5 to 50 μm on the surface of each insulating layer 1b and in the through hole 7 every time the insulating layer 1b is formed. It is formed by applying a predetermined pattern by a pattern forming method such as a semi-additive method or a subtractive method.

【0014】絶縁基板1の上面から下面にかけて形成さ
れた配線導体2は、半導体素子4の各電極を外部電気回
路基板に接続するための導電路として機能し、絶縁基板
1の上面に設けられた部位の一部が半導体素子4の各電
極に例えば鉛−錫共晶合金から成る半田バンプ8を介し
て接合される電子部品接続パッド2aを、絶縁基板1の
下面に露出した部位の一部が外部接続端子としてのリー
ドピン3を接合するためのピン付けパッド2bを形成し
ており、ピン付けパッド2bにはリードピン3が鉛−錫
−アンチモン合金等の半田9を介して立設されている。
このような電子部品接続パッド2aおよびピン付けパッ
ド2bは、図2に要部拡大平面図で示すように、配線導
体2に接続された略円形のパターンの外周部をソルダー
レジストと呼ばれる最外層の絶縁層1bにより15〜150
μm程度の幅で被覆してその外周縁を画定することによ
りその直径φが、電子部品接続パッド2aであれば略70
〜200μm程度に、ピン付けパッド2bであれば略0.5〜
2.5mm程度になるように形成されている。なお、この
ようなソルダーレジスト1bにより電子部品接続パッド
2a同士あるいはピン付けパッド2b同士の半田8や9
による電気的な短絡が有効に防止されるとともに電子部
品接続パッド2aおよびピン付けパッド2bの絶縁基板
1に対する接合強度が高いものとなっている。
The wiring conductor 2 formed from the upper surface to the lower surface of the insulating substrate 1 functions as a conductive path for connecting each electrode of the semiconductor element 4 to an external electric circuit board, and is provided on the upper surface of the insulating substrate 1. An electronic component connection pad 2a, a part of which is joined to each electrode of the semiconductor element 4 via a solder bump 8 made of, for example, a lead-tin eutectic alloy, is partially exposed at the lower surface of the insulating substrate 1. A pinning pad 2b for joining the lead pin 3 as an external connection terminal is formed, and the lead pin 3 is erected on the pinning pad 2b via a solder 9 such as a lead-tin-antimony alloy.
As shown in the enlarged plan view of the main part of FIG. 2, the electronic component connection pad 2a and the pinning pad 2b are formed by forming the outer peripheral portion of the substantially circular pattern connected to the wiring conductor 2 on the outermost layer called solder resist. 15 to 150 depending on the insulating layer 1b
By coating with a width of about μm and defining the outer peripheral edge, if the diameter φ is approximately 70% if the electronic component connection pad 2a is used.
About 200 μm, about 0.5-
It is formed to be about 2.5 mm. In addition, the solder 8 or 9 between the electronic component connection pads 2a or between the pinning pads 2b is formed by the solder resist 1b.
Electrical short circuit is effectively prevented, and the bonding strength of the electronic component connection pad 2a and the pinning pad 2b to the insulating substrate 1 is high.

【0015】また、ピン付けパッド2bに接合されたリ
ードピン3は搭載する電子部品4を外部電気回路に接続
するための外部接続端子として機能する。
The lead pins 3 joined to the pinning pads 2b function as external connection terminals for connecting the mounted electronic components 4 to an external electric circuit.

【0016】そして、この配線基板においては、電子部
品接続パッド2aに半導体素子4の各電極を半田バンプ
8を介して接合して半導体素子4を搭載するとともにこ
の半導体素子4を図示しない蓋体やポッティング樹脂に
より封止することによって電子装置となり、この電子装
置におけるリードピン3をソケットや半田を介して外部
電気回路基板の配線導体に接続することにより本発明の
電子装置が外部電気回路基板に実装されることとなる。
In this wiring board, the electrodes of the semiconductor element 4 are bonded to the electronic component connection pads 2a via the solder bumps 8, and the semiconductor element 4 is mounted. An electronic device is obtained by sealing with a potting resin, and the electronic device of the present invention is mounted on the external electric circuit board by connecting the lead pins 3 of the electronic device to the wiring conductors of the external electric circuit board via a socket or solder. The Rukoto.

【0017】なお、リードピン3は、図3に要部拡大断
面図で示すように、例えば鉄−ニッケル−コバルト合金
や鉄−ニッケル合金等の金属から成る直径が0.25〜0.5
mm程度で長さが1〜3.5mm程度の略円柱状であり、
その上端部に直径が0.4〜1.5mmで厚みTが0.05〜0.3
mm程度のネールヘッドと呼ばれる略円板状の径大部3
aを有している。そして、この径大部3aの上端面およ
び側面をピン付けパッド2bに鉛−錫−アンチモン合金
等の半田を介して接合することによりリードピン3がピ
ン付けパッド2bに立設されている。
The lead pin 3 has a diameter of 0.25 to 0.5 made of a metal such as an iron-nickel-cobalt alloy or an iron-nickel alloy, as shown in FIG.
It is approximately cylindrical with a length of about 1 to 3.5 mm in about mm,
The upper end has a diameter of 0.4 to 1.5 mm and a thickness T of 0.05 to 0.3.
A substantially disk-shaped large diameter part 3 called a nail head of about mm
a. The upper end surface and the side surface of the large-diameter portion 3a are joined to the pinning pad 2b via a solder such as a lead-tin-antimony alloy, so that the lead pin 3 stands upright on the pinning pad 2b.

【0018】このとき、本発明においては、径大部3a
の厚みTを0.05〜0.3mmとし、さらに径大部3aの厚
みTに対するピン付けパッド2bの外周縁から径大部3
a側面までの距離Dの比率、即ち、D/Tが0.25≦D/
T≦1.5となるように半田付けされている。そしてこの
ことが重要である。なお、ここでいうピン付けパッド2
bの外周縁とは、ピン付けパッド2b用のパターンの外
周部が絶縁層1bで覆われている場合であれば、絶縁層
1bの開口縁に対応する部位を指し、そのような絶縁層
1bで覆われていない場合であれば、ピン付けパッド2
b用のパターンそのものの外周縁を指す。このように、
径大部3aの厚みTを0.05〜0.3mmとするとともに、
径大部3aの厚みTに対するピン付けパッド2bの外周
縁から径大部3までの距離Dの比率D/Tが0.25≦D/
T≦1.5となるように半田付けすることにより、半田9
と径大部3a側面およびピン付けパッド2bとを広い面
積で強固に接合することができるとともにリードピン3
に引っ張りの力が印加されたときにその引っ張り応力が
ピン付けパッド2bと絶縁基体1との接合部に大きく印
加されることを有効に防止することができる。したがっ
て、本発明のピン付き配線基板およびこれを用いた電子
装置によると、リードピン3の絶縁基板1に対する接合
強度を例えば50N以上の大きなものとすることができ
る。
At this time, in the present invention, the large-diameter portion 3a
Of the large diameter portion 3a from the outer peripheral edge of the pinning pad 2b to the thickness T of the large diameter portion 3a.
a The ratio of the distance D to the side surface, that is, D / T is 0.25 ≦ D /
Soldered so that T ≦ 1.5. And this is important. The pinning pad 2 here
The outer peripheral edge of the insulating layer 1b refers to a portion corresponding to the opening edge of the insulating layer 1b if the outer peripheral portion of the pattern for the pinning pad 2b is covered with the insulating layer 1b. If not covered with pin 2
Refers to the outer peripheral edge of the pattern for b. in this way,
While the thickness T of the large diameter portion 3a is set to 0.05 to 0.3 mm,
The ratio D / T of the distance D from the outer peripheral edge of the pinning pad 2b to the large diameter portion 3 to the thickness T of the large diameter portion 3a is 0.25 ≦ D /
By soldering so that T ≦ 1.5, the solder 9
And the side surface of the large diameter portion 3a and the pinning pad 2b can be firmly joined in a wide area, and the lead pin 3
When a tensile force is applied to the substrate, it is possible to effectively prevent the tensile stress from being greatly applied to the joint between the pinning pad 2b and the insulating substrate 1. Therefore, according to the wiring board with pins of the present invention and the electronic device using the same, the bonding strength of the lead pins 3 to the insulating substrate 1 can be increased, for example, to 50 N or more.

【0019】なお、リードピン3の径大部3aの厚みT
が0.05mm未満であると、径大部3aの側面と半田9と
の接合面積が狭いものとなり、リードピン3と半田9と
を強固に接合することが困難となる傾向にあり、他方、
0.3mmを超えると、そのような厚い径大部3aをリー
ドピン3の上端部に効率良く形成することが困難とな
る。したがって、リードピン3の径大部3aの厚みTは
0.05〜0.3mmの範囲に特定される。
The thickness T of the large diameter portion 3a of the lead pin 3
Is less than 0.05 mm, the joint area between the side surface of the large-diameter portion 3a and the solder 9 becomes narrow, and it tends to be difficult to firmly join the lead pin 3 and the solder 9;
If it exceeds 0.3 mm, it is difficult to efficiently form such a thick large-diameter portion 3a on the upper end of the lead pin 3. Therefore, the thickness T of the large diameter portion 3a of the lead pin 3 is
It is specified in the range of 0.05 to 0.3 mm.

【0020】また、径大部3aの厚みTに対するピン付
けパッド2bの外周縁から径大部3aまでの距離Dの比
率D/Tが0.25未満では、ピン付けパッド2bと半田9
との接合面積が狭いものとなり、ピン付けパッド2bと
半田9とを強固に接合することが困難となるとともに、
リードピン3に引っ張りの力が印加されたときに、この
力によって発生する応力がピン付けパッド2bと絶縁基
板1との接合部に大きく作用してピン付けパッド2bが
絶縁基板1から剥離してしまいやすくなり、他方、D/
Tが1.5を超えると、ピン付けパッド2b上に多量の半
田が流れるため、径大部3aとピン付けパッド2bとの
間に適度な大きさの半田の溜まりを形成するために多量
の半田9が必要となり、そのような多量の半田9を使っ
てリードピン3とピン付けパッド2bとを半田付けする
と、半田9の一部が径大部3aを越えてリードピン3の
下端部まで流れてしまい、リードピン3をソケットや半
田を介して外部電気回路基板の配線導体に電気的に接続
する際にその接続が困難となる。したがって、径大部3
aの厚みTに対するピン付けパッド2bの外周縁から径
大部3aまでの距離Dの比率D/Tは0.25≦D/T≦1.
5の範囲に特定される。
If the ratio D / T of the distance D from the outer peripheral edge of the pinning pad 2b to the large diameter portion 3a to the thickness T of the large diameter portion 3a is less than 0.25, the pinning pad 2b and the solder 9
And it becomes difficult to firmly join the pinning pad 2b and the solder 9 with each other.
When a pulling force is applied to the lead pins 3, the stress generated by this force greatly acts on the joint between the pinning pad 2b and the insulating substrate 1, and the pinning pad 2b peels off from the insulating substrate 1. On the other hand, D /
When T exceeds 1.5, a large amount of solder flows on the pinning pad 2b. When the lead pin 3 and the pinning pad 2b are soldered using such a large amount of solder 9, a part of the solder 9 flows over the large diameter portion 3a to the lower end of the lead pin 3, When the lead pins 3 are electrically connected to the wiring conductor of the external electric circuit board via the socket or the solder, the connection becomes difficult. Therefore, the large diameter part 3
The ratio D / T of the distance D from the outer peripheral edge of the pinning pad 2b to the large-diameter portion 3a to the thickness T of a is 0.25 ≦ D / T ≦ 1.
Specified in the range of 5.

【0021】かくして、本発明のピン付き配線基板およ
びこれを用いた電子装置によれば、リードピン3を垂直
あるいは斜めに50N程度の力で引っ張ったとしてもリー
ドピン3が絶縁基板1から取れることがなく、搭載する
電子部品を正常に作動させることが可能なピン付き配線
基板および電子装置を提供することができる。
Thus, according to the wiring board with pins of the present invention and the electronic device using the same, even if the lead pins 3 are pulled vertically or diagonally with a force of about 50 N, the lead pins 3 are not removed from the insulating substrate 1. In addition, it is possible to provide a wiring board with pins and an electronic device that can normally operate electronic components to be mounted.

【0022】なお、本発明は、上述の実施の形態の一例
に限定されるものではなく、本発明の要旨を逸脱しない
範囲であれば種々の変更が可能であることはいうまでも
ない。
It should be noted that the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the present invention.

【0023】[0023]

【発明の効果】本発明のピン付き配線基板およびこれを
用いた電子装置によれば、径大部の厚みをT、ピン付け
パッドの外周縁から径大部までの距離をDとしたとき
に、0.05mm≦T≦0.3mmであり、かつ0.25≦D/T
≦1.5であることから、半田とリードピンの径大部およ
びピン付けパッドとの接合を強固なものとすることがで
きるとともにピン付けパッドに印加される応力を小さな
ものとすることができる。その結果、リードピンを絶縁
基板に強固に接合することができ、搭載する電子部品を
外部電気回路に正常に接続することができる。
According to the wiring board with pins of the present invention and the electronic device using the same, when the thickness of the large diameter portion is T and the distance from the outer peripheral edge of the pinning pad to the large diameter portion is D, , 0.05 mm ≦ T ≦ 0.3 mm, and 0.25 ≦ D / T
Since ≦ 1.5, the bonding between the solder and the large-diameter portion of the lead pin and the pinning pad can be strengthened, and the stress applied to the pinning pad can be reduced. As a result, the lead pins can be firmly joined to the insulating substrate, and the mounted electronic components can be normally connected to the external electric circuit.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のピン付き配線基板および電子装置の実
施形態例の断面図である。
FIG. 1 is a cross-sectional view of an embodiment of a wiring board with pins and an electronic device according to the present invention.

【図2】本発明のピン付き配線基板および電子装置の実
施形態例の要部拡大平面図である。
FIG. 2 is an enlarged plan view of a main part of an embodiment of a wiring board with pins and an electronic device according to the present invention.

【図3】本発明のピン付き配線基板および電子装置の実
施形態例の要部拡大断面図である。
FIG. 3 is an enlarged sectional view of a main part of an embodiment of a wiring board with pins and an electronic device according to the present invention.

【符号の説明】[Explanation of symbols]

1・・・・・絶縁基体 2・・・・・配線導体 2b・・・・ピン付けパッド 3・・・・・リードピン 3a・・・・径大部 4・・・・・電子部品としての半導体素子 9・・・・・半田 T・・・・・径大部3aの厚み D・・・・・ピン付けパッド2bの外周縁から径大部3
aまでの距離
1 ... insulating base 2 ... wiring conductor 2 b ... pinning pad 3 ... lead pin 3 a ... large diameter part 4 ... semiconductor as electronic parts Element 9: solder T: thickness of large-diameter portion 3a D: large-diameter portion 3 from the outer peripheral edge of pinning pad 2b
Distance to a

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H05K 1/18 B23K 101:40 // B23K 101:40 H01L 23/12 P Fターム(参考) 5E336 AA04 BB03 BB15 CC34 CC58 EE03 5E346 AA15 BB16 CC04 CC09 CC32 DD02 DD12 DD32 DD33 EE33 FF01 FF07 FF15 HH11 5F067 AB07 BB20 EA02 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H05K 1/18 B23K 101: 40 // B23K 101: 40 H01L 23/12 PF term (Reference) 5E336 AA04 BB03 BB15 CC34 CC58 EE03 5E346 AA15 BB16 CC04 CC09 CC32 DD02 DD12 DD32 DD33 EE33 FF01 FF07 FF15 HH11 5F067 AB07 BB20 EA02

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 配線導体を有する有機材料系の絶縁基板
の下面に前記配線導体と電気的に接続されたピン付けパ
ッドを設けるとともに該ピン付けパッドに上端部に略円
板状の径大部を有するリードピンを前記径大部の上端面
および側面と前記ピン付けパッドとの間に半田を介在さ
せて立設して成るピン付き配線基板であって、前記径大
部の厚みをT、前記ピン付けパッドの外周縁から前記径
大部までの距離をDとしたときに、0.05mm≦T≦
0.3mmであり、かつ0.25≦D/T≦1.5であ
ることを特徴とするピン付き配線基板。
A pinned pad electrically connected to the wiring conductor is provided on the lower surface of an organic material-based insulating substrate having a wiring conductor, and the pinned pad has a substantially disc-shaped large-diameter portion at the upper end. A pin having a lead pin having an upper end surface and a side surface of the large-diameter portion and a pin interposed therebetween with solder interposed therebetween, wherein the thickness of the large-diameter portion is T, When the distance from the outer peripheral edge of the pinning pad to the large diameter portion is D, 0.05 mm ≦ T ≦
A wiring board with pins, wherein 0.3 mm and 0.25 ≦ D / T ≦ 1.5.
【請求項2】 配線導体を有する有機材料系の絶縁基板
の下面に前記配線導体と電気的に接続されたピン付けパ
ッドを設けるとともに該ピン付けパッドに上端部に略円
板状の径大部を有するリードピンを前記径大部の上端面
および側面と前記ピン付けパッドとの間に半田を介在さ
せて立設して成るピン付き配線基板に電子部品を搭載す
るとともに該電子部品の電極と前記配線導体とを電気的
に接続して成る電子装置であって、前記径大部の厚みを
T、前記ピン付けパッドの外周縁から前記径大部までの
距離をDとしたときに、0.05mm≦T≦0.3mm
であり、かつ0.25≦D/T≦1.5であることを特
徴とする電子装置。
2. A pinned pad electrically connected to the wiring conductor is provided on a lower surface of an organic material-based insulating substrate having a wiring conductor, and a substantially disk-shaped large-diameter portion is provided at an upper end of the pinned pad. An electronic component is mounted on a pinned wiring board having a lead pin having a vertical position with the solder interposed between the upper end surface and the side surface of the large-diameter portion and the pinning pad, and the electrode of the electronic component and the electrode An electronic device electrically connected to a wiring conductor, wherein T is the thickness of the large-diameter portion, and D is the distance from the outer peripheral edge of the pinning pad to the large-diameter portion. 05mm ≦ T ≦ 0.3mm
And 0.25 ≦ D / T ≦ 1.5.
JP2001019609A 2001-01-29 2001-01-29 Wiring board with pin and electronic device using the same Pending JP2002223074A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001019609A JP2002223074A (en) 2001-01-29 2001-01-29 Wiring board with pin and electronic device using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001019609A JP2002223074A (en) 2001-01-29 2001-01-29 Wiring board with pin and electronic device using the same

Publications (1)

Publication Number Publication Date
JP2002223074A true JP2002223074A (en) 2002-08-09

Family

ID=18885458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001019609A Pending JP2002223074A (en) 2001-01-29 2001-01-29 Wiring board with pin and electronic device using the same

Country Status (1)

Country Link
JP (1) JP2002223074A (en)

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