JP2002217718A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit that is short in lockup time and prevents occurrence of unlocking. SOLUTION: The PLL circuit is provided with a generating means 2 that generates 1st and 2nd reference signals, a 1st variable frequency divider 4 that outputs a 1st feedback signal, a 2nd variable frequency divider 8 that outputs a 2nd feedback signal and an excluding means 14 that excludes the output of 2nd feedback signal while the 1st feedback signal is outputted to convert it into a 3rd feedback signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL circuit.

[0002]

2. Description of the Related Art Conventionally, this type of circuit is, for example, "SANY
O TECHNICAL REVIEW ”, VOL. 1
0, NO. 1, FEB. It is shown on page 32 of 1978. However, this circuit is a one-stage phase comparator (using only one position comparator) and performs only one phase comparison during one cycle of the reference signal, so that the lock-up time (output The first disadvantage is that the time until the signal is synchronized is short.

[0003] In order to solve this drawback, Japanese Patent Laid-Open No.
No. 135822 has been proposed. According to this publication, generating means for generating a plurality of reference signals having different phases, a plurality of (for example, four) frequency dividers for dividing an output signal of the voltage controlled oscillator, and a feedback signal of each frequency divider are provided. A plurality of phase comparators for comparing each reference signal are provided.

[0004]

However, the circuit disclosed in the above publication has a second drawback in that the power consumption is large. The inventor of the present invention has investigated the cause and found that the reason is that a plurality of frequency dividers are provided. Further, if the phase comparison is performed 16 times during one cycle of the reference signal in order to further reduce the lock-up time, 16 frequency dividers are required, and the power consumption is further increased.

Further, since a plurality of frequency dividers requiring a relatively large amount of space are used, there is a third disadvantage that the size of the apparatus is increased, the cost is increased, and it is difficult to implement an LSI.

The present applicant has filed Japanese Patent Application No. 2000-76250 in order to solve these drawbacks. According to this application, two variable frequency dividers 4 and 9 each have a first feedback circuit. And a second feedback signal. However, while these feedback signals are being output together, the outputs of the phase comparators to which these feedback signals are input interfere with each other, and the output of the phase comparator becomes out of lock. ).

Therefore, the present invention takes into account such conventional disadvantages, and has a short lock-up time, a small power consumption, a low cost and easy to be integrated into an LSI, and no lock release.
A PLL circuit is provided.

[0008]

In order to solve the above-mentioned problems, according to the first aspect of the present invention, a generating means for generating a first reference signal and a second reference signal, and an output signal of a voltage controlled oscillator are respectively separated. A first variable frequency divider that outputs a first feedback signal, a second variable frequency divider that outputs a second feedback signal, and a second variable frequency divider that outputs the second feedback signal while the first feedback signal is being output. An elimination means for eliminating the output and converting the output into a third feedback signal.

According to the present invention, the first variable frequency divider is set with a frequency division number N (N is a value obtained by dividing a set frequency by a reference frequency), and the second variable frequency divider has Dividing number N / n
(N is an integer of 3 or more).

[0010] According to the present invention of claim 3, the generating means includes:
Generating a plurality of reference signals having different phases, wherein one of the reference signals is the first reference signal and the other (n-1)
The sum of the reference signals is the second reference signal.

According to a fourth aspect of the present invention, a first phase comparator for comparing the phase of the first reference signal and the first feedback signal;
A second phase comparator for comparing the phases of the second reference signal and the third feedback signal is provided.

According to a fifth aspect of the present invention, the exclusion means includes:
Its input side is connected to the output side of the first variable frequency divider and the output side of the second variable frequency divider, and its output side is connected to the input side of the second phase comparator, and comprises a logic circuit.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A PLL circuit 1 according to an embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of the PLL circuit 1, and FIG. 2 is a time chart of each signal used in the PLL circuit 1.

In these figures, the generating means 2 comprises, for example, a reference oscillator OSC, a fixed frequency divider M, a ring counter RIC, an OR gate 3 and the like. Fixed frequency divider M
Is divided at a frequency division ratio of 64, for example, and is connected between the reference oscillator OSC and the ring counter RIC. The fixed frequency divider M converts the signal (oscillation frequency is, for example, 25.6 MHz) output from the reference oscillator OSC into 64 and divides the signal (frequency is 400 KHz) by a ring counter R
Output to IC.

The ring-type counter RIC is connected to, for example, 16 flip-flops (not shown), and outputs 16 reference signals FR1 to FR16 in response to the input of the above 400 KHz signal.

The reference signal FR2 is 1/1 of the reference signal FR1.
It is delayed from the reference signal FR1 by six periods. Similarly, the reference signal FRA (A is an integer from 2 to 16) is (A−
1) It is delayed from the reference signal FR1 by / 16 cycle. In this way, each reference frequency of the reference signals FR1 to FR16 is 400 KHz ÷ 16 = 25 KHz, which matches the desired channel space (inter-station frequency). As described above, the generating means 2 outputs the plurality of reference signals FR having different phases.
1 to FR16 are generated.

The first reference signal (reference signal) FR1 is
It is input to one input side of the phase comparator PC1. Reference signal F
Each of R2 to FR16 is input to the input side of the OR gate 3, and the output of the OR gate 3 is input to one input side of the second phase comparator PC2. That is, one first reference signal FR1
Is input to the first phase comparator PC1, the plurality of reference signals FR2 to FR16 are added by the OR gate 3, and the added second reference signal FR is output to the second phase comparator PC1.
2 is input. As described above, the generation unit 2 generates the first reference signal FR1 and the second reference signal FR.

The first variable frequency divider 4 includes, for example, a 2-coefficient prescaler 5, a swallow counter A1, and a course counter N1.
And so on. The 2 coefficient prescaler 5 is, for example,
The frequency division of 64 or 65 is performed. A first match circuit (not shown) is connected to the swallow counter A1, and a second match circuit (not shown) is connected to the course counter N1. The load signal L1 output from the first variable frequency divider 4 is applied to a swallow counter A1 and a course counter N1.

For example, it is assumed that the user has set 1.65 GHz with a set frequency key (not shown). The control unit 6 (comprising a microcomputer or the like) connected to the set frequency key calculates the frequency division number N of the first variable frequency divider 4 and outputs it to the first variable frequency divider 4. That is, N = 1.65
× 106 KHz ÷ 25 KHz = 66000 (because the reference frequency is 25 KHz). That is, the first variable frequency divider 4
Is a value obtained by dividing a set frequency by a reference frequency, and a frequency division number N is set.

Based on the frequency division number N, the control unit 6 operates the number of times K1 of the swallow counter A1 and the course counter N1.
Is calculated and set (for example, K1 = 16
Times, K2 = 1031 times). Thus, the first variable frequency divider 4
Can be switched by the pulse swallow counter with only two types of frequency division, so that the propagation delay time can be reduced and the operation speed can be improved.

As described above, the first feedback signal FP1 obtained by dividing the output signal VO of the voltage controlled oscillator VCO by N is input to the other input side of the first phase comparator PC1.

The first phase comparator PC1 compares the phase of the first reference signal FR1 with the phase of the first feedback signal FP1, and compares the phase comparison signal (pump-up signal U1) with the phase comparison signal (pump-down signal D1). To the first charge pump CP1
Output to That is, the first phase comparator PC1 compares the phase of one first reference signal FR1 with one first feedback signal FP1 output from the first variable frequency divider 4.

The first charge pump CP1 generates an error signal ER1 based on the phase comparison signals U1 and D1, and outputs the error signal ER1 to the low-pass filter LPF.

The low-pass filter LPF outputs the error signal ER
A control voltage CV from which one high-frequency component is cut is generated and output to the voltage controlled oscillator VCO. These generating means 2
, A first phase comparator PC1, and a first charge pump CP
1, a low-pass filter LPF, and a voltage-controlled oscillator VC
A first PLL frequency synthesizer 7 is constituted by O, the first variable frequency divider 4, and the like.

The second variable frequency divider 8 comprises, for example, a 2-coefficient prescaler 9, a swallow counter A2, a course counter N2 and the like. The two-coefficient prescaler 9 performs, for example, frequency division of 32 or 33. A first match circuit (not shown) is connected to the swallow counter A2, and a second match circuit (not shown) is connected to the course counter N2. The load signal L2 output from the second variable frequency divider 8 is applied to a swallow counter A2 and a course counter N2.

As described above, the division number N is stored in the second variable frequency divider 8.
Is given. Assuming that the total number of the plurality of reference signals FR1 to FR16 is n, for the second variable frequency divider 8, for example, N /
n is given (set). At this time, the second reference signal FR is obtained by adding (n-1) reference signals FR2 to FR16.

For example, if n = 16, the controller 6
Is N / n = 66000/16 with respect to the second variable frequency divider 8.
= 4125. The control unit 6 calculates and sets the number of operations K3 of the swallow counter A1 and the number of operations K4 of the course counter N2 based on the frequency division number N / n (for example, K3 = 29 times, K4 = 128 times). ).

In this way, the second variable frequency divider 8 divides the output signal VO of the voltage controlled oscillator VCO by the frequency division number N / n (for example, 4125), and 16 Hi per cycle TR.
A second feedback signal fp including a level signal (feedback signal) fp1 and FP2 to FP16 is output (see FIG. 2).

As described above, the phase generated by the generating means 2 is different on one input side of the second phase comparator PC2 (n-
1) A second reference signal FR obtained by adding the reference signals FR2 to FR16 is input.

The input side of the rejection means 14 is connected to the output side of the first variable frequency divider 4 and the output side of the second variable frequency divider 8. The output side of the rejection means 14 is connected to the second phase comparator PC
2 are connected to the other inputs.

The elimination means 14 is, for example, a NAND gate 15
And a logic circuit comprising an AND gate 16. The first feedback signal FP1 is input to one input side of the NAND gate 15, and the second feedback signal f is input to the other input side.
p is input.

One input of the AND gate 16 receives the output of the NAND gate 15, the other input receives the second feedback signal fp, and the output of the AND gate 16 is connected to the second phase comparator PC2. Is input to the input side of.

The rejection means 14 outputs the first feedback signal FP1
Is a Lo signal and the second feedback signal fp is a Lo signal, the Lo signal is output (this is called a first state).
The elimination unit 14 outputs a Hi signal when the first feedback signal FP1 is a Lo signal and the second feedback signal fp is a Hi signal (this is referred to as a second state).

The rejection means 14 determines that the first feedback signal FP1 is H
When the signal is an i signal and the second feedback signal fp is a Lo signal, a Lo signal is output (this is called a third state). The elimination unit 14 is configured such that the first feedback signal FP1 is a Hi signal,
And when the second feedback signal fp is a Hi signal, it outputs a Lo signal (this is called a fourth state).

As described above, while the first feedback signal FP1 is being output (ie, when the first feedback signal FP1 is a Hi signal), the rejection means 14 outputs the second feedback signal fp to the output fp1.
(That is, the signal fp is a Hi signal) is excluded. As a result, at points A and B, the third feedback signal FP becomes a Lo signal (see FIG. 2).

In this manner, the first feedback signal FP1 becomes Hi
When the signal is a signal, a signal obtained by converting the output of the second feedback signal fp1 into a Lo signal is referred to as a third feedback signal FP (see FIG. 2).

As in the second state, the first feedback signal F
If the second feedback signal fp is a Hi signal when P1 is a Lo signal, the elimination means 14 outputs the second feedback signal fp as a Hi signal. As a result, the third feedback signal FP becomes A
At point B, point B, etc. (when the first feedback signal FP1 is a Hi signal), the signal becomes Lo, but at other points, the second feedback signal f
This is the same waveform as p.

As described above, the second reference signal FR and the third feedback signal FP are input to the second phase comparator PC2 (see FIGS. 1 and 2).

The second phase comparator PC2 receives the second reference signal F
R (the sum of the reference signals FR2 to FR16) and the third feedback signal FP (comprising the feedback signals FP2 to FP16)
Are compared in phase, and a phase comparison signal (pump-up signal U
2) and the phase comparison signal (pump down signal D2) is output to the second charge pump CP2.

The second charge pump CP2 generates an error signal ER2 based on the phase comparison signals U2 and D2, and outputs the error signal ER2 to the low-pass filter LPF.

The low-pass filter LPF outputs the error signal ER
A control voltage CV from which the high frequency component 2 is cut is generated and output to the voltage controlled oscillator VCO. These generating means 2
, A second phase comparator PC2, and a second charge pump CP
2, a low-pass filter LPF, and a voltage-controlled oscillator VC
The second PLL frequency synthesizer 10 is composed of O, the second variable frequency divider 8, the elimination means 14, and the like.

The lock detector 11 receives the first feedback signal FP1 output from the first variable frequency divider 4 and the second reference signal FR1. The lock detector 11 is, for example, a known detector including an AND gate and a resistor. This PLL circuit 1
Rises (at the time of search), the frequency of the output signal VO of the voltage controlled oscillator VCO is different from the set frequency.
The feedback signal FP1 and the first reference signal FR1 are not synchronized. Therefore, at this time, the lock detector 11 outputs a Lo signal (asynchronous detection signal) to the control unit 6.

When the PLL circuit 1 is locked (for example, when the frequency of the output signal VO falls within ± 300 Hz of the set frequency), the first feedback signal FP1 and the first reference signal F
R1 is almost synchronized. At this time, the lock detector 1
1 outputs a Hi signal (synchronization detection signal) to the control unit 6. This state is expressed as “steady state”.

Each output terminal of the control section 6 is electrically connected to the second variable frequency divider 8, the second phase comparator PC2, and the second charge pump CP2, respectively. Note that the lock detector 11 may be provided so as to be attached to the first phase comparator PC1, or may be provided integrally with the first phase comparator PC1. The PLL circuit 1 is configured by the above components.

Next, according to FIGS. 1 and 2, the present PLL circuit 1
Will be described. First, for example, it is assumed that the user sets 1.65 GHz with the set frequency key and presses the start key.

The control section 6 outputs the frequency division number N = 66000 to the first variable frequency divider 4. At the same time, the control unit 6
Is N / n = 66000/16 with respect to the second variable frequency divider 8.
= 4125 is output.

The signal 25.6 MHz of the reference oscillator OSC is frequency-divided to 400 KHz by the fixed frequency divider M.
16 is output. The reference signals FR1 to FR16 have a reference frequency of 25 KHz and rise at timings t1 to t16, respectively (see FIG. 2).

The first variable frequency divider 4 includes a voltage controlled oscillator VC
The output signal VO from O is divided by a division number N = 66000 to generate a first feedback signal FP1, and the first feedback signal FP
1 (see FIG. 2) is output to the first phase comparator PC1.

The second variable frequency divider 8 divides the output signal VO by a dividing number N / n = 4125 to generate a second feedback signal fp. The elimination unit 14 eliminates the output fp1 of the second feedback signal fp while the first feedback signal FP1 is being output, and converts the second feedback signal fp into the third feedback signal FP.

The first phase comparator PC1 receives the first reference signal F
It compares the phase of R1 with the first feedback signal FP1, and outputs the phase comparison signals U1 and D1 to the first charge pump CP1. The first charge pump CP1 outputs the phase comparison signal U1,
In accordance with D1, an error signal ER1 is output to the low-pass filter LPF. The low-pass filter LPF outputs a control voltage CV to the voltage controlled oscillator VCO according to the error signal ER1.

Next, the second phase comparator PC2 compares the phases of the second reference signal FR and the third feedback signal FP, and
For the charge pump CP2, the phase comparison signals U2, D2
Is output.

The second charge pump CP2 outputs an error signal ER2 to the low-pass filter LPF according to the phase comparison signal. According to the error signal ER2, the low-pass filter LPF supplies the voltage-controlled oscillator VCO with
The control voltage CV is output. As a result, the voltage-controlled oscillator V
The output signal VO output from the CO approaches the set frequency. Such a phase comparison operation is repeated.

With this configuration, 1 of the first reference signal FR1
Since the phase comparison is performed 16 times during the period (TR) (see FIG. 2), the lock-up time (the time until the output signal VO is substantially synchronized with the set frequency) is shorter than that of the conventional single-stage phase comparator. Time) is reduced to about 1/16 times.

As described above, when the synchronization is not detected (that is, at the time of the search in which the lock detector 11 outputs the Lo signal to the control unit 6), the first variable frequency divider 4 and the first variable frequency divider 4
The phase comparator CP1, the first charge pump CP1, the second variable frequency divider 8, the second phase comparator CP2, the second charge pump CP2, etc. are operating.

When the above-described phase comparison is repeated, the output signal VO is synchronized with the set frequency. That is, at this time, the frequency of the output signal VO is set to ± 300 of the set frequency.
Hz. At this time (at steady state), the lock detector 11
Outputs a Hi signal (synchronization detection signal) to the control unit 6.

In the steady state, the control section 6 stops the second variable frequency divider 8 and the second phase comparator PC2 by inputting the synchronization detection signal, thereby stopping the second charge pump CP2.
To stop.

In a steady state, the control section 6 continues the operation of only the first variable frequency divider 4 and continues the operations of the first phase comparator PC1 and the first charge pump CP1. That is,
The control unit 6 continues the operation of the first PLL frequency synthesizer 7 and stops the operation of the second PLL frequency synthesizer 10.

As described above, when the synchronization detection signal is input (at a steady state), the control unit 6 continues the operation of the first PLL frequency synthesizer 7, so that the frequency division and the phase comparison operation are performed accurately. As a result, it is possible to stably output the output signal VO having the set frequency of 1.65 GHz.

When the synchronization detection signal is input (at a steady state),
The control unit 6 includes a second variable frequency divider 8 and a second phase comparator PC2.
Then, the operation of the second charge pump CP2 is stopped. As a result, the power consumption of the PLL circuit 1 is reduced.

[0060]

According to the first aspect of the present invention, the generating means for generating the first reference signal and the second reference signal, and the first signal for dividing the output signal of the voltage controlled oscillator and outputting the first feedback signal are provided. A variable frequency divider and a second variable frequency divider that outputs a second feedback signal; and, while the first feedback signal is being output, the output of the second feedback signal is eliminated and converted to a third feedback signal. And an exclusion unit. As described above, while the first feedback signal is being output, the output of the second feedback signal is excluded. Therefore, the phase comparison output of the first phase comparator to which the first feedback signal is input and the second feedback signal are output. The phase comparison output of the second phase comparator to which the signal is input does not interfere with each other. As a result, the output signal VO is out of lock (the phase signal
However, suddenly deviating from the set frequency) can be prevented.

According to the second aspect of the present invention, the first variable frequency divider has a frequency division number N (N is a value obtained by dividing a set frequency by a reference frequency), and the second variable frequency divider has: Division number N / n
(N is an integer of 3 or more). As described above, since the frequency division number N / n is set for the second variable frequency divider, the second variable frequency divider operates during one cycle of the first reference signal.
A plurality of (n-1) Hi level signals are output. Further, the first variable frequency divider outputs one first feedback signal during one cycle of the first reference signal. As a result, the phase comparator performs the phase comparison n times (n is an integer of 3 or more) during one cycle of the first reference signal, and the lock-up time is shortened. In addition, two variable frequency dividers may be used to perform the phase comparison n times during the one cycle. As a result, the number of variable frequency dividers can be reduced, the cost can be reduced, and the LSI can be easily implemented.

According to the third aspect of the present invention, the generating means includes:
Generating a plurality of reference signals having different phases, wherein one of the reference signals is the first reference signal and the other (n-1)
The sum of the reference signals is the second reference signal. Thus, the phases are different, (n-1)
Since the second reference signal obtained by adding the reference signals is input to the phase comparator, during one cycle of the first reference signal, (n-1)
Phase comparisons are performed at accurate timing. In addition, since the (n-1) reference signals are added, the circuit configuration can be simplified.

According to a fourth aspect of the present invention, a first phase comparator for comparing the phase of the first reference signal and the first feedback signal;
4. The PLL according to claim 3, further comprising a second phase comparator for comparing the phases of the second reference signal and the third feedback signal.
circuit. As described above, the first phase comparator compares the phase of the first reference signal, which is one of the plurality of reference signals, with the single first feedback signal, and thus can perform accurate phase comparison. As a result, an output signal that exactly matches the set frequency can be output in a steady state. The second phase comparator compares the phase of the second reference signal with the third feedback signal (a signal from which the output of the first feedback signal has been eliminated). As a result, the output of the first phase comparator and the output of the second phase comparator do not interfere with each other, and lock-out can be prevented.

According to a fifth aspect of the present invention, the exclusion means comprises:
The input side is connected to the output side of the first variable frequency divider and the output side of the second variable frequency divider, the output side is connected to the input side of the second phase comparator, and comprises a logic circuit. I do. Thus, while the first feedback signal is being output, the elimination means for eliminating the output of the second feedback signal is constituted by a logic circuit, so that the circuit configuration can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PLL circuit 1 according to an embodiment of the present invention.

FIG. 2 is a time chart of various signals used in the PLL circuit 1;

[Explanation of symbols]

 2 generating means 4 first variable frequency divider 8 second variable frequency divider 14 rejection means

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J106 AA04 CC20 CC21 CC53 DD46 FF01 FF08 FF09 KK03 PP03 QQ09 RR20

Claims (5)

[Claims] 1. A first variable frequency divider for generating a first reference signal and a second reference signal, a first variable frequency divider for dividing an output signal of a voltage controlled oscillator and outputting a first feedback signal, and a second variable frequency divider for outputting a first feedback signal.
A second variable frequency divider that outputs a feedback signal; and an elimination unit that eliminates the output of the second feedback signal and converts the output to a third feedback signal while the first feedback signal is being output. A PLL circuit characterized by the above-mentioned. 2. The frequency division number N (N is a value obtained by dividing a set frequency by a reference frequency) is set in the first variable frequency divider, and the frequency division number N / n is set in the second variable frequency divider. (N is an integer of 3 or more)
2. The PLL circuit according to claim 1, wherein 3. The generating means generates a plurality of reference signals having different phases, one of the reference signals is the first reference signal, and the other (n-1) reference signals are added. 3. The PLL circuit according to claim 2, wherein said signal is said second reference signal. 4. A first phase comparator for comparing the phase of the first reference signal and the first feedback signal, and a second phase comparator for comparing the phase of the second reference signal and the third feedback signal. 4. The PLL circuit according to claim 3, wherein: 5. The exclusion means, wherein an input side of the exclusion means is the first
5. The logic circuit according to claim 4, wherein the output is connected to an output of the variable frequency divider and an output of the second variable frequency divider, and an output of the variable frequency divider is connected to an input of the second phase comparator. PLL circuit.