JP2002217376A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce variations in a threshold voltage and a drain current resulted from a thickness and a diffusing state of a gate electrode, in the semiconductor device such as a high-frequency amplifier which uses an FET having a the gate electrode of a metal embedding type. SOLUTION: In the semiconductor device in which a DC bias dividing resistor is used for the FET having the gate electrode of a metal embedding type, a metal-semiconductor alloy layer is formed on a surface of one of a ground side resistor which connects the gate electrode of the FET and the ground electrode, and a power supply side resistor which connects the gate electrode of the FET and the terminal for supplying DC gate bias. Thus, it is possible to reduce variations in a threshold voltage and a drain current of the FET.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifying circuit for a compound semiconductor microwave, and more particularly to a semiconductor device having a resistance element used in a DC gate bias circuit for reducing power consumption.

[0002]

2. Description of the Related Art A typical monolithic IC for microwaves (hereinafter abbreviated as MMIC) as a high-frequency amplifier circuit using GaAs excellent in high-frequency characteristics has, for example, a two-stage FET as shown in an equivalent circuit diagram shown in FIG. Amplifier circuit,
DC cut capacitors 71, 72, 73 and microstrip lines 74, 75,
76, 77 and bias voltage dividing resistors 63, 64, 65, 66
It is composed of When the gate voltage VG of the FET is supplied from the power supply terminal 67 and the drain voltage VD is supplied from the power supply terminal 68, the high-frequency signal input to the input terminal 69 is amplified and output from the output terminal 70. . Here, ground side resistors 63 and 6 are provided as DC bias voltage dividing resistors for applying DC bias voltages VG1 and VG2 from the power supply terminal 67 to the gates of the FETs 61 and 62, respectively.
5 and gate power supply side resistors 64 and 66 are connected.

[0003] These resistors are formed in a semi-insulating GaAs substrate by ion implantation resistors, and the voltage division ratio is always fixed. For example, the gate power supply side resistance 64 = 3KΩ, the ground side resistance 63 = 2KΩ, and the voltage VG1 of the power supply terminal 67 is -5V.
In this case, the DC gate bias voltage VG1 of the FET 61 is fixed at -2V.

In this conventional compound semiconductor MMIC amplifying circuit, the amplifying circuit current, ie, the idle current Iid, increases or decreases when the high-frequency input voltage is off due to manufacturing variations in the threshold voltage of the field-effect transistor. The current at the time of the small RF signal also varies. Further, when the circuit current decreases, the output power becomes insufficient. On the other hand, when the circuit current increases, the efficiency decreases.

As a method for solving this problem, Japanese Patent Laid-Open Publication No.
As disclosed in US Pat. No. 4,140,852, an ion-implanted resistor in which the ground-side resistance of the DC bias voltage dividing resistor is formed in the same compound semiconductor substrate as the FET, and the resistance on the gate power supply side is an n-layer on the compound semiconductor substrate. And an active layer recess resistor formed by recessing the MMIC to form a circuit for compensating the idling current of the circuit.

[0006] However, such a compensation circuit is referred to as an MM.
If the FET used for the MMIC is a buried metal gate electrode even if it is used for an IC, it depends on the thickness of the metal-semiconductor alloy layer on the Schottky junction surface formed when the buried metal gate electrode is formed. Since the threshold voltage changes and the operating current of the FET is greatly affected, variations in the characteristics of the MMIC due to variations in the drain current have occurred. Therefore, in order to use a metal-embedded gate electrode FET for an MMIC, it has been desired to compensate for variations in drain current due to a change in threshold voltage.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and a semiconductor device having an amplifier circuit for a compound semiconductor microwave according to the present invention has been made in view of the above problems. It is an object of the present invention to provide a semiconductor device such as a high-frequency amplifier using an FET having an electrode, which can suppress variations in threshold voltage and drain current due to the thickness and diffusion state of a gate electrode.

[0008]

In order to achieve the above object, a semiconductor device according to the present invention comprises a FET having a buried metal gate electrode and a DC bias voltage dividing resistor connected to the FET gate electrode and a ground electrode. A metal-semiconductor alloy layer is formed on one of the surfaces of the ground-side resistor connected between the gate and the power supply-side resistor connected between the gate electrode of the FET and the terminal supplying the DC gate bias. It is characterized by doing.

As a result, in a FET having a buried metal gate electrode, variations in threshold voltage and drain current caused by manufacturing variations in the gate electrode can be suppressed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

In the amplifier circuit shown in FIG. 1, an FET 1 for amplifying a high-frequency signal is provided between an input terminal 5 for inputting a high-frequency signal and an output terminal 6 for outputting a high-frequency signal. The drain electrode is connected to the output terminal 6, the source electrode is connected to the ground terminal 9, and the gate electrode is connected to the input terminal 5 via the capacitor 8. Also, a drain power supply terminal 7 is provided to supply a drain current.
Is connected to the drain terminal of the FET 1 and the gate power supply terminal 4 is connected to the gate terminal of the FET 1 via the power supply side resistor 2 to apply a positive DC gate bias and to the ground terminal 9 via the ground side resistance 3. It is connected. Here, the DC gate bias can be fixed by dividing the voltage applied from the gate power supply terminal 4 according to the ratio of the resistance values of the power supply side resistance 2 and the ground side resistance 3.

Next, FIG. 2 shows a layout of a semiconductor device in which this circuit is formed on a semi-insulating GaAs substrate.

The FET 10 of the semiconductor device shown in FIG. 2 has an n-type active layer formed of a compound semiconductor and a high-concentration n ⁺ -type active layer formed on a semi-insulating GaAs substrate by ion implantation. ^A drain electrode 12 and a source electrode 13 are formed on the upper surface of the ⁺ type active layer. Further, a gate electrode 11 mainly composed of Pt is formed on the upper surface of the n-type active layer between the drain electrode 12 and the source electrode 13, and a metal-embedded gate electrode is formed by metal diffusion by heat treatment. Here, a portion of the gate electrode 11 buried in the n-type active layer portion is formed with a metal-semiconductor alloy layer in which a metal and a semiconductor are mixed.

The gate electrode 11 of the FET 10 is connected to an input terminal 17 via a capacitor 20, the drain electrode 12 is connected to an output terminal 18 and a drain power supply terminal 19, and the source electrode 13 is connected to a ground terminal 21. I have.

In order to apply a DC gate bias to the FET 10, the gate electrode 11 is connected to a gate power supply terminal 16 via a power supply-side resistor 14 and is connected to a ground-side resistor 1
5 is connected to the ground terminal 21.

Next, A- of the power supply side resistor 14 shown in FIG.
FIG. 3 is a sectional view taken along the line A ′.

The power supply side resistor 14 is formed, for example, by the following steps. That is, first, the ion implantation resistor 32 is formed on the semi-insulating GaAs substrate 31 by ion implantation simultaneously with the formation of the n-type active layer of the FET 10 described above. The resistance value of the ion implantation resistor 32 can be adjusted by the amount of the ion implantation. Thereby, the resistance value of the power supply-side resistor 14 can be fixed to a desired resistance value.

Next, the above-described FET 1 is placed on the semi-insulating GaAs substrate 31 adjacent to both ends of the ion implantation resistor 32.
The n ⁺ type semiconductor layer 33 is formed by ion implantation simultaneously with the formation of the n ⁺ type active layer of 0. This n ⁺ type semiconductor layer 33
An ohmic electrode 34 is formed on the upper surface of the FET at the same time as the formation of the ohmic electrode of the FET by a vacuum deposition method or the like, and an interlayer insulating film 35 is formed except for a part of the surface of the ohmic electrode 34 necessary for connection. A metal wiring layer 36 is formed on the upper surface of the ohmic electrode 34 and the metal wiring layer 36.
Are connected. Then, a protective film 37 is formed on the entire surface.

Next, B- of the ground-side resistor 15 shown in FIG.
FIG. 4 is a sectional view taken along the line B ′.

The ground-side resistor 15 is formed, for example, by the following steps. That is, first, the ion implantation resistor 32 is formed on the semi-insulating GaAs substrate 31 by ion implantation simultaneously with the n-type active layer of the FET 10 described above. The resistance value of the ion implantation resistor 32 can be adjusted by the amount of the ion implantation. Thereby, the resistance value of the ground-side resistor 15 can be fixed to a desired resistance value.

Next, the above-mentioned FET 1 is placed on the semi-insulating GaAs substrate 31 adjacent to both ends of the ion implantation resistor 32.
The n ⁺ type semiconductor layer 33 is formed by ion implantation simultaneously with the formation of the n ⁺ type active layer of 0. This n ⁺ type semiconductor layer 33
The ohmic electrode 34 is formed at the same time as the ohmic electrode of the FET by a vacuum evaporation method or the like. Then
The metal layer 41 is formed on the upper surface of the ion implantation resistor 32 at the same time when the gate electrode of the FET is formed. Then, in the step of turning the gate electrode of the FET into a metal-embedded gate electrode by metal diffusion by heat treatment, the metal layer 41 is also diffused into the ion implantation resistor 32 to form a metal-semiconductor alloy layer 42. Here, when the metal layer 41 is formed simultaneously with the gate electrode of the FET, the diffusion amount of the metal layer 41 becomes substantially equal to the diffusion amount of the gate electrode, and the thickness of the metal-semiconductor alloy layer 42 and the gate electrode The embedding depth is almost the same.

Next, the ohmic electrode 34 necessary for connection
An interlayer insulating film 35 is formed except for a part of the surface of the substrate, a metal wiring layer 36 is formed on the upper surface of the interlayer insulating film 35, and the ohmic electrode 34 and the metal wiring layer 36 are connected. Then, a protective film 37 is formed on the entire surface.

In a semiconductor device using an FET with a metal-embedded gate electrode in the amplifier circuit shown in FIG. 1, the step of converting the gate electrode of each FET into a metal-embedded gate electrode is performed by the thickness of the gate electrode and heat treatment. The thickness variation of the metal-semiconductor alloy layer of the gate electrode occurs. For this reason, the threshold voltage of the FET changes. However, by forming a metal-semiconductor alloy layer on the surface of the ground-side resistor 3 as in this embodiment, the change in the threshold voltage of the FET can be compensated.

That is, as the thickness of the metal-semiconductor alloy layer of the gate electrode of the FET increases, the threshold voltage of the FET decreases, and the drain current shifts in the direction of decreasing.
Since the thickness of the metal-semiconductor alloy layer 42 on the surface of the ground-side resistor 3 is also increased, the spread of the surface depletion layer increases, and the resistance value of the ground-side resistor 3 increases, so that the gate bias of the FET shifts in the positive direction. Then, the drain current can be compensated for in the increasing direction. Conversely, when the thickness of the metal-semiconductor alloy layer of the gate electrode of the FET is reduced, the FET
Of the metal-semiconductor alloy layer 42 on the surface of the ground-side resistor 3 becomes thinner, the spread of the surface depletion layer becomes smaller and the ground-side resistor 3 FET resistance decreases
, The gate bias shifts in the negative direction, and the drain current can be reduced.

Next, in a semiconductor device using an FET having a buried metal gate electrode in an amplifier circuit as shown in FIG. 1, the metal-semiconductor alloy layer of the gate electrode is made of Pt-GaAs.
When the ground-side resistor 3 is formed by an s-alloy layer, the ground-side resistor 3 is formed by a conventional ion-implanted resistor, and when the ground-side resistor 3 is formed by providing a metal-semiconductor alloy layer 42 on the surface of the ion-implanted resistor according to the present invention. Pt of the gate electrode
FIG. 5 shows a change in drain current depending on the thickness of the -GaAs alloy layer.

When the ground-side resistor 3 shown in FIG. 5 is formed by a conventional ion implantation resistor, the Pt of the gate electrode
-The drain current decreases as the thickness of the GaAs alloy layer increases. In contrast, when the metal-semiconductor alloy layer 42 is formed on the surface of the ground-side resistor 3 and the ion-implanted resistor as in the present invention, the Pt-GaAs of the gate electrode is formed.
Even if the thickness of the alloy layer changes, the drain current hardly changes. That is, a change in drain current caused by a change in the thickness of the Pt-GaAs alloy layer of the gate electrode can be compensated, and the drain current can be kept at a constant value.

As an embodiment of the present invention, when the semiconductor substrate is GaAs and the metal material of the gate electrode is Pt, a metal layer 41 of the same Pt as the metal material of the gate electrode is formed on the surface of the ground-side resistor. Although the case where the semiconductor alloy layer 42 is formed has been described, the metal-semiconductor alloy layer formed of any combination of materials in which the metal-semiconductor alloy layer 42 has a Schottky interface can use the metal-embedded FET of the present invention. By compensating for the threshold voltage of the semiconductor device, the drain current can be maintained at a constant value.

Even if the shape and the formation region of the metal-semiconductor alloy layer 42 formed on the surface of the ion-implanted resistor slightly change, if the surface of the ion-implanted resistor covers at least 50% or more, the drain current is kept at a constant value. Can be kept. In the embodiment, the case where the resistor is formed on the surface of the ion-implanted resistor has been described. However, it is needless to say that a metal-semiconductor alloy layer is formed on the surface of the resistor formed by diffusion or epitaxial growth other than ion implantation. Can achieve the same effect.

In this embodiment, the case where a positive DC gate bias is applied to the gate power supply terminal of the FET 1 shown in FIG. 1 has been described. However, the negative DC gate is applied to the gate power supply terminal shown in FIG. Even in the case of operating by applying a bias, the same effect as that obtained in this embodiment can be obtained by reversing the structure of the ground-side resistor and the structure of the power-supply-side resistor. That is, when a negative DC gate bias is applied to the gate power supply terminal, the ground-side resistor 15 is formed with the structure of the ion implantation resistor shown in FIG. 3, and the power supply-side resistor is formed on the surface of the ion implantation resistor shown in FIG. By forming a metal-semiconductor alloy layer on the substrate, a change in drain current of the FET can be compensated.

[0030]

As described above, according to the present invention, in a semiconductor device using a DC bias voltage dividing resistor for an FET having a metal embedded gate electrode, the FET is connected between the gate electrode and the ground electrode of the FET. Ground side resistance or F
By forming a metal-semiconductor alloy layer on one of the surfaces of the power supply side resistance between the gate electrode of the ET and the terminal supplying the DC gate bias, the threshold voltage or the Variation in drain current can be suppressed.

As a result, in a semiconductor device such as a high-frequency amplifier using an FET having a gate electrode of a buried metal type, a decrease in the yield of the semiconductor device due to variations in the threshold voltage and drain current due to the thickness and diffusion state of the gate electrode. Can be suppressed.

[Brief description of the drawings]

FIG. 1 is an amplifier circuit.

FIG. 2 is a layout of a semiconductor device in which the amplifier circuit of FIG. 1 is formed on a semi-insulating GaAs substrate.

FIG. 3 is a cross-sectional view of the power supply-side resistor A-A ′ shown in FIG. 2;

FIG. 4 is a sectional view taken along line B-B ′ of the ground-side resistor 15 shown in FIG. 2;

FIG. 5 shows the relationship between the thickness of a Pt—GaAs alloy layer of a gate electrode and drain current.

FIG. 6 is an equivalent circuit of a typical monolithic IC for microwaves as a high-frequency amplifier circuit using GaAs.

[Explanation of symbols]

5, 17, 69 ----- Input terminal 6, 18, 70 ----- Output terminal 1, 10, 61, 62 ----- FET 2, 14, 64, 66 ----- Power supply Side resistance 3,15,63,65 ----- Ground side resistance 8,20,71,72 ----- Capacitor 7,19,68 ----- Drain power supply terminal 4,16,67- --- Gate power supply terminal 31 ----- Semi-insulating Ga
As substrate 32 ----- Ion implantation resistance 33 ----- n ⁺ type semiconductor layer 34 ----- Ohmic electrode 35 ----- Interlayer insulating film 36 ----- Metal wiring layer 37- ---- Protective film 41 ----- Metal layer 42 ----- Metal-semiconductor alloy layer

Claims (7)

[Claims] 1. A semiconductor device in which a DC bias voltage dividing resistor is connected to an FET having a metal embedded gate electrode,
On the surface of either the ground-side resistor connected between the gate electrode of the FET and the ground electrode, or the power-side resistor connected between the gate electrode of the FET and the terminal supplying the DC gate bias A semiconductor device comprising a metal-semiconductor alloy layer. 2. A metal-semiconductor alloy layer is formed on a surface of the ground-side resistor when a DC gate bias supplied to a gate electrode of the FET is a positive bias. Semiconductor device. 3. The method according to claim 1, wherein a metal-semiconductor alloy layer is formed on the surface of the power-supply-side resistor when the DC gate bias supplied to the gate electrode of the FET is a negative bias. Semiconductor device. 4. A metal-semiconductor alloy layer formed on a surface of the ground-side resistor or the power-supply-side resistor covers at least 50% of a surface of the resistor. 4. The semiconductor device according to 3. 5. The ground-side resistor and the power-supply-side resistor are connected to each other by F
5. The semiconductor device according to claim 1, which has the same active structure as ET, and is formed by ion implantation, diffusion or epitaxial growth. 6. A metal-semiconductor alloy layer formed on a surface of the ground-side resistor or the power-supply-side resistor is formed of a metal containing Pt as a main component on a GaAs layer. The semiconductor device according to claim 1. 7. A metal-semiconductor alloy layer formed on the surface of the ground-side resistor or the power-supply-side resistor is manufactured in the same step as the step of forming the buried metal gate. 6. The method for manufacturing a semiconductor device according to claim 1.