JPH10178190A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain optimal Schottky junction and ohmic characteristic by controlling various characteristics, such as threshold voltage, etc., through simultaneous heat treatment of a Schottky electrode and 9η ohmic electrode. SOLUTION: A source electrode 16 and a drain electrode 17 made of Au-Ge based metal are formed on an n<+> region 15 of a GaAs substrate 11. Next, a gate electrode 22 formed of 300Å-thick Pt, 200Å-thick Mo, 1000Å-thick Ti, 500Å-thick Pt, and 3500Å-thick Au is formed on an active layer 13. Then it is heated at about 400 deg.C for on minute, and the source and drain electrodes 16 and 17 are changed into an alloy, so that they are connected with the region 15 through ohmically jointed, and the lowermost Pt layer of the gate electrode 22 is diffused to GaAs, so as to connect it with active layer through Schottky jointed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device. In particular, it relates to a method for manufacturing a field-effect transistor such as a GaAs MESFET for high output.

[0002]

2. Description of the Related Art A Pt-embedded field-effect transistor in which a gate electrode is formed of Pt, and the gate electrode is subjected to a heat treatment to form a Schottky junction of the gate electrode with an active layer, has a desired Schottky characteristic, current value,
It is a very effective device with a high threshold voltage and high withstand voltage.

FIG. 1 shows a conventional Pt embedded GaAsM.
FIG. 14 is a cross-sectional view showing a manufacturing process of the ESFET 9; FIG.
(A) is a diagram showing a semi-insulating GaAs substrate 1 before forming a gate electrode, a source, and a drain electrode.
An active layer 2 composed of an n-type ion implantation layer is formed on the surface of an As substrate 1, and a p layer 3 is formed thereunder. On both sides of the active layer 2 and the p layer 3, n ⁺ regions (source region, drain region) 4 into which n-type ions are implanted at a high concentration are formed.

First, as shown in FIG. 1B, a source electrode 5 having an ohmic junction with the n ⁺ region is formed on the n ⁺ region 4 of the GaAs substrate 1 by photolithography.
Then, a heat treatment for alloying is performed by forming the drain electrode 6. Next, a P electrode serving as a gate electrode 7 is formed on the upper surface of the active layer 2.
t is deposited by a vacuum evaporation method or the like. After this, H2
When heat treatment is performed at about 400 ° C. in a gas, Pt diffuses into the active layer, and Pt and GaAs undergo a solid-phase reaction, and PtAs
And a metal compound mainly composed of PtGa or the like. This P
The reaction layer 8 made of tAs, PtGa, or the like becomes a good Schottky junction, and the junction position becomes G with the progress of the solid-phase reaction.
Moving into aAs, a GaAs MESFET 9 having a buried Pt gate electrode 7 as shown in FIG. 1D is formed.

[0005]

SUMMARY OF THE INVENTION GaAs as described above
In the MESFET, a source electrode and a drain electrode (ohmic electrode) are formed, heat treatment for alloying is performed on the source electrode and the drain electrode, and then a gate electrode (Schottky electrode) made of Pt is deposited on the active layer. The gate electrode is heat-treated in order to obtain a desired current value, threshold voltage, and high withstand voltage.

However, the heat treatment of the gate electrode is often performed at about 400 ° C., so that the source electrode and the drain electrode already alloyed by the heat treatment are further subjected to the heat treatment, so that the source electrode and the drain electrode are heated. There is a problem in that it deteriorates and affects element characteristics.

In the case where the Schottky electrode is formed before the source and drain electrodes and heat treatment is performed, diffusion of the gate electrode into the active layer proceeds in the alloying process of the ohmic electrode, and the pinch-off voltage and the like are increased. However, it is difficult to control the various characteristics described above, and there is a problem that the element characteristics deteriorate.

The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and an object of the present invention is to simultaneously heat-treat a Schottky electrode and an ohmic electrode so that various characteristics such as a threshold voltage can be obtained. It is an object of the present invention to control characteristics so that a good Schottky junction and ohmic characteristics can be obtained.

[0009]

DISCLOSURE OF THE INVENTION A method for manufacturing a semiconductor device according to the present invention comprises:
After forming a Schottky electrode whose lowermost layer is made of Pt and an ohmic electrode on a semiconductor substrate, the Schottky electrode and the ohmic electrode are simultaneously heat-treated.

According to the method of the present invention, since the ohmic electrode and the Schottky electrode are simultaneously heat-treated, alloying of the ohmic electrode and control of characteristics such as the pinch-off voltage Vp by the Schottky electrode can be performed simultaneously. The manufacturing process of the semiconductor device can be simplified. In addition, since the heat treatment for the ohmic electrode and the heat treatment for the Schottky electrode are not separately performed, the heat treatment for one of the ohmic electrode and the Schottky electrode causes It is possible to reduce the variation in element characteristics and stabilize the element without deterioration. Further, since the deterioration of the element and the variation in the characteristics are reduced, the yield can be improved.

The heat treatment temperature is 350 to 450
It is desirable to be set to ° C. Ohmic electrode is 350 ° C
At lower temperatures, good ohmic properties are not exhibited, and both electrodes begin to deteriorate above 450 ° C.

[0012] Such a semiconductor device can be applied to a device using a compound semiconductor.
It can be used for AsMESFET. In particular, high effects can be obtained by using a Pt-embedded field-effect transistor that forms a Schottky junction by reacting the lowermost Pt layer and the active layer. In addition, in this case, if the lowermost Pt layer completely reacts with the active layer by heat treatment, variations in device characteristics can be reduced, and device characteristics can be stabilized.
The element characteristics can be easily managed by controlling the thickness of the layer.

The structure of the gate electrode is preferably such that a Mo layer is formed on a Pt layer (a reaction layer after heat treatment), a Ti layer is formed thereon, and a low-resistance metal layer such as Au or Al is formed thereon. . According to such an electrode configuration, the lowermost Pt
By making the layer completely react with the active layer, a good Schottky junction can be obtained, and a good operation can be performed even under a forward bias. Further, the gate resistance can be reduced by the low resistance metal layer. Further, the function of the Mo layer prevents interdiffusion between the Pt layer and the Ti layer, and stops the reaction between the gate electrode and the active layer when the Pt layer has completely reacted with the active layer. it can. Further, the Mo layer has a large film stress and poor adhesion to the Au layer and the Al layer.
By forming the i layer, the adhesion to the Mo layer can be improved.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment) FIGS. 2A to 2H show a Pt-embedded GaAs MESFET (hereinafter, referred to as an embodiment) according to an embodiment of the present invention.
FIG. 14 is a schematic cross-sectional view showing a manufacturing step of a Pt gate FET) 24. Hereinafter, an optimal embodiment of the present invention will be described with reference to FIG. First, as shown in FIG. 2A, p-type ions, for example, Be, are formed on the surface of the semi-insulating GaAs substrate 11.
Mg at an acceleration energy of 200 keV and an implanted ion density of 2
The p-type layer 12 is formed by implantation at a rate of × 10 ¹² / cm ² . Next, as shown in FIG. 2B, n-type ions, for example, Si
With an acceleration energy of 100 keV and an implanted ion density of 5 × 1
The n-type active layer 13 is formed by implantation at 0 ¹² / cm ² .

Next, as shown in FIG.
The surface of the s-substrate 11 is covered with a photoresist 14, a photoresist 14 is opened in a region where a source region and a drain region are to be formed by photolithography, and the photoresist 14 is used as a mask and selectively n-type through the mask opening. Ions, for example, Si are accelerated at an energy of 180 keV and an implanted ion density is 1 × 10 ¹³ / cm ^2.
Implanted into the n ⁺ region 15 (source region, drain region)
To form Thereafter, as shown in FIG. 2D, a source electrode 16 and a drain electrode 17 are formed on the n ⁺ region 15 using a metal made of Au-Ge.

Next, a resist film 19 is formed on the surface of the GaAs substrate 11, and photolithography is performed to obtain a resist film 19 as shown in FIG.
As shown in (e), an opening 20 having a width equal to the gate length and having a reverse taper shape is formed in the resist film 19. Next, the recess 18 is formed by dipping in a phosphoric acid-based etchant.

Thereafter, as shown in FIG. 2F, the active layer 13 is passed through the opening 20 of the resist film 19 by vapor deposition.
Pt with a thickness of 300 Å, Mo with a thickness of 200 、, Ti with a thickness of 1000 、, Pt with a thickness of 500 、, and a thickness of 350
A gate electrode metal layer 21 made of Au of 0 ° is sequentially deposited, and Pt / Mo / Ti
The gate electrode metal layer 21 made of / Pt / Au is peeled off (lifted off) together with the resist film 19, and the gate electrode 22 made of Pt / Mo / Ti / Pt / Au as shown in FIG. 2 (g) and FIG. To form

Thereafter, a heat treatment is performed at a temperature of about 400 ° C. for 1 minute to alloy the source and drain electrodes 16 and 17 to form an ohmic junction with the n ⁺ region 15.
The lowermost Pt layer of the gate electrode 22 is diffused into GaAs to form a Schottky junction with the active layer.

As schematically shown in FIGS. 4A and 4B,
By this heat treatment, Pt in the lowermost layer of the gate electrode 22 is diffused into GaAs, solid-phase reacts with GaAs to form an alloy, and a reaction layer 23 made of a compound such as PtAs or PtGa.
Is generated, and the gate electrode 22 is Schottky-bonded to the active layer 13. As a result, as shown in FIG. 2 (h), a Pt gate FET 24 including a Pt-embedded gate electrode 22 having a good Schottky junction and comprising a reaction layer (PtAs, PtGa) / Mo / Ti / Pt / Au. Is formed.

(Characteristics of this Embodiment) In the Pt gate FET manufactured by the above process, the gate electrode is composed of Pt (or a reaction layer) / Mo / Ti / Pt / Au. Of these, the lowermost Pt layer reacts with the active layer as described above, generates a reaction layer made of PtAs, PtGa, or the like, forms a buried gate electrode, and realizes a good Schottky junction. is there.

In the manufacturing method of the present invention, it is not always necessary that the lowermost Pt layer of the gate electrode is completely diffused into GaAs and completely reacted with GaAs, but as described below, it is completely reacted with GaAs. It is preferred that

A Pt layer not reacting with GaAs remains, or a metal other than Pt diffuses into GaAs and
When reacting with s, the reaction layer changes due to heat in the heat treatment step or heat during device operation, and the device characteristics vary, become unstable, or deteriorate. On the other hand, if the Pt layer formed on the active layer is completely reacted with GaAs to form a reaction layer, in a subsequent step after the formation of the gate electrode, a temperature equal to or higher than the heat treatment temperature of the gate electrode is obtained. Pt layer and GaAs even at heat treatment temperature
The reaction with s does not proceed any further, and the device characteristics do not change. In particular, the pinch-off voltage of the element does not change. Similarly, there is no possibility that the device characteristics such as the pinch-off voltage change and become unstable due to heat generated during the device operation. Therefore, it is desirable that the lowermost Pt layer be completely reacted with GaAs.

Further, according to the manufacturing method of the present invention, the source and drain electrodes and the gate electrode are simultaneously subjected to the heat treatment as described above, so that the ohmic alloying of the source and drain electrodes and the pinch-off voltage Vp due to the Schottky junction are obtained. Can be simultaneously controlled, and the manufacturing process of the Pt gate FET can be simplified.
Further, since only one heat treatment step is required, the source and drain electrodes once subjected to heat treatment for alloying are deteriorated during the heat treatment of the Schottky electrode, and the diffusion and reaction of the Pt layer are performed once. The Schottky electrode that has been subjected to the heat treatment is not deteriorated by the heat treatment for alloying the ohmic electrode. This makes it possible to reduce and stabilize the variation in element characteristics of the Pt gate FET, and to improve the yield.

The heat treatment temperature is 350 to 450
It is desirable to be set to ° C. The source and drain electrodes are
At a temperature lower than 350 ° C., good ohmic properties are not exhibited, and at 450 ° C. or higher, deterioration of each electrode starts.

In order to perform the heat treatment well, the thickness of the lowermost Pt layer of the gate electrode and the structure of the active layer are preferably as follows.

(Thickness of Pt Layer) Here, in order for the Pt layer to completely react with the active layer by heat treatment, the thickness of the Pt layer needs to be reduced. According to the prototype, the thickness of the Pt layer is preferably set to 500 ° or less. In particular, in the above-described embodiment, the thickness of the Pt layer is set to 2 as the optimum value.
50 degrees. As the thickness of the Pt layer increases, Pt
Not only does the heat treatment time for completely reacting the layer with the active layer become longer, but when the same pinch-off voltage is realized as the thickness of the Pt layer increases, the rising steepness of the transconductance gm also decreases, and the film thickness increases. Increases, the film stress of the Pt layer increases, and the adhesion to the GaAs substrate deteriorates.

On the other hand, if the thickness of the Pt layer is smaller than 100 °, it is difficult to control the thickness with the current technology, and Pt is not sufficiently diffused, so that a good Schottky junction cannot be obtained. Therefore, the thickness of the Pt layer is 100 °
The above is preferred. As described above, the thickness of the Pt layer is 100 to
500 ° is desirable.

(Diffusion Depth of Pt Layer) When the Pt layer is completely diffused into the active layer by heat treatment, it is important to control the pinch-off voltage Vp to a desired value. here,
When the Pt layer is diffused into the active layer by about twice the thickness of the Pt layer and the thickness of the reaction layer is about twice the thickness of the Pt layer, the reaction layer becomes thermally stable and the reliability increases. It has been experimentally found that the element characteristics are stabilized.

(Relationship between Active Layer Thickness and Pt Layer Thickness)
The thickness of the active layer before the heat treatment is determined by the Pt on the active layer.
It is preferably 2 to 10 times the thickness of the layer. Since the diffusion depth of the Pt layer is desirably about twice the thickness of the Pt layer, the thickness of the active layer should be 2 times the thickness of the Pt layer so that the entire active layer is not blocked by the reaction layer. More than twice as much. Further, when the thickness of the active layer is 10 times or more the thickness of the Pt layer, the steepness of the rise of the transconductance gm is reduced, and the characteristics of the element are deteriorated.

(Function of Mo Layer) The Mo layer functions as a diffusion barrier layer, and ensures that the Pt layer completely reacts with the active layer, and that the reaction between the other metal and the active layer. To block.

As described above, in order to fabricate a stable Pt gate FET with small manufacturing variations, the gate electrode must be connected to the active layer when the Pt layer is completely diffused into the active layer to form a reaction layer. Diffusion must be stopped to prevent metals other than Pt from diffusing into the active layer. First, since Mo does not easily react with GaAs, as shown in FIG. 4B, the Pt layer reacts with the active layer, and when the reaction layer contacts the Mo layer, the reaction between the gate electrode and the active layer occurs. Stops. In addition, since Mo acts as a diffusion barrier layer that blocks the diffusion of other metals, it prevents Ti, Au, and the like from diffusing into the active layer or the reaction layer and changing element characteristics such as the pinch-off voltage Vp. Further, in the Mo layer, the lowermost Pt is Ti
Since the diffusion into the layer is also prevented, the amount of the Pt layer diffused into the Ti layer and diffused into GaAs fluctuates, thereby preventing the depth of the reaction layer from being varied. Therefore, by forming a Mo layer having a certain thickness on the Pt layer,
Required accuracy such as process control and processing time management for completely reacting only the Pt layer with the active layer is relaxed.

This Mo layer is also formed as thin as the Pt layer, and has a thickness of 200 ° in the above embodiment. Since the Mo layer has a large film stress, when the gate length is short, the adhesion becomes worse when a thick film is formed. Therefore, the thickness of the Mo layer is reduced.

The Ti layer is for assisting the diffusion preventing effect of the thin Mo layer.
To suppress diffusion of the layer into the Pt / GaAs reaction layer,
This is essential for improving the adhesion between the Mo layer and the intermediate Pt layer.

It is to be noted that W, Ta, Cr, etc. are known as those acting as such a diffusion barrier.
Instead of the o layer, a metal such as W, Ta, or Cr may be used as the diffusion barrier layer.

(Other Metal Layers) The uppermost Au layer is a layer for reducing the resistance of the gate electrode and has the largest thickness. That is, in the above embodiment, 35
The thickness is set to 00 °. Therefore, instead of the Au layer, Al or the like having a low specific resistance may be used.

The intermediate Pt layer on the Ti layer functions as a diffusion barrier for preventing the reaction between Ti and Au. Cr may be used instead of Pt.

When the gate length is short, if a thick Mo film is deposited on the lowermost Pt layer, there is a problem of adhesion, etc., and it is difficult to deposit a thick Mo film. Then, the mutual diffusion between the Pt layer and the Ti layer cannot be prevented. Therefore, in the above gate structure, the Mo film is made very thin to facilitate the formation of the Mo film. Further, the inter-diffusion is prevented by the intermediate Pt layer and the Ti layer. It is important to improve the adhesion of the slab.

[Brief description of the drawings]

1 (a) to 1 (d) are conventional Pt gate FETs.
It is a schematic sectional drawing which shows the manufacturing process of.

2 (a) to 2 (h) show P according to an embodiment of the present invention.
FIG. 4 is a schematic cross-sectional view illustrating a manufacturing process of a t-gate FET.

FIG. 3 is a schematic enlarged sectional view showing a gate electrode formed on an active layer.

4 (a) and 4 (b) show that the Pt layer on the active layer is made of GaAs.
It is a figure which shows typically what diffuses in and alloys.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Semi-insulating GaAs substrate 13 Active layer 16 Source electrode 17 Drain electrode 22 Gate electrode 23 Reaction layer

Claims (5)

[Claims] 1. A semiconductor, wherein a Schottky electrode having at least a lowermost layer made of Pt and an ohmic electrode are formed on a semiconductor substrate, and then the Schottky electrode and the ohmic electrode are simultaneously heat-treated. Device manufacturing method. 2. The temperature of the heat treatment is 350 to 450 ° C.
The method for manufacturing a semiconductor device according to claim 1, wherein: 3. The Schottky electrode is characterized in that a Mo layer is formed on the Pt layer, a Ti layer is formed thereon, and a low-resistance metal layer is formed thereon. A method for manufacturing a semiconductor device according to claim 1. 4. The method according to claim 1, wherein, of the lowermost Pt layer, Pt in a region in contact with the active layer is completely reacted with the active layer. 5. The method according to claim 1, wherein the semiconductor substrate is a compound semiconductor substrate.