JP2002198372A - Semiconductor device and its fabrication method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To fill metal into contact holes or via holes with no voids left or no stage cut generated, which has become difficult in the conventional methods (sputtering method, CVD method) for the development of refinement/high-aspect- ratio according to the progress of refinement/densification of semiconductor device. SOLUTION: Holes of contact hole or via hole with fine and high aspect ratio are formed on a wafer. A liquid material dissolved metal-organic compound in an organic solvent having adequate wettability to a wafer surface and to the inside walls of contact holes or via holes is applied. The wafer is dried to remove the organic solvent, and burned to decompose the metal- organic compound so that only metal remains and the metal fills the holes of fine and high aspect ratio of the contact holes or via holes without generating conductivity inferiority by voids or stage cuttings.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for embedding a fine and high aspect ratio hole (via hole, contact hole, etc.) in a semiconductor device with a metal, and / or a wiring pattern. The present invention relates to a method of forming and a semiconductor device having a pattern manufactured by such a method.

[0002]

2. Description of the Related Art A semiconductor device has a multi-layered wiring layer, which is formed by repeating the following procedure in a multi-layered wiring manufacturing process.

[0003] 1) Via holes (or contact holes) are formed in an insulating film by a photoresist process.

2) A conductive material is buried in via holes (or contact holes). 3) A wiring layer is formed.

4) A wiring pattern is formed by a photoresist process. 5) An insulating film is formed. Of the above-mentioned procedures, 2) and 3) may be performed in the same step, or a series of completely different steps may be performed. Sometimes it is done.

As the former representative process, there is known a process in which hole filling and wiring layer formation are simultaneously performed with the same metal by means such as plasma sputtering. In addition, as a typical process of the latter, a hole is filled (plug formation) by CVD in a material gas atmosphere such as tungsten fluoride, and the like.
Thereafter, a wiring layer is formed by means such as sputtering.

Also, in order to bury metal in holes and grooves other than contact holes or via holes,
The procedure is performed as described above.

The above-described photoresist process is a process of forming a pattern on a base film using a resist pattern usually used in a semiconductor device manufacturing process as a mask, and applying a resist on the surface of a substrate on which a thin film is formed. After the applied resist is dried, the resist is exposed to light using a pattern formed on a photomask using an exposure device, and the exposed resist is developed.Then, the resist is used as a mask to process a thin film by, for example, etching using plasma. , Then remove the resist used as a mask,
It consists of a series of steps for cleaning the substrate surface.

[0009]

However, there is a strong demand for finer and higher-density wiring of semiconductor devices, and the design rules for semiconductor devices are in the range of 0.15 μm to 0.1 μm.
And miniaturization is progressing rapidly. Along with this, the wiring itself has been miniaturized, and the diameter of the via hole (or contact hole) has been miniaturized and the aspect ratio has been rapidly increasing. For this reason, it is becoming difficult to completely fill these fine and high aspect ratio holes with metal.

That is, in the first prior art, since the deposition rate near the via hole entrance is the highest,
The entrance of the hole is blocked by the deposited metal, voids are formed inside the via hole, and contact failures (so-called disconnection) occur due to the discontinuity with the lower wiring, resulting in a completed semiconductor device. However, there arises a problem that the device becomes defective. Attempts have been made to fill the via holes by heating the formed metal film to a high temperature and reflowing it.However, it is impossible to completely fill the inside of the fine and high aspect ratio holes as described above. Extremely difficult.

Similarly, in the second prior art, the farther from the hole entrance (the closer to the bottom of the hole), the more difficult it is to supply the CVD gas. Therefore, it takes an extremely long time, resulting in the formation of voids. As a result, disconnection may occur, making it impossible to make contact with the lower wiring, or a semiconductor device having low reliability may be completed.

The present invention solves the above-mentioned problems of the prior art,
It is an object of the present invention to provide a method of completely filling a metal into a via hole (or a contact hole) having a fine and high aspect ratio and manufacturing a semiconductor device with a high yield. Still another object of the present invention is to provide a highly reliable semiconductor device in which a metal is completely filled in a via hole (or a contact hole) having a fine and high aspect ratio.

[0013]

In order to achieve the above object, according to the present invention, a metal is filled in a via hole (or a contact hole) in a process as shown in FIG.

That is, as shown in FIG. 1, a liquid material obtained by dissolving a metal-organic compound in a solvent is applied to a wafer having via holes (or contact holes) formed therein. Here, by using a metal-organic compound dissolved in a solvent having an appropriate wettability with respect to the inner surface of the via hole, the liquid material is reduced by one capillary action.
The liquid material can be filled inside the fine holes only by supplying the liquid material once.

Next, by drying the wafer on which the liquid material is applied, the solvent of the liquid material is vaporized. Further, by firing, the metal-organic compound is thermally decomposed, and only the metal remains as a film. For this reason, the inside of the contact hole is completely filled with the metal, and an electrical connection with a conductive portion such as a lower wiring or a diffusion layer exposed at the bottom of the contact hole can be obtained.

Thereafter, the metal film formed on the wafer may be patterned by a photoresist process to form a wiring pattern. Alternatively, if necessary, the metal other than in the contact hole or via hole is removed by means of CMP (chemical mechanical polishing) or the like, and the surface of the insulating film is flattened. A wiring metal layer to be connected may be formed again, patterned by a photoresist process, and then sent to the next step.

As a method similar to the present invention, there is, for example, a method disclosed in Japanese Patent Application Laid-Open No. Hei 7-147283, which aims at flattening a non-flat substrate surface and is an object of the present invention. Contact hole aspect ratio is 1 ~
The object of the present invention is only about 1.5, and no consideration is given to filling the inside of the fine and high aspect ratio hole with which the present invention is applied.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a method for filling a fine and high aspect ratio hole with metal according to the present invention will be described in detail.

As shown in FIG. 2A, an insulating film 41 is formed on a Si wafer substrate 40 by a CVD method, and a fine and high aspect ratio hole 42 is formed by a reactive ion etching method.
And a groove (not shown) is used as a sample. A liquid material 43 is dropped on the surface of the sample as shown in FIG.

The liquid material 43 used here is a red-brown liquid obtained by dissolving palladium trifluoroacetate in a mixture of acetonitrile and NMP (N-methyl-2-pyrrolidone).

After the dropping, excess liquid material is removed if necessary, and drying is performed on a hot plate at 80 ° C. for 10 minutes. Thereafter, the resultant was continuously fired at 250 ° C. for 30 minutes in the air. By this drying and baking, the liquid material 43 film is removed from the liquid
As shown in (c), a palladium film 44 was formed.
A section including the via-hole section is cut out as a thin piece having a thickness of 0.1 μm or less from the sample by a FIB (focused ion beam) processing apparatus, and the TEM (transmission electron microscope) is used.
Was observed.

As a result, the hole 42 having an entrance diameter of 0.15 μm, a hole bottom diameter of 0.1 μm, and a depth of 0.9 μm (aspect ratio:
It was confirmed that 6) was completely filled with palladium. The entrance diameter is 0.2 μm, the hole bottom diameter is 0.15 μm,
It was also confirmed that the hole 42 having a depth of 0.9 μm (aspect ratio 4.5) was completely filled with palladium.

Further, the entrance width is 0.25 μm and the bottom width is 0.0
It was confirmed that the groove having a depth of 75 μm and a depth of 0.75 μm was completely filled with palladium.

The liquid material 43 used here was applied to a flat portion where no holes or grooves were formed, and the specific resistance of the palladium film 44 obtained by drying and firing was measured. 2 in the atmosphere
The specific resistance of the film fired at 50 ° C. for 30 minutes is 100 to 300.
μΩ · cm. When fired in air at a temperature exceeding 300 ° C., the metal palladium was oxidized, and the specific resistance increased rapidly.

On the other hand, when firing in a nitrogen atmosphere,
00 ° C, 50-80 μΩcm for 30 minutes, 400 ° C,
After 30 minutes, a specific resistance of 30 to 40 μΩ · cm was obtained. Even when the temperature was increased to 600 ° C., the specific resistance did not increase.

The film thickness of the liquid material 43 is reduced to about 1/10 by drying and firing, but no voids are found in the holes 42. This is because the thermal decomposition of the liquid material during firing causes volume contraction of the liquid material, but the thermal decomposition occurs from the part in contact with the insulating film or metal film, and the liquid material that remains fluid even if the volume decreases occurs is supplied. It is considered that voids do not occur to compensate for the decrease in volume by being performed.

The obtained palladium film 44 is coated with AES and E
Analysis by SCA showed that the constituent atoms of palladium trifluoroacetate, carbon and fluorine, were below the detection limit. Oxygen was detected from the palladium film 44 when fired in the air, but was below the detection limit when fired in a nitrogen atmosphere.

Next, the case where the filling of a fine hole or a fine groove with a metal film according to the present invention is applied to a method of manufacturing a semiconductor device will be described in detail with reference to the drawings.

[Embodiment 1] FIG. 3 shows a manufacturing process when applied to the manufacture of a CMOS semiconductor device according to an embodiment of the present invention.

FIG. 3A shows a cross section of the CMOS semiconductor device during its manufacture. That is, after an n-well region 2 and a p-well region 3 are formed on a Si substrate 1 and a field oxide film 4 and gate oxide films 5 and 6 for element isolation are formed, polycrystalline Si gate electrodes 7 and 8 are formed. Are formed, and source-drain diffusion layers 9, 10, 11, and 12 are formed using polycrystalline Si gate electrode 6 as a mask.
An S transistor is formed. An insulating film (BPSG or PSG film) 15 is formed on these transistors, and contact holes 16, 17, 18, and 19 for taking out electrodes are formed by a reactive ion etching technique using a photoresist process. .

The contact holes 16, 17, 18,
The size of 19 has a hole diameter of 0.25 to 0.15 μm and a depth of 0.5 to 1 μm.

The contact holes 16, 17, 1 are formed on the wafer by a usual sputtering technique as necessary.
A barrier layer (not shown) of Ti or the like is formed in 8 and 19.

Thereafter, as shown in FIG. 3B, a liquid material 2 in which a metal-organic compound is dissolved in a solvent is placed on the wafer.
0 is applied. This liquid material 20 has an appropriate wettability with respect to the interlayer insulating film 15 or the barrier layer formed by sputtering, and voids are left in the fine contact holes 16, 17, 18, and 19 due to the capillary phenomenon. Without being completely filled. Further, a liquid material 20 film is also formed on the insulating film 15.

Here, a case will be described in which palladium trifluoroacetate is dissolved in a mixture of acetonitrile and N-methyl-2-pyrrolidone (hereinafter referred to as NMP) as the liquid material 20. However, the present invention is not limited to this.
An organometallic compound dissolved in a solvent having an appropriate wettability with respect to a material such as SG, SiO2, or SiN can be used, and is limited by the material of the metal finally formed. Considering that it is dissolved in an organic solvent and thermally decomposed at the time of firing, metals other than palladium are metals that are hardly oxidized by heating, that is, Au, Pt,
It is desirable to use either a noble metal such as Ag or an alloy mainly containing them. However, if firing is performed in a vacuum atmosphere, an inert gas atmosphere, or a reducing gas atmosphere, it is not necessary to use a noble metal, and the selection range of materials is widened.

After applying the liquid material 20, the wafer is heated and dried. This is a step for vaporizing and removing the solvent, and is not necessarily performed in an independent process, but may be performed continuously in the next firing step.

Next, the dried wafer is fired by means such as an electric furnace or a hot plate. Note that, as described above, drying may be performed at the initial stage of firing, followed by firing. Palladium trifluoroacetate is 25
0-300 ° C, 300-500 ° C if in inert gas
By heating at a temperature of 1 to 30 minutes, a palladium film 21 is formed as shown in FIG. Naturally, firing in an inert gas atmosphere has a smaller specific resistance and is suitable when low-resistance wiring is required. This palladium film 21
Is formed on the surface of the insulating film 15 in addition to the inside of the contact holes 16, 17, 18, and 19, and is patterned by a photoresist process to form the first layer as shown in FIG. It can be used as the wirings 22, 23, 24, 25. Alternatively, since metal can be easily removed by a chemical etching means or CMP (chemical mechanical polishing), as shown in FIG. 3 (e), metal is deposited only in the contact holes 16, 17, 18, and 19. Leave the contacts 26, 27, 28, 29
And a first wiring layer may be formed thereon by ordinary sputtering or the like, and may be patterned by a photoresist process. In this case, contact 2
6, 27, 28 and 29 and the material of the first layer wiring are different, but there is no problem.

According to this method, the contact hole which is most susceptible to the miniaturization and high-density of the semiconductor device can be completely filled with the metal without generating voids or disconnections.

[Embodiment 2] Another embodiment of the semiconductor manufacturing method according to the present invention will be described in detail.

FIG. 4 shows a manufacturing process in a method of manufacturing a CMOS semiconductor device according to one embodiment of the present invention. The semiconductor devices in the figures are shown in cross-sectional views.

In FIG. 4A, after an n-well region 2 and a p-well region 3 are formed in a Si substrate 1, a field oxide film 4 and gate oxide films 5 and 6 for element isolation are formed. Polycrystalline Si gate electrodes 7, 8 are formed, and source-drain diffusion layers 9, 10, 11, 12 are formed using polycrystalline Si gate electrodes 7, 8 as a mask, thereby forming a CMOS transistor. An insulating film (BPSG or PSG film) 15 is formed on these transistors,
Contact holes 16, 17, 18, and 19 for taking out electrodes are formed by the reactive ion etching technique.
Thereafter, a metal such as Al is deposited in the contact holes 16, 17, 18, and 19 by a sputtering method and a wiring metal film is formed on the surface of the insulating film 15, and the wiring of the first layer is formed by a photoresist process. Patterns are formed, and an interlayer insulating film 30 is formed on the entire surface.

Next, as shown in FIG. 4B, via holes 31 and 32 for making connections between wiring layers formed in multiple layers are formed in the interlayer insulating film 30 by reactive ion etching or the like. . The via holes 31 and 32 have been miniaturized year by year with the miniaturization of the design rules of semiconductor devices, and the most advanced devices have emerged to have a diameter of 0.15 μm, a depth of 2.5 μm, and an aspect ratio exceeding 16. It is clear that further miniaturization and higher aspect ratio will progress. It is extremely difficult to fill such fine and high-aspect via holes with a conventional technique such as sputtering or CVD without generating voids or disconnections.

In the present invention, as shown in FIG. 4C, a liquid material 35 in which a metal-organic compound is dissolved in a solvent is applied onto the wafer. This liquid material 35 is used for the interlayer insulating film 30.
It has an appropriate wettability with respect to, and is completely filled without leaving voids in the fine via holes 31 and 32 by capillary action. Also, a liquid material 35 film is formed on the insulating film 30.

Here, a case will be described where palladium trifluoroacetate is dissolved in a mixture of acetonitrile and N-methyl-2-pyrrolidone (hereinafter referred to as NMP) as the liquid material. However, the present invention is not limited to this.
It is possible to apply an organometallic compound dissolved in a solvent having an appropriate wettability with respect to such a material, and the material is limited by the material of the finally formed metal. Considering that it is dissolved in an organic solvent and thermally decomposed at the time of firing, the metal other than palladium is a metal which is hardly oxidized by heating at the time of firing, that is, a precious metal such as Au, Pt, Ag or the like. Alloys are preferred. However, if firing is performed in a vacuum atmosphere, an inert gas atmosphere, or a reducing gas atmosphere, it is not necessary to use a noble metal, and the selection range of materials is widened.

After applying the liquid material 35, the wafer is heated and dried. This is a step for vaporizing and removing the solvent, and is not necessarily performed in an independent process, but may be performed continuously in the next firing step.

Next, the dried wafer is fired by means such as an electric furnace or a hot plate. Note that, as described above, drying may be performed at the initial stage of firing, followed by firing. Palladium trifluoroacetate is 25
0 to 300 ° C, 300 to 450 ° C if in an inert gas
By heating at a temperature of 1 to 30 minutes, a palladium film 36 is formed. Naturally, firing in an inert gas atmosphere has a lower specific resistance and is suitable when low-resistance wiring is required. This palladium film 36 is used for the via holes 31 and 3.
Although formed on the surface of the insulating film 30 in addition to the inside, it can be easily removed by chemical etching or CMP (chemical mechanical polishing). FIG. 4D shows CMP.
2 shows a cross section after the palladium film on the insulating film is removed and the surface of the insulating film 30 is flattened. After the palladium film on the surface of the insulating film 30 is removed, only the via holes 31 and 32 are left in a state where the palladium film is filled.

Next, as shown in FIG. 4E, a metal thin film 37 for forming wiring is formed on the wafer by a method such as sputtering. As materials, Al, C
It is selected from metals such as u, Mo, W, and Ti, or alloys containing these as main components.

After the film formation, the wiring patterns 38, 3 are formed by a normal photoresist process, as shown in FIG.
9 is formed and sent to the next step.

When a wiring layer is further formed, the above-mentioned steps are repeated as necessary in the next step. From the viewpoint of the diameter and the aspect ratio of the via hole, when the hole can be formed by the conventional method, the hole may be formed by the conventional method.

According to the above method, metal can be completely filled in a fine and high aspect ratio via hole, which has been difficult to completely fill by the conventional sputtering and CVD techniques, and a semiconductor device can be manufactured at a high yield. Can be manufactured.

Embodiment 3 Next, another embodiment of the method for manufacturing a semiconductor device according to the present invention will be described. FIG.
(A) shows a cross section of a bipolar LSI during a manufacturing process. In FIG. 5A, n is placed on a p-type Si substrate 101.
A diffusion layer (collector buried layer) 102 is formed, and oxide films (commonly called LOCOS) 103, 104,
After the formation of 105, the collector extraction region 106, the base region 107, and the emitter region 108 are respectively diffused into the collector region, the base region, and the emitter region by impurity diffusion.
Is formed. Thereafter, an insulating film 109 is deposited on the entire surface, an electrode lead-out portion is selectively opened, and a metal wiring layer connected to each of the electrode lead-out portions 110, 111, 112 is patterned. Here, as the metal wiring, a metal such as Al, W, Mo, or Cu, or a silicide such as Mo or W is used via a barrier layer such as Ti. An interlayer insulating film 113 for forming a second wiring layer is formed thereon.

As shown in FIG. 5B, the interlayer insulating film 11
In 3, via holes 115, 116, 117 for making connections between wiring layers formed in multiple layers are formed by reactive ion etching or the like. Via holes have been miniaturized year by year with the miniaturization of design rules for semiconductor devices, and the most advanced devices have a diameter of 0.15 μm and a depth of 2.
Even those with a size of 5 μm and an aspect ratio of more than 16 have appeared, and it is obvious that further miniaturization and higher aspect ratio will be further advanced. It is extremely difficult to fill such fine and high-aspect via holes with a conventional technique such as sputtering or CVD without generating voids or disconnections.

In the present invention, as shown in FIG. 5C, a liquid material 118 obtained by dissolving a metal-organic compound in a solvent is applied to the wafer. This liquid 118 contains the interlayer insulating film 113.
And has a sufficient wettability with respect to water, and is completely filled by the capillary phenomenon without leaving voids in fine via holes. Further, a liquid material 118 film is also formed on the insulating film 113.

Here, a case will be described in which palladium trifluoroacetate is dissolved as a liquid material in a mixture of acetonitrile and N-methyl-2-pyrrolidone (hereinafter referred to as NMP). However, the present invention is not limited to this.
An organometallic compound dissolved in a solvent having an appropriate wettability with respect to a material such as N can be used, and is limited by the properties of the metal finally formed. Considering that it is dissolved in an organic solvent and thermally decomposed at the time of firing, the metal other than palladium is a metal which is hardly oxidized by heating at the time of firing, that is, a precious metal such as Au, Pt, Ag or the like. Alloys are preferred. However, if firing is performed in a vacuum atmosphere, an inert gas atmosphere, or a reducing gas atmosphere, it is not necessary to use a noble metal, and the selection range of materials is widened.

Next, the wafer coated with the liquid material 118 is dried by heating. This is a step for evaporating the solvent, and is not necessarily performed in an independent process, and may be performed continuously in the next baking step.

Next, the dried wafer is fired by means such as an electric furnace or a hot plate. Note that, as described above, drying may be performed at the initial stage of firing, followed by firing. Palladium trifluoroacetate is 25
0 to 300 ° C, 300 to 450 ° C if in an inert gas
By heating at a temperature of 1 to 30 minutes, a palladium film is formed. Although this palladium film is formed not only in the via hole but also on the surface of the insulating film 113, it can be easily removed by etching or CMP (chemical mechanical polishing). FIG. 5D shows that the palladium film on the insulating film is removed by CMP and the insulating film 113 is removed.
The cross section after the surface is flattened is shown. After the palladium film on the surface of the insulating film 113 has been removed, the palladium 11 only remains inside the via holes 115 to 117.
9, 120 and 121 are left in a filled state.

Next, as shown in FIG. 5E, a metal thin film 124 serving as a wiring material is formed on the wafer by a sputtering method. As materials, Al, Cu, Mo,
It is selected from alloys containing W and Ti as main components.

After the film formation, the wiring patterns 126 and 1 are formed by a normal photoresist process as shown in FIG.
27 and 128 are formed and flowed to the next step.

When a wiring layer is further formed, the above-described steps are repeated as necessary in the next step. From the viewpoint of the diameter and the aspect ratio of the via hole, if it can be formed by the conventional method, it may be formed by the conventional method.

According to the above method, the metal can be completely filled in the fine and high aspect ratio via hole, which is difficult to fill by the conventional sputtering or CVD technique, and the space between the upper and lower wiring layers can be reliably formed. This makes it possible to improve the reliability of connection between wirings as compared with the conventional method, and to manufacture a semiconductor device with a high yield.

Embodiment 4 Next, another embodiment of the present invention will be described with reference to the drawings.

FIG. 6A is a cross-sectional view of a CMOS semiconductor device in the middle of a manufacturing process, similarly to FIG. 3A. However, the interlayer insulating film 51 is formed thicker by the thickness of the wiring layer, and is planarized by CMP to eliminate surface irregularities. Other parts are the same as those in FIG.

As shown in FIG. 6B, via holes 52 and 53 and grooves 54 and 55 for embedding wiring patterns are formed in the interlayer insulating film 51 by reactive ion etching using a photoresist process or the like. Is done.

Next, as shown in FIG. 6C, a liquid material 56 obtained by dissolving a metal-organic compound in a solvent is placed on the wafer.
Is applied. The liquid 56 has an appropriate wettability with respect to the interlayer insulating film 51, and is formed in the fine via holes 52 and 53 and the wiring embedding groove 5 by capillary action.
4, 55 are completely filled without leaving voids. Also, a liquid material 56 film is formed on the insulating film 51.

Here, a case will be described in which palladium trifluoroacetate is dissolved in a mixture of acetonitrile and N-methyl-2-pyrrolidone (hereinafter referred to as NMP) as the liquid material. However, the present invention is not limited to this.
It is possible to apply an organometallic compound dissolved in a solvent having an appropriate wettability for such a material as described above, and is limited by the properties of the finally formed metal.

Next, the wafer coated with the liquid material 56 is heated and dried. This is a process to evaporate the solvent,
It is not always necessary to carry out the treatment in an independent manner, and the treatment may be carried out continuously in the next firing step.

Next, the dried wafer is fired by means such as an electric furnace or a hot plate. Note that, as described above, drying may be performed at the initial stage of firing, followed by firing. Palladium trifluoroacetate is 25
0 to 300 ° C, 300 to 450 ° C if in an inert gas
By heating at a temperature of 1 to 30 minutes, a palladium film can be formed. This palladium membrane is
2 and 53, and the grooves 54 and 55,
Etching or CMP is also formed on the surface
(Chemical-mechanical polishing). FIG. 6D shows a cross section after the palladium film on the insulating film is removed by CMP and the surface of the insulating film 113 is flattened. After the palladium film on the surface of the insulating film 51 is removed, the via holes 52 and 53 are removed.
And only the grooves 54 and 55 are left filled with palladium 57, 58 and 59, 60. This allows
The filling of the via hole and the formation of the wiring pattern can be performed simultaneously. Embodiment 5 Next, another embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

FIG. 7A shows a cross section of a trench capacitor used in a DRAM during a manufacturing process. A lower electrode 203 of polysilicon or metal is formed on the inner surface of a hole 202 formed in the insulating film 201 by means such as reactive ion etching, and a dielectric film 204 is further formed on the lower electrode 203. At this stage, the trench hole diameter is 0.1 to 0.2 μm and the depth is about 2 μm.
Here, as shown in FIG. 7B, a liquid material 205 in which a metal-organic compound is dissolved in a solvent is applied. This liquid 20
5 has an appropriate wettability with respect to the dielectric film 204, and is completely filled without leaving a void in the fine trench hole 202 by a capillary phenomenon. Further, a liquid material 205 film is also formed on the insulating film 201.

Here, a case will be described where palladium trifluoroacetate is dissolved in a mixture of acetonitrile and N-methyl-2-pyrrolidone (hereinafter referred to as NMP) as the liquid material 205. However, the present invention is not limited to this, and an organic metal compound dissolved in a solvent having an appropriate wettability to the insulating film 202 such as SiO 2 or SiN and the dielectric film 204 can be applied. And the nature of the metal ultimately formed. Considering that it is dissolved in an organic solvent and thermally decomposed during firing, metals other than palladium include
Metals that are not easily oxidized by heating during firing, ie, Au, P
Precious metals such as t and Ag or alloys mainly containing them are desirable. However, if firing is performed in a vacuum atmosphere, an inert gas atmosphere, or a reducing gas atmosphere, it is not necessary to use a noble metal, and the selection range of materials is widened.

Next, the wafer coated with the liquid material 205 is dried by heating. This is a step for evaporating the solvent, and is not necessarily performed in an independent process, and may be performed continuously in the next baking step.

Next, the dried wafer is fired by means such as an electric furnace or a hot plate. Note that, as described above, drying may be performed at the initial stage of firing, followed by firing. Palladium trifluoroacetate is 25
0 to 300 ° C, 300 to 450 ° C if in an inert gas
By heating at a temperature of 1 to 30 minutes, a palladium film can be formed. The palladium film is formed not only inside the trench hole 202 but also on the surface of the insulating film 201. The palladium film formed on the surface of the insulating film 201 is easily removed by etching or CMP (chemical mechanical polishing). can do. If necessary, the palladium film formed on the insulating film 201 can be patterned by a photoresist process and used as an electrode.

As described above, the trench can be completely filled without generating a void or the like in a trench having a fine deep hole, which is one of the components of the DRAM. Also, insulating film 2
Since the metal film formed on the substrate 01 can also be used as an electrode if necessary, the number of manufacturing steps can be reduced.

Embodiment 6 Next, another embodiment of the present invention will be described with reference to FIG. FIG. 8A is a cross-sectional view showing a part of a MOS transistor in the course of manufacture. Diffusion layers 211 and 212 are formed on a Si substrate 210, and a groove 214 for forming a metal gate is formed in the SiO2 film 213 formed thereon. This groove has a width of 0.06 μm and a depth of 0.5 μm as the pattern becomes finer.
At the bottom of the groove 214, a SiO2 film (not shown) of about 0.01 μm is formed. Here, as shown in FIG. 8B, a liquid material 215 in which a metal-organic compound is dissolved in a solvent is applied. This liquid 215 is a SiO 2 film 213
, And is completely filled without leaving voids in the fine grooves 214 due to capillary action. Further, a liquid material 215 film is also formed on the SiO 2 film 213.

Here, a case will be described where palladium trifluoroacetate is dissolved in a mixture of acetonitrile and N-methyl-2-pyrrolidone (hereinafter referred to as NMP) as the liquid material 215. However, the present invention is not limited to this, and it is possible to apply an organometallic compound dissolved in a solvent having appropriate wettability to the SiO2 film 213, and is limited by the properties of the finally formed metal. . Considering that it is dissolved in an organic solvent and thermally decomposed during firing, metals other than palladium are metals that are not easily oxidized by heating during firing, that is, Au, Pt, and A.
Precious metals such as g or alloys mainly containing them are desirable. However, if firing is performed in a vacuum atmosphere, an inert gas atmosphere, or a reducing gas atmosphere, it is not necessary to use a noble metal, and the selection range of materials is widened.

Next, the wafer coated with the liquid material 215 is heated and dried. This is a step for evaporating the solvent, and is not necessarily performed in an independent process, and may be performed continuously in the next baking step. Next, the dried wafer is fired by means such as an electric furnace or a hot plate. Note that, as described above, drying may be performed at the initial stage of firing, followed by firing. Palladium trifluoroacetate can form a palladium film by heating at a temperature of 250 to 300 ° C. in the air and 300 to 450 ° C. in an inert gas for 1 to 30 minutes. This palladium film is formed in the groove 214 and also on the surface of the SiO2 film 213, but can be easily removed by means such as etching or CMP (chemical mechanical polishing). As a result, as shown in FIG. 8C, only the trench 214 is filled with the metal palladium 216, and the metal gate forming step is completed.

[0075]

As described above, according to the present invention, a metal material is dissolved in a solvent having good wettability to a sample in a sample in which a deep hole having a fine diameter or a deep groove having a fine width is formed on the surface. The molten metal material is sufficiently supplied to the bottom of the deep hole or the deep groove by supplying in the step, and the metal is deposited in the deep hole or the deep groove by heating the sample to remove the solvent. It has become possible to fill the inside of the deep hole or groove with a sufficient amount of metal for practical use.

That is, according to the present invention, by applying a liquid material for forming a metal film on a wafer having a fine deep hole formed therein, a capillary phenomenon caused by wettability of the liquid material to the wafer is obtained. The fine deep hole is filled with a liquid material, and the liquid material is dried and thermally decomposed, so that the fine deep hole can be filled with a metal. In other words, since the holes can be completely filled without generating voids or the like in fine or high aspect ratio holes or grooves that are difficult to fill by conventional metal film forming means such as sputtering and CVD, semiconductors can be produced at a high yield. Devices can be manufactured.

Further, according to the present invention, the metal can be completely filled by the above-mentioned method without causing voids or breaks in the fine deep hole, so that a highly reliable semiconductor device can be obtained.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing the steps of the method of the present invention.

FIG. 2 is a cross-sectional view of a sample in which a deep hole is formed for explaining the method of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor device for explaining steps of the method of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor device illustrating a process which is another embodiment of the method of the present invention.

FIG. 5 is a cross-sectional view of a semiconductor device illustrating a manufacturing process which is another embodiment of the method of the present invention.

FIG. 6 is a cross-sectional view of a semiconductor device illustrating a manufacturing process which is another embodiment of the method of the present invention.

FIG. 7 is a cross-sectional view of a trench capacitor for explaining a manufacturing process which is another embodiment of the method of the present invention.

FIG. 8 is a cross-sectional view of a metal gate transistor for explaining a manufacturing process which is another embodiment of the method of the present invention.

[Explanation of symbols]

1... Si substrate, 2... N-well region, 3
..... p-well region, 4 ... field oxide film, 5, 6, .... gate oxide film, 7, 8, ....
Gate electrode, 15,... Insulating film, 16, 17, 1
8, 19 contact hole, 20 liquid material, 21 metal film formed from liquid material,
31, 32, 52, 53 ... Via hole,
54, 55: wiring groove 101: Si substrate 102: collector burying layer 103: 1
04, 105... Oxide film, 115, 116, 11
7 via holes, 118 liquid materials, 119, 120, 121 filled palladium, 126, 127, 128 wiring patterns,
201: an insulating film; 204: a dielectric film;
205: liquid material 211, 212: diffusion layer, 216: metal gate

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Katsuro Mizukoshi 5-20-1, Kamimizuhoncho, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Group 4M104 AA01 BB02 BB04 BB14 BB16 BB18 CC01 DD08 DD16 DD17 DD19 DD37 DD51 DD63 DD75 DD78 FF13 FF17 FF18 FF22 GG09 GG10 GG14 GG15 HH13 HH14 HH20 5F033 HH07 HH08 HH09 HH11 HH12 HH13 HH14 HH18 HH19 HH20 HH28 HH29 KK18 JJ18 JJ18 JJ18 JJ18 JJ18 JJ18 JJ18 JJ18 JJ18 JJ18 JJ18 JJ18 JJ08 MM05 MM13 NN06 NN07 PP15 PP26 QQ08 QQ09 QQ13 QQ37 QQ48 QQ73 RR04 RR06 RR14 RR15 SS11 WW00 WW01 XX00 XX02 XX03 XX04

Claims (31)

[Claims] 1. A method of manufacturing a semiconductor device, comprising: forming an insulating film on a surface of a substrate on which a wiring pattern is formed, wherein the insulating film has a diameter of 0.2 μm or less, an aspect ratio of 4 or more, and Forming a pattern including fine holes exposing a part of the pattern, applying an organometallic complex solution obtained by dissolving an organometallic complex in a solution on a substrate on which the pattern including the fine holes is formed, Heating the substrate to which the is applied to evaporate the solvent of the organometallic complex solution, thereby removing the solvent and leaving the metal electrically connected to the wiring pattern inside the fine holes of the substrate. Manufacturing method of a semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1, wherein a pattern for connecting to the metal remaining inside said fine hole is formed on said insulating film. 3. The method of manufacturing a semiconductor device according to claim 2, wherein a pattern for connecting to the metal remaining inside said fine hole is formed by sputtering. 4. A pattern formed on the insulating film is electrically connected to a wiring pattern covered with the insulating film via a metal remaining inside the fine hole. A method for manufacturing a semiconductor device according to claim 2. 5. A pattern for processing the surface of the insulating film after the metal is left inside the fine hole, and connecting to the metal remaining inside the fine hole on the insulating film having the processed surface. 3. The method of manufacturing a semiconductor device according to claim 2, wherein 6. A method for manufacturing a semiconductor device, comprising: forming a wiring pattern on a substrate by a photoresist process; forming an insulating film on a surface of the substrate on which the wiring pattern has been formed; Forming a pattern including fine holes exposing a part of the wiring pattern on the bottom surface with an aspect ratio of 4 or less at 2 μm or less and dissolving an organometallic complex in a solution on a substrate on which the pattern including the fine holes is formed Coating the organometallic complex solution, heating the substrate to which the organometallic complex solution has been applied, and evaporating the solvent of the organometallic complex solution to remove the solvent, including the inside of the fine holes of the substrate. A method of manufacturing a semiconductor device, comprising: leaving a metal film on a surface of a substrate; removing the metal film remaining on the surface of the substrate while leaving the metal film remaining inside the fine holes of the substrate. Method. 7. A wiring pattern electrically connected to the wiring pattern covered with the insulating film via a metal remaining in the fine hole is formed on the insulating film. 7. The method for manufacturing a semiconductor device according to item 6. 8. A process for removing the metal film remaining on the surface of the substrate while leaving the metal film remaining inside the fine holes of the substrate is a process for flattening the surface of the substrate. The method for manufacturing a semiconductor device according to claim 6, wherein 9. A wiring pattern is formed on a substrate by a photoresist process, an insulating film is formed on the surface of the substrate on which the wiring pattern has been formed, and the insulating film has a diameter of 0.2 μm or less and the wiring pattern is formed on the bottom surface. A fine hole exposing a part of the organic metal complex is formed by a photoresist process, a solution of an organometallic complex is applied on a substrate on which the fine hole is formed, and a solvent of the organometallic complex solution applied to the substrate is evaporated. Forming a metal film electrically connected to the wiring pattern inside the fine hole of the substrate. 10. A metal film formed inside said fine hole,
10. The method according to claim 9, wherein the material is one of gold, platinum, palladium, silver, and an alloy mainly containing any of these.
The manufacturing method of the semiconductor device described in the above. 11. The method according to claim 9, further comprising the step of forming a wiring pattern electrically connected to the metal film formed inside the fine hole of the substrate on the insulating film by a photoresist process. Semiconductor device manufacturing method. 12. After forming a metal film inside the fine holes of the substrate, processing the surface of the insulating film, and forming the metal film inside the fine holes of the substrate on the surface of the processed insulating film. 10. The method for manufacturing a semiconductor device according to claim 9, wherein a wiring pattern electrically connected to the film is formed by a photoresist process. 13. The method for manufacturing a semiconductor device according to claim 9, wherein the step of vaporizing the solvent of the solution containing the metal component is performed by heating the substrate. 14. The method according to claim 13, wherein the heating of the substrate is performed in a vacuum atmosphere, an inert gas atmosphere, or a reducing gas atmosphere. 15. After forming a fine hole in the insulating film, a metal film is formed on the inner wall surface of the fine hole, and the wiring pattern is electrically connected to the inside of the fine hole having the metal film formed on the inner wall surface. The metal film to be connected is formed.
The manufacturing method of the semiconductor device described in the above. 16. A wiring pattern is formed on a substrate by a photoresist process, an insulating film is formed on the surface of the substrate on which the wiring pattern has been formed, and fine holes are formed in the insulating film by a photoresist process. Gold, platinum, palladium electrically connected to the wiring pattern inside the hole,
Silver, or any one of these alloys is mainly formed, and gold, platinum, palladium, silver, or an alloy mainly containing any of these is formed inside the fine hole on the insulating film. Forming a wiring pattern electrically connected to any one of the above. 17. The wiring pattern formed on the insulating film may be formed by forming gold, platinum, palladium, silver, or an alloy mainly containing any of these inside the fine hole. 17. The method for manufacturing a semiconductor device according to claim 16, wherein the surface is processed and the surface is formed on the processed insulating film. 18. A deep groove pattern or a deep hole pattern is formed in an insulating film formed on a substrate, the deep groove pattern or the deep hole pattern is formed by a photoresist process, and the inside of the formed deep groove pattern or the deep hole pattern is formed. Money,
A method for manufacturing a semiconductor device, comprising forming one of platinum, palladium, silver, and an alloy mainly containing any of these. 19. The deep groove pattern or gold, platinum, palladium, silver, or an alloy mainly containing any of these, formed inside the deep groove pattern, is formed on the insulating film on which the deep groove pattern is formed. Gold, platinum, palladium, silver,
Alternatively, a solution containing any of these alloys is applied, and the substrate is heated to evaporate the solvent of the solution and pyrolyze gold, platinum, palladium, silver,
19. The method for manufacturing a semiconductor device according to claim 18, wherein any one of alloys mainly including any of these is formed. 20. The method according to claim 18, wherein the deep groove pattern or the deep hole pattern is a capacitor of a memory part of the semiconductor device. 21. The method according to claim 18, wherein the deep groove pattern or the deep hole pattern is a gate electrode of a transistor portion of the semiconductor device. 22. A semiconductor device comprising: a first wiring pattern layer; an insulating film layer formed on the first wiring pattern layer; and a second wiring pattern layer formed on the insulating film layer. In the semiconductor device, the insulating film layer has a hole pattern filled therein with a metal film formed by thermal decomposition of an organometallic complex, and the metal film filled in the hole pattern forms the hole pattern. A semiconductor device, wherein the first wiring pattern layer and the second wiring pattern layer are electrically connected. 23. A semiconductor device in which a plurality of wiring pattern layers are formed with an insulating film interposed therebetween, wherein the insulating film has a hole pattern, and is formed by being supplied in liquid form inside the hole pattern. A semiconductor device, wherein a metal film is filled, and wiring patterns above and below the insulating film are electrically connected by the metal film filled inside the hole pattern. 24. A semiconductor device having a plurality of wiring pattern layers formed with an insulating film interposed therebetween, wherein said insulating film has a hole pattern having a diameter of 0.2 μm or less and an aspect ratio larger than 4. The inside of the pattern is filled with a metal film that is supplied in a liquid state and formed by a thermal decomposition reaction, and the metal film filled inside the hole pattern electrically connects wiring patterns above and below the insulating film. A semiconductor device, which is connected to a semiconductor device. 25. A metal film of a material different from the filled metal film is formed between an inner wall surface of the hole pattern and a metal film filled inside the hole pattern. The semiconductor device according to any one of claims 22 to 24, wherein 26. The metal film filled in the hole pattern,
25. The semiconductor device according to claim 22, wherein the semiconductor device is formed of a material different from a material of the wiring pattern layer. 27. A semiconductor device in which a plurality of wiring pattern layers are formed with an insulating film interposed therebetween, wherein the insulating film has a hole pattern, and gold, platinum, palladium, silver, or Any one of these alloys is formed, and the gold, platinum, palladium, silver, or any one of these alloys is used to fill the hole pattern. A semiconductor device, wherein wiring patterns above and below the insulating film are electrically connected. 28. Gold formed inside said hole pattern,
28. The method according to claim 27, wherein any one of platinum, palladium, silver, and an alloy mainly containing any of them is supplied in a solution state and is formed by a thermal decomposition reaction. Semiconductor device. 29. A semiconductor device comprising a plurality of wiring pattern layers formed with an insulating film interposed therebetween, a capacitor, and a transistor, wherein the capacitor has a deep groove or deep hole structure. Wherein gold, platinum, palladium, silver, or an alloy mainly containing any of these is formed inside the semiconductor device. 30. A semiconductor device comprising a plurality of wiring pattern layers formed with an insulating film interposed therebetween, a capacitor, and a transistor, wherein the gate electrode of the transistor has a deep groove or deep hole structure. Or inside the deep hole,
A semiconductor device comprising one of gold, platinum, palladium, silver, and an alloy mainly containing any of them. 31. Gold, platinum, palladium, silver, or an alloy mainly containing any of these, formed inside the deep groove or the deep hole, is supplied in a solution state, and is formed by a thermal decomposition reaction. 30. The method of claim 29, wherein
Or a semiconductor device described in 30.