JPH1116912A - Manufacture of semiconductor integrated circuit device and manufacture device of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce contact resistance in the connection hole parts of a semiconductor integrated circuit device having wirings, in which Cu and the like are set to be main conduction layers. SOLUTION: Silicon films are deposited on the wirings 14, where copper is set to be main conduction layers 14a by a sputtering method or a CVD method, and an interlayer insulating film 16 is formed. Connection holes 17 are opened to the interlayer insulating film 16 is prescribed positions by using photographic technology. Oxide layers 23 are formed at the bases of the connection holes 17 after the connection holes 17 are opened by ashing for removing a resist mask used for photolithography or the exposure of atmosphere after the connection holes 17 are opened. Then, the oxide layers 23 are changed into copper by thermal treatment or plasma treatment or the irradiation of ultraviolet rays under a reducing atmosphere of hydrogen or ammonia, so as to dissolve it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device manufacturing technique and a semiconductor integrated circuit device.
The present invention relates to a technique effective when applied to a semiconductor integrated circuit device having a wiring having copper as a main conductive layer.

[0002]

2. Description of the Related Art Conventionally, wiring layers in a semiconductor integrated circuit are formed, for example, on November 30, 1984, by Ohm Co., Ltd., "LSI Handbook", p.
292, a high-melting-point metal thin film such as an aluminum (Al) alloy or tungsten (W) is formed on an insulating film, and a photolithography process is used to form a thin film having the same shape as the wiring pattern on the wiring thin film. A resist pattern is formed, and a wiring pattern is formed by a dry etching process using the resist pattern as a mask.

However, in the method using the Al alloy, there is a problem that the wiring resistance is remarkably increased as the wiring is miniaturized, the wiring delay is increased, and the performance of the semiconductor integrated circuit device is reduced. . Especially high performance logic LS
In the case of I, a great problem has arisen as a performance hindrance factor.

For this reason, recently, 1993 VMIC
(VLSI Multilevel Interconnection Conference) As described in the Proceedings, pp. 15-21, after burying the wiring metal with Cu as the main conductor layer on the groove formed in the insulating film, the extra metal outside the groove is chemically Mechanical polishing method (CM
A method of forming a wiring pattern in a groove by removing the wiring pattern using the P method has been studied.

Also, in 1995 VMIC (VLSI Multile
vel Interconnection Conference) Proceedings, p308-
As described in p314, a technique is known in which a substrate is heat-treated after a Cu film is sputtered to fluidize Cu, and the fluidized Cu is moved into the groove to fill the groove.

[0006] Further, although not a disclosed technology, it is a technology invented by the present inventors, and is disclosed in Japanese Patent Application No. 8-25 / 1996.
No. 4362, that is, after sputtering a Cu film, the substrate is heat-treated in a state where voids are present in the Cu film, and Cu is buried in the groove and Cu in the groove and Cu on the surface of the insulating film are simultaneously formed. There is known a technique in which a film is separated from the film, and an excess Cu film on the surface of the insulating film is removed by removing the film with a tape or the like.

[0007]

However, in the case of a semiconductor integrated circuit device using a wiring having Cu as a main conductor layer, a connection hole is opened in an interlayer insulating film covering the wiring layer in order to connect to a lower wiring. At this time, an oxide film (copper oxide) is formed on the surface of the lower wiring at the bottom of the connection hole. Alternatively, an oxide film is formed on the surface or side surface of the wiring after forming the wiring by a damascene method or patterning combining photolithography and etching. Such an oxide film is oxidized by being exposed to ozone or oxygen plasma at the time of ashing of a resist after opening a connection hole, or by being exposed to an air atmosphere after forming a connection hole or a wiring. It is formed by natural oxidation, and causes a problem that the contact resistance at the bottom of the connection hole or the resistance of the wiring itself increases. Eventually, this may cause performance degradation such as impeding the high-speed response of the semiconductor integrated circuit device, and if it is notable, it may cause malfunction or decrease reliability.

As a method of removing such an oxide film,
An etching process using a special copper oxide etching gas may be performed, or a step of removing copper oxide by sputter etching may be considered.

However, when a special etching gas is used, a new gas is required, and the etching process and the etching apparatus are complicated, which is not preferable. When removing copper oxide by sputter etching,
When copper oxide is formed at the bottom of the connection hole, the connection hole has a high aspect ratio with the progress of miniaturization,
It becomes difficult to exert the effect of sputtering even to the bottom of the deep connection hole. That is, in the future highly integrated semiconductor device, it is difficult to clean the wiring surface at the bottom of the connection hole by sputter etching.

An object of the present invention is to provide a technique capable of reducing a contact resistance in a connection hole portion of a semiconductor integrated circuit device having a wiring using Cu or the like as a main conductor layer.

Another object of the present invention is to provide a technique capable of reducing the wiring resistance of a semiconductor integrated circuit device having a wiring using Cu or the like as a main conductor layer.

Further, it is an object of the present invention to secure the operation of a semiconductor integrated circuit device having a wiring using Cu or the like as a main conductor layer, to improve its reliability, and to improve its performance. It is to provide the technology that can be done.

Another object of the present invention is to realize a technique capable of easily removing an oxide film formed when forming a wiring or a connection hole using Cu or the like as a main conductor layer, and to realize the technique. It is an object of the present invention to provide an apparatus for manufacturing a semiconductor integrated circuit device that can be manufactured.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) In a method of manufacturing a semiconductor integrated circuit device according to the present invention, a semiconductor integrated circuit element is formed on a main surface of a semiconductor substrate, and a wiring made of copper, silver, aluminum, or an alloy thereof is provided in an upper layer. A method of manufacturing a semiconductor integrated circuit device having a multilayer wiring structure in which a plurality of wirings are formed, wherein: (a) a step of opening a connection hole or a groove in an interlayer insulating film covering the wiring; The method comprises the steps of applying heat, plasma or light energy while maintaining a reducing atmosphere, and (c) forming a conductive member in the connection hole or groove.

According to such a method of manufacturing a semiconductor integrated circuit device, heat, plasma or light energy is applied while holding the semiconductor substrate in a reducing atmosphere after, for example, opening a connection hole in the interlayer insulating film covering the wiring. Therefore, the oxide film (copper oxide) on the wiring surface at the bottom of the connection hole formed at the time of opening the connection hole can be removed. Therefore, even if a conductive member such as a plug is formed in the connection hole thereafter, the predetermined resistance of the semiconductor integrated circuit device is maintained without increasing the contact resistance due to the high-resistance copper oxide, and the reliability is improved. Can be improved.

That is, when a connection hole is opened in an interlayer insulating film covering a wiring, a high-resistance copper oxide (CuO or the like) is formed on the wiring surface at the bottom of the connection hole. Is reduced and converted to copper, so that the contact resistance does not increase.

By applying thermal energy in a reducing atmosphere, the reduction reaction can be promoted. By applying plasma energy, for example, hydrogen radicals are generated and the reduction reaction is promoted by the reactivity of the hydrogen radicals. Can be. Further, by applying light energy, the gas in the reducing atmosphere is excited to increase the reactivity, for example, to generate hydrogen or ammonium radicals,
The reduction reaction can be promoted.

When plasma energy is applied, the effect of sputtering is simultaneously exerted by the effect of plasma self-biasing, etc., and in addition to the chemical effect of radicals, the physical effect of sputtering (bombardment) is also increased. The synergistic effect of both actions makes it possible to further promote the reduction reaction.

In this manufacturing method, since no action such as sputtering is involved except when plasma energy is applied, it is possible to surely exert a reducing action even on the bottom of the connection hole having a high aspect ratio. It also has an advantageous effect on future miniaturization. Also, since there is no action such as sputtering, there is no change in the shape of the connection hole,
It is also possible to easily deal with fine processing. further,
The object etched by sputtering or the like does not re-attach to the bottom of the connection hole, and the re-adhesion does not cause a contact failure. In addition, since the wiring at the bottom of the connection hole is only reduced and not etched by sputtering, there is a problem that the accumulation of the wiring is reduced without reducing the copper atoms and the like constituting the wiring. Nothing. Even when plasma energy is applied, the above-described effect can be obtained in the same manner when processing is performed under conditions where the effect of sputtering is suppressed and a chemical effect is strongly exerted. Such conditions can generally be achieved with high processing pressures and low input power.

(2) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a semiconductor integrated circuit element is formed on a main surface of a semiconductor substrate, and a wiring made of copper, silver, aluminum, or an alloy thereof is formed thereon. A method for manufacturing a semiconductor integrated circuit device having a multilayer wiring structure in which a plurality of wirings are formed, comprising: (a) forming a groove or a connection hole in an interlayer insulating film covering a semiconductor integrated circuit element or a wiring; After depositing a thin film made of copper, silver or aluminum or an alloy thereof on the surface of the interlayer insulating film including the groove or the connection hole, the thin film on the interlayer insulating film excluding the groove or the connection hole is removed to form the wiring or the wiring and the lower layer. Forming a connection member for connecting to the wiring; and (b) applying heat, plasma or light energy while maintaining the semiconductor substrate in a reducing atmosphere.

According to such a method of manufacturing a semiconductor integrated circuit device, not only the bottom of the connection hole described in (1) but also the wiring or the connection when the wiring or the connecting member is formed by using a so-called damascene method. It is also possible to remove an oxide film (copper oxide) formed on the surface of the member.
As a result, it is possible to improve the performance of the semiconductor integrated circuit device without increasing the resistance value of the wiring or the connection member due to the oxide film formed on the surface of the wiring or the connection member. In the future, when the miniaturization of semiconductor integrated circuit devices advances and the film thickness of wiring or connecting members decreases,
The effect of the oxide film is relatively large, and the effect of taking such a measure becomes more remarkable.

(3) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a semiconductor integrated circuit element is formed on a main surface of a semiconductor substrate, and a wiring made of copper, silver, aluminum, or an alloy thereof is formed thereon. A method of manufacturing a semiconductor integrated circuit device having a multilayer wiring structure in which a plurality of wirings are formed, comprising: (a) copper, silver, aluminum, or aluminum on an upper surface of an interlayer insulating film covering a semiconductor integrated circuit element or a wiring; Forming a wiring by patterning the thin film after depositing a thin film made of such an alloy; and (b) applying heat, plasma or light energy while maintaining the semiconductor substrate in a reducing atmosphere. is there.

According to such a method of manufacturing a semiconductor integrated circuit device, not only the cases described in the above (1) and (2), but also the oxide film generated when the wiring is patterned on the interlayer insulating film. Removal can also be performed. As a result, as described in (2), it is possible to suppress an increase in the resistance of the wiring due to the oxide film and improve the performance of the semiconductor integrated circuit device.

(4) The thin film may be deposited by sputtering, CVD, or plating.
Alternatively, after a seed film made of copper, silver or aluminum is formed by a sputtering method, it may be deposited on the seed film by a plating method. By forming a thin film using a sputtering method or a CVD method in this manner, a semiconductor integrated circuit device can be stably manufactured using a conventionally established process, and when a plating method is used, It is possible to simplify the process and reduce the manufacturing cost.

By depositing a barrier metal before depositing the above-mentioned thin film, it is possible to prevent atoms such as metals constituting the thin film from diffusing into the interlayer insulating film. Further, in order to prevent the diffusion, not only the barrier metal but also the penetration of atoms such as metal may be prevented by modifying the interlayer insulating film or the like.

(5) The reducing atmosphere may be a hydrogen atmosphere or an ammonia atmosphere. As described above, by setting the atmosphere to a hydrogen atmosphere or an ammonia atmosphere, the wiring can be reduced without using a special gas, and the process can be simplified and the manufacturing apparatus can be simplified.

(6) In the manufacturing method, before or after the step (b), the substrate is exposed to or exposed to a reducing atmosphere at the bottom of the connection hole, the upper surface of the connection member, or the upper surface or side surface of the wiring. The method may include a step of performing sputter etching of the wiring portion or the connection member by plasma sputtering.

As described above, by further performing sputter etching on the wiring portion or the connecting member portion exposed to the reducing atmosphere, that is, the portion where the oxide film of the wiring or the connecting member is removed, the contact resistance is further reduced, or A reduction in the resistance value of the wiring can be ensured. In other words, when impurities exist at the bottom of the connection hole or on the surface or side surface of the wiring, it is considered that the impurity increases the contact resistance of the connection hole or the resistance of the wiring. This impurity can be removed by etching, so that contact resistance or wiring resistance can be reduced.

(7) The wiring has an anti-reflection film for preventing reflection of exposure light when patterning the wiring or forming connection holes or grooves in an interlayer insulating film on the wiring. Is included. The antireflection film can be made of an alloy such as copper in addition to titanium nitride (TiN).

(8) In the above-described manufacturing method, after the step (b), the semiconductor substrate is heated so that the bottom of the connection hole is heated.
The method may include a step of recrystallizing the wiring portion or the connecting member portion exposed to the reducing atmosphere on the upper surface of the connecting member or the upper surface or the side surface of the wiring. As described above, by recrystallizing by heating the portion exposed to the reducing atmosphere, that is, the portion from which the oxide film has been removed, the contact resistance of the connection hole or the resistance value of the wiring can be reduced. In other words, in the portion where the oxide film is removed by reduction of the wiring or the connection member, oxygen atoms are removed from the oxide film. For example, when the oxide film is made of copper, copper may be porous. It is. Such a porous portion may increase the contact resistance or increase the resistance value of the wiring. However, in the present invention, the wiring or the connecting member is fluidized by heating and is recrystallized. It is possible to eliminate the porous portion. As a result, it is possible to increase the contact resistance or suppress the increase in the resistance value of the wiring. In addition,
As a specific example of the heating temperature, for example, when copper is reduced in a hydrogen atmosphere at 350 ° C., a method of further increasing the temperature by 100 ° C. and treating at 450 ° C. can be exemplified.
Further, according to the present method, it is possible to reduce or eliminate polishing scratches formed on the wiring surface by fluidizing the members when forming the wiring by the CMP method.

(9) The apparatus for manufacturing a semiconductor integrated circuit device according to the present invention comprises a first reaction chamber capable of applying heat, plasma or light energy while maintaining a semiconductor substrate in a reducing atmosphere; An apparatus for manufacturing a semiconductor integrated circuit device having a second reaction chamber on which a compound can be deposited, wherein the first reaction chamber and the second reaction chamber are the same reaction chamber, or The first reaction chamber and the second reaction chamber may be connected in a non-oxidizing atmosphere or a reduced-pressure atmosphere.

According to such a semiconductor integrated circuit device manufacturing apparatus, the first reaction chamber and the second reaction chamber are the same reaction chamber, or the first reaction chamber and the second reaction chamber are not connected to each other. Are combined in a non-oxidizing or reduced-pressure atmosphere,
After removing the oxide film at the bottom of the connection hole or the surface or side surface of the wiring, a metal or a metal compound can be deposited without oxidizing the portion. As a result, the contact resistance of the connection hole can be reduced, the resistance value of the wiring can be reduced, and the performance and reliability of the semiconductor integrated circuit device can be improved.

(10) The manufacturing apparatus of the present invention further has a third reaction chamber capable of sputter-etching the semiconductor substrate by plasma sputtering, and comprises a first reaction chamber, a second reaction chamber, and a second reaction chamber. The third reaction chamber is the same reaction chamber, or the first reaction chamber, the second reaction chamber and the third reaction chamber are the same.
May be combined in a non-oxidizing atmosphere or a reduced-pressure atmosphere. As described above, by providing the third reaction chamber capable of being sputter-etched, impurities at the bottom of the connection hole or the surface or side surface of the wiring are further removed, thereby further reducing the contact resistance of the connection hole and further reducing the resistance of the wiring. The value can be reduced. Moreover, since these reaction chambers are connected in the same reaction chamber or in a non-oxidizing atmosphere or a reduced-pressure atmosphere, the bottom of the connection hole or the surface or side surface of the wiring is not oxidized during the process.

(11) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a semiconductor integrated circuit element is formed on a main surface of a semiconductor substrate, and a wiring made of copper, silver, aluminum, or an alloy thereof is formed on the semiconductor integrated circuit element. A method of manufacturing a semiconductor integrated circuit device having a multilayer wiring structure in which a plurality of wirings are formed, wherein the connection holes are opened in an interlayer insulating film covering the wirings or after the wirings are formed, This is for heating a semiconductor substrate having wiring. According to such a method of manufacturing a semiconductor integrated circuit device, even if an oxide film is formed on the bottom of the connection hole or on the surface or side surface of the wiring, only the oxygen atoms of copper oxide (CuO or the like) are heated by heating the semiconductor substrate. Is removed, and an increase in the contact resistance or an increase in the resistance value of the wiring can be suppressed. That is, the oxygen of copper oxide (such as CuO) has a certain vapor pressure, and can be changed from copper oxide (such as CuO) to copper by heating. Such heating can
Although the reaction can be performed in an inert atmosphere, it is preferably performed under reduced pressure.

[0037]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and a repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a sectional view showing an example of a semiconductor integrated circuit device manufactured by applying a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

The semiconductor integrated circuit device of the first embodiment is
An n-type MISFET Qn is formed in a p-well 4 of a semiconductor substrate 1 having an SOI insulating layer 2 and a U-groove element isolation region 3. SOI insulating layer 2, U-groove element isolation region 3
Is, for example, a silicon oxide film.

The n-type MISFET Qn is formed on the main surface of the semiconductor substrate 1 via a gate insulating film 6 made of, for example, a silicon oxide film having a thickness of several nm, for example, a gate electrode made of a low-resistance polycrystalline silicon film. 7 and impurity semiconductor regions 8 formed on the main surface of the semiconductor substrate 1 on both sides of the gate electrode 7. Sidewall spacers 9 and a cap insulating film 10 are provided on the side and upper surfaces of the gate electrode 7, respectively. Is formed.

The impurity semiconductor region 8 is an n-type MISFET
It functions as a source / drain region of Qn. W is formed on the gate electrode 7 and the impurity semiconductor region 8.
It may be constituted by a silicide film in which a refractory metal silicide film such as Six, MoSix, TiSix, TaSix or the like is laminated. The sidewall spacer 9 and the cap insulating film 10 can be, for example, a silicon oxide film or a silicon nitride film. When a silicon nitride film is used, the side wall spacer 9 and the cap insulating film 10 made of the silicon nitride film are used. Used as a mask,
A connection hole can be opened in an interlayer insulating film described later in a self-aligned manner.

Semiconductor substrate 1 and n-type MISFET Qn
Is formed with an interlayer insulating film 11a. As the interlayer insulating film 11a, a reflow film such as a BPSG film or a PSG film can be used. However, a laminated film with a silicon oxide film formed by a CVD method or a sputtering method below or above the interlayer insulating film 11a can be used. Can also.
The connection hole 1 is formed in the interlayer insulating film 11a on the impurity semiconductor region 8.
In the connection hole 12, a tungsten film 13a formed by, for example, a sputtering method and a metal plug 13b made of tungsten formed by, for example, a blanket CVD method or a selective CVD method are formed.

An interlayer insulating film 11b is formed above the interlayer insulating film 11a, and a wiring 14 is formed in a wiring groove 15 formed in the interlayer insulating film 11b.

The wiring 14 is composed of a main conductive layer 14a and a titanium nitride film 14b. The main conductive layer 14a may be, for example, copper, but may be silver or aluminum or an alloy thereof. By using such a material having a low resistivity as a main conductive layer, an increase in wiring resistance due to miniaturization of the wiring 14 can be suppressed. This makes it possible to achieve higher performance of the semiconductor integrated circuit device. The titanium nitride film 14b can function as a blocking film for preventing diffusion of a material constituting the main conductive layer 14a, for example, copper.
A tantalum nitride film, a tungsten nitride film, a sputtered tungsten film, or a compound thereof with silicon can also be used.

An interlayer insulating film 16 is formed on the upper surfaces of the wiring 14 and the interlayer insulating film 11b. As the interlayer insulating film 16, a silicon oxide film formed by a CVD method or a sputtering method can be exemplified. A connection hole 17 is provided in the interlayer insulating film 16 on the wiring 14, and the connection hole 1 is formed.
Similar to the connection hole 12, a tungsten film 18a formed by, for example, a sputtering method and a metal plug 18b made of tungsten formed by, for example, a blanket CVD method or a selective CVD method, are formed in 7.

At the interface between the tungsten film 18a and the wiring 14 at the bottom of the connection hole 17, for example, copper oxide, which is an oxide of copper, forming the wiring 14 is not formed. This is because the connection hole 17 is opened after the connection hole 17 is opened as described later.
The purpose of this is to reduce and eliminate the oxide film formed on the surface of the wiring 14 at the bottom of the wiring 7, thereby reducing the contact resistance in the connection hole 17 and improving the reliability of the electrical connection. It is possible. As a result, the performance and reliability of the semiconductor integrated circuit device can be improved.

As an upper layer of the interlayer insulating film 16, the interlayer insulating film 1
9 is formed, and a wiring 20 is formed in a wiring groove 21 formed in the interlayer insulating film 19.

The wiring 20 is made of the main conductive layer 2 like the wiring 14.
0a and a titanium nitride film 20b. Main conductive layer 20a
May be, for example, copper, but may be silver or aluminum or an alloy thereof. By using such a material having a low resistivity as a main conductive layer, an increase in wiring resistance due to miniaturization of the wiring 20 can be suppressed. This makes it possible to achieve higher performance of the semiconductor integrated circuit device. The titanium nitride film 20b can function as a blocking film for preventing the diffusion of a material constituting the main conductive layer 20a, for example, copper. In addition to the titanium nitride film, a tantalum nitride film, a tungsten nitride film, a sputtered tungsten film, or With silicon.

Note that no oxide film is formed on the surface of the wiring 14 or the wiring 20. This is for reducing and eliminating the oxide film formed on the surface of the wiring 14 or the wiring 20 to be described later, for example, by the CMP method, thereby reducing the resistance of the wiring 14 or the wiring 20. It is possible. As a result, the performance of the semiconductor integrated circuit device can be improved.

Although the first embodiment exemplifies a case where the number of wiring layers is two, an interlayer insulating film and a wiring similar to the interlayer insulating films 16 and 19 and the wiring 20 are formed in a multilayer structure. It is also possible to provide a semiconductor integrated circuit device having a multilayer wiring structure of three or more layers.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to the drawings. 2 to 18 are sectional views showing an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

Firstly, p has a SOI insulating layer 2 formed by hyperoxia implantation or the like ^- providing a semiconductor substrate 1 made of the form of single crystal silicon, an impurity for the conductivity type of p-type, such as boron Is doped by ion implantation or the like to form a p-well 4. The p-well 4 may be doped with an impurity gas during the epitaxial growth by the high-concentration oxygen implantation method.

Next, a U-groove reaching the SOI insulating layer 2 is formed on the main surface of the semiconductor substrate 1, and thereafter, for example, a silicon oxide film is deposited, and an excess silicon oxide film is removed by using a CMP method or the like. A silicon oxide film is buried in the U groove,
A U-groove element isolation region 3 is formed (FIG. 2).

Next, a silicon oxide film serving as a gate insulating film 6, a polycrystalline silicon film serving as a gate electrode 7, and a silicon oxide film serving as a cap insulating film 10 are sequentially deposited on the main surface of the semiconductor substrate 1 to form a laminated film. Is formed, and the laminated film is etched using a resist patterned by photolithography as a mask to form a gate insulating film 6, a gate electrode 7, and a cap insulating film 10 (FIG. 3). The gate insulating film 6 can be deposited by, for example, a thermal CVD method, and the gate electrode 7 can be formed by a CVD method. However, in order to reduce the resistance value, the gate electrode 7 is doped with an n-type impurity (for example, P). Is also good. Note that a refractory metal silicide film such as WSix, MoSix, TiSix, or TaSix may be laminated on the gate electrode 7. The cap insulating film 10 can be deposited by, for example, a CVD method.

Next, after a silicon oxide film is deposited on the semiconductor substrate 1 by the CVD method, reactive ion etching (RI
The silicon oxide film is anisotropically etched by the method E) to form sidewall spacers 9 on the side walls of the gate electrode 7 and ion-implant n-type impurities (phosphorus) to form p-wells on both sides of the gate electrode 7. 4 is an n-type MISFET Qn
Semiconductor region 8 constituting source and drain regions of
Is formed (FIG. 4). The side wall spacer 9
A low-concentration impurity semiconductor region may be formed before the formation of the semiconductor layer, and a high-concentration impurity semiconductor region may be formed after the formation of the sidewall spacer 9.

Next, a silicon oxide film is deposited on the semiconductor substrate 1 by a sputtering method or a CVD method to form an interlayer insulating film 11a.
To form Further, a connection hole 12 is formed in the interlayer insulating film 11a on the impurity semiconductor region 8 on the main surface of the semiconductor substrate 1 by using a known photolithography technique (FIG. 5).

Next, the tungsten film 1 is formed by sputtering.
3a is deposited (FIG. 6), and a tungsten film 13c is further deposited by blanket CVD (FIG. 7).

Next, the interlayer insulating film 11a other than the connection hole 12
Tungsten film 13c and tungsten film 13a
Is polished and removed by a CMP method to form a metal plug 13b (FIG. 8).

Next, a silicon oxide film is deposited by a sputtering method or a CVD method to form an interlayer insulating film 11b, which is further processed by using a known photolithography technique and an etching technique to form a wiring groove 15 (FIG. 9). 9). In addition,
Here, a silicon oxide film formed by a sputtering method or a CVD method is illustrated, but a coating film of SOG or the like, an organic film, a CVD silicon oxide film to which fluorine is added, a silicon nitride film, and a plurality of types of insulating films May be used as a multilayer film. The wiring groove 15 is formed in a region where the wiring material is to be buried later to form the wiring 14. In the first embodiment, the wiring groove 15 is formed after the metal plug 13 is formed.
Is formed, but after the connection hole 12 is opened, the wiring groove 1 is formed.
5 may be formed, and then the metal plug 13 may be formed.

Next, a titanium nitride film 14b to be the titanium nitride film 14b of the wiring 14 is deposited on the entire surface of the semiconductor substrate 1 (FIG. 10). The titanium nitride film 14b can be deposited by, for example, a CVD method or a sputtering method. The deposition of the titanium nitride film 14b is performed to improve the adhesion of the copper film and prevent the diffusion of copper, which will be described later. Although a titanium nitride film is exemplified in the first embodiment, a metal film such as tantalum or a tantalum nitride film may be used. It is also possible to sputter-etch the surface of the titanium nitride film 14b immediately before the next step of depositing the main conductive layer 14a. By such sputter etching, water, oxygen molecules, and the like adsorbed on the surface of the titanium nitride film 14b can be removed, and the adhesion of the main conductive layer 14a can be improved.
In particular, after deposition of the titanium nitride film 14b, the effect is great when vacuum breaking is performed to expose the surface to the atmosphere and deposit the main conductive layer 14a.

Next, a thin film of a metal, for example, copper, which will be the main conductive layer 14a, is deposited, heat-treated and fluidized to form the main conductive layer 14a well embedded in the wiring groove 15 (FIG. 11). For the deposition of the copper film, a normal sputtering method can be used, but a physical vapor deposition method such as an evaporation method may be used. The conditions of the heat treatment require a temperature and a time at which copper constituting the main conductive layer 14a is fluidized, and may be, for example, 350 ° C. to 400 ° C. for 3 minutes to 5 minutes.

Next, excess titanium nitride film 14b and main conductive layer 14a on interlayer insulating film 11b are removed, and
Are formed (FIG. 12). The removal of the titanium nitride film 14b and the main conductive layer 14a may be performed by, for example, a CMP method, but may be performed by an etch-back method. When the wiring 14 is formed, for example, when a CMP method is used, the process is performed in the air atmosphere, and the surface of the wiring 14 where copper is exposed is exposed to the air atmosphere and oxidized. You. As a result, an oxide layer (copper oxide) is formed on the surface of the wiring 14.
22 is generated. The oxide layer 22 is a high-resistance body, and if left unattended, increases the resistance value of the wiring 14 and causes a failure in electrical connection with an upper-layer wiring described later. Causes the performance and reliability of the device to decrease. However, in the first embodiment, in the process described below, the oxide layer 22 is reduced,
Since it is changed to copper, such a problem does not occur.

Next, the oxidized layer 22 is reduced to copper, which disappears (FIG. 13). The reduction reaction is performed by holding the semiconductor substrate 1 in a reducing atmosphere and applying heat, plasma, or light energy. Examples of the reducing atmosphere include a hydrogen atmosphere or an ammonia atmosphere.
Further, the reducing atmosphere can be at normal pressure or reduced pressure. In such a reducing atmosphere, hydrogen or ammonia can be activated by simultaneously applying heat, plasma or light energy to increase the reactivity and promote the reduction reaction. Also, by applying heat, plasma or light energy, the generation of hydrogen radicals is promoted,
The reduction reaction can be promoted by exposing the oxide layer 22 to the hydrogen radicals.

The application of heat energy can be performed by heating the semiconductor substrate 1, for example, a heat treatment at about 350 ° C. in a hydrogen or ammonia atmosphere. The application of plasma energy
Glow discharge can be performed under reduced pressure of hydrogen or ammonia, or a mixed gas of these gases and a rare gas such as argon. Further, application of light energy can be performed by irradiation with ultraviolet rays in a hydrogen or ammonia atmosphere. It is preferable to use far ultraviolet rays such as a low-pressure mercury lamp or an excimer laser as the ultraviolet rays, and it is preferable to irradiate the oxide layer 22 directly.

Further, even if the semiconductor substrate 1 is not placed in a reducing atmosphere but is simply subjected to a heat treatment in a non-oxidizing atmosphere, only the oxygen atoms in the oxide layer 22 are removed and the oxide layer 22 is changed to copper. Can be. This is presumably because copper oxide has a certain vapor pressure and oxygen may be dissociated particularly under reduced pressure. However,
It is considered that the effect of removing oxygen atoms is greater when heat treatment is performed in a reducing atmosphere.

As described above, in the first embodiment, the oxide layer 22
Can be removed, so that the resistance value of the wiring 14 can be reduced and the performance of the semiconductor integrated circuit device can be improved. Moreover, the removal of the oxide layer 22 is not a removal by an etching action, but a change to copper by reduction of the oxide layer 22, and does not involve a decrease in deposition. For this reason,
Even if such a reduction process is performed, the film thickness of the wiring 14 does not decrease, and does not reduce the resistance value.

When oxygen in the oxide layer 22 is removed by applying plasma energy, a sputtering operation utilizing a self-bias of plasma can be used together. In this case, not only oxygen in the oxide layer 22 is removed to promote the reduction reaction, but also impurities attached to the oxide layer 22 or the wiring 14 can be removed. Thus, an increase in the resistance value of the wiring 14 due to impurities can be suppressed, and the performance of the semiconductor integrated circuit device can be improved.

Further, at the same time as or after the reduction of the oxide layer 22, the semiconductor substrate 1 is heated, and the copper of the wiring 14 can be fluidized and recrystallized. this is,
There is a possibility that the surface of the reduced wiring 14 is somewhat porous.
4 can be suppressed from increasing. The elimination of the porous state also has the effect of suppressing the re-oxidation. Further, according to the present method, polishing scratches formed on the wiring surface when the wiring is formed by the CMP method can be reduced or eliminated by fluidizing the member.

Although not shown, a metal layer serving as an antireflection film may be formed on the surface of the wiring 14.

Next, a silicon oxide film is deposited on the semiconductor substrate 1 by a sputtering method or a CVD method to form an interlayer insulating film 16. Although a silicon oxide film formed by a sputtering method or a CVD method is illustrated here, a coating film of SOG or the like, an organic film, a CVD silicon oxide film to which fluorine is added, a silicon nitride film, and a plurality of types of insulating films It may be a multilayer film in which films are stacked. Further, a connection hole 17 is opened in the interlayer insulating film 16 at a predetermined position by using a known photolithography technique (FIG. 14). An oxide layer 23 is formed on the bottom of the connection hole 17 by ashing for removing a resist mask used for photolithography after the opening of the connection hole 17 or by exposure to the air atmosphere after the opening of the connection hole 17. Is done. The oxide layer 23 is a high-resistance body like the oxide layer 22, and if left unattended, electrical connection with a metal plug described later will be poor, and normal operation of the semiconductor integrated circuit device will be ensured. Cannot be performed, and the reliability is reduced.

Therefore, as in the case of the oxide layer 22 formed on the surface of the wiring 14, the oxide layer 23 is reduced to copper and is eliminated (FIG. 15). Since the reduction reaction is the same as that of the oxide layer 22, detailed description is omitted.

As described above, in the first embodiment, since oxide layer 23 can be removed, connection hole 17 can be removed.
The electric connection at the bottom of the semiconductor integrated circuit device can be reliably performed, the normal operation of the semiconductor integrated circuit device can be ensured, and its reliability and performance can be improved. Moreover, the oxide layer 23
Is not a removal by an etching action, but a change to copper by reduction of the oxide layer 23, and is not accompanied by a decrease in deposition. Therefore, even if such a reduction treatment is performed, the film thickness of the wiring 14 does not decrease, and the resistance value does not decrease. Further, since no etching action is involved, the shape of the connection hole 17 does not change. This is in line with the demands of future technology that requires more precise microfabrication, and has the effect of being one of the technologies that facilitates high integration of semiconductor integrated circuit devices. Further, the side wall of the connection hole 17 is sputtered,
There is no reattachment of spatter to the bottom. This eliminates the occurrence of reattachment due to sputtering, which may cause a reduction in the reliability of the electrical connection, thereby further improving the reliability of the semiconductor integrated circuit device.

When oxygen in the oxide layer 23 is removed by applying plasma energy, a sputtering operation utilizing a self-bias of plasma can be used together. In this case, not only the oxygen in the oxide layer 23 is removed to promote the reduction reaction, but also the impurities at the bottom of the connection hole 17 can be removed. As a result, it is possible to suppress a decrease in the reliability of the electrical connection due to the impurities, and to improve the reliability of the semiconductor integrated circuit device.

In the sputtering, the oxide layer 23 is formed by reduction.
Can be carried out before or after disappearing. As a result, it is possible to improve the reliability of the semiconductor integrated circuit device by removing impurities, as in the above-described effect.

After the reduction of the oxide layer 23, the semiconductor substrate 1 is heated, and the copper of the wiring 14 at the bottom of the connection hole 17 can be fluidized and recrystallized. This is because the surface of the reduced wiring 14 may be somewhat porous, and this can be eliminated by recrystallization to suppress a reduction in electrical connection reliability. The elimination of the porous state also has the effect of suppressing the re-oxidation.

Next, the tungsten film 1 is formed by sputtering.
8a (FIG. 16), and a tungsten film 18c is further deposited by blanket CVD (FIG. 17). Note that the deposition of the tungsten film 18a is preferably performed after the reduction of the oxide layer 23, without being exposed to the air atmosphere, while maintaining the reduced pressure atmosphere or the non-oxidizing atmosphere.

Next, the tungsten film 18c and the tungsten film 18a on the interlayer insulating film 16 other than the connection holes 17 are polished and removed by the CMP method to form a metal plug 18b (FIG. 18).

Finally, the interlayer insulating film 11b and the wiring 14
As in the case of (1), a wiring 20 composed of a main conductive layer 20a and a titanium nitride film 20b is formed in an interlayer insulating film 19 and a wiring groove 21 formed in the interlayer insulating film 19, and the semiconductor integrated circuit device shown in FIG. Almost completed. An oxide layer is formed on the wiring 20 similarly to the wiring 14, but it is needless to say that the oxide layer can be reduced and eliminated like the wiring 14.

According to the method of manufacturing the semiconductor integrated circuit device of the first embodiment, no oxide layer is formed on the surfaces of wirings 14 and 20, and an oxide layer is formed on wiring 14 on the bottom of connection hole 17. Not formed. As a result, it is possible to secure a predetermined function of the semiconductor integrated circuit device and improve the reliability and performance of the semiconductor integrated circuit device.

(Embodiment 2) FIG. 19 is a sectional view showing an example of a semiconductor integrated circuit device manufactured by applying a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention. .

The semiconductor integrated circuit device according to the second embodiment is
As in the first embodiment, an n-type MISFET is
The structure up to the formation of Qn and the provision of the wiring 14 as the first-layer wiring in the wiring groove 15 of the interlayer insulating film 11b thereover is the same as in the first embodiment. Therefore, the description of that part is omitted. The semiconductor integrated circuit device according to the second embodiment is different from the semiconductor integrated circuit device according to the first embodiment in that the second layer wiring is simultaneously opened with a wiring groove and a connection hole to the first layer wiring. In this case, the connection member and the wiring member are formed integrally at the same time, and then the excess wiring member is removed by a CMP method or the like. Therefore, in the following description, only the differences will be described.

An interlayer insulating film 24 is formed on the upper surfaces of the wiring 14 and the interlayer insulating film 11b. Interlayer insulating film 24
Can be exemplified by a silicon oxide film formed by the CVD method or the sputtering method as in the first embodiment.

In the interlayer insulating film 24, a connection hole 25 and a wiring groove 26 are integrally provided at predetermined positions. In the connection hole 25 and the wiring groove 26, a wiring which is a conductor as a connection member and a wiring material is provided. 27 are formed. Wiring 27
Is to integrally form the connecting member and the wiring member at the same time.

The wiring 27 is composed of the main conductive layer 27a and the main conductive layer 2
It comprises a seed film 27b and a titanium nitride film 27c for forming 7a by plating. Main conductive layer 27a
The seed film 27b may be, for example, copper, but may be silver or aluminum or an alloy thereof. By using such a material having a low resistivity as a main conductive layer, an increase in wiring resistance due to miniaturization of the wiring 27 can be suppressed. The titanium nitride film 27c is
The main conductive layer 27a and the seed film 27b can function as a blocking film for preventing diffusion of a material such as copper, and can function as a titanium nitride film, a tantalum nitride film,
A tungsten nitride film, a sputtered tungsten film, or a compound thereof with silicon can also be used.

The titanium nitride film 2 at the bottom of the connection hole 25
At the interface between the wiring 7c and the wiring 14, for example, copper oxide, which is an oxide of copper, constituting the wiring 14 is not formed. This is for reducing and eliminating the oxide film formed on the surface of the wiring 14 at the bottom of the connection hole 25 after the formation of the opening of the connection hole 25 and the formation of the wiring groove 26 as in the first embodiment. It is possible to reduce the contact resistance in the connection hole 25 and to improve the reliability of the electrical connection. As a result, the performance and reliability of the semiconductor integrated circuit device can be improved.

Further, no oxide film is formed on the surface of the wiring 14 or the wiring 27. This is also for reducing the oxide film formed on the surface of the wiring 14 or the wiring 27 after the formation by the CMP method, for example, in the same manner as in the first embodiment, thereby reducing the thickness of the wiring 14 or the wiring 27. It is possible to reduce the resistance. As a result,
The performance of the semiconductor integrated circuit device can be improved.

Although the second embodiment exemplifies the case where the number of wiring layers is two, the semiconductor integrated circuit device having a multi-layered structure of three or more layers may be formed. This is the same as in the first embodiment.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to the drawings. 20 to 23 are sectional views showing an example of a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps.

The manufacturing method of the second embodiment is the same as the steps up to FIG. 13 in the first embodiment. Therefore, the description of that part will be omitted, and the subsequent steps will be described.

A silicon oxide film is deposited on the interlayer insulating film 11b and the wiring 14 by a sputtering method or a CVD method to form an interlayer insulating film 24. Thereafter, a connection hole 25 is opened in the interlayer insulating film 24 at a predetermined position by using a known photolithography technique. Further, a wiring groove 26 is formed using a known photolithography technique (FIG. 20). The bottom of the connection hole 25 is formed by ashing for removing a resist mask used for photolithography after the formation of the connection hole 25 and the wiring groove 26 or in the atmosphere after the formation of the connection hole 25 and the wiring groove 26. By the exposure, an oxide layer 28 is formed as in the first embodiment. The oxide layer 28 is a high-resistance body like the oxide layers 22 and 23 of the first embodiment.
5, electrical connection at the bottom of the semiconductor integrated circuit device 5 becomes defective, so that normal operation of the semiconductor integrated circuit device cannot be ensured, and reliability is reduced.

Therefore, as in the first embodiment, the oxide layer 28 is reduced to copper and disappears. Thereby, electrical connection at the bottom of the connection hole 25 can be ensured. Note that the reduction reaction is the same as that in Embodiment 1, and thus the detailed description is omitted.

As described above, in the second embodiment, the oxide layer 28
, The electrical connection at the bottom of the connection hole 25 can be reliably performed, the normal operation of the semiconductor integrated circuit device can be secured, and its reliability and performance can be improved. is there. Moreover, the removal of the oxide layer 28 is not a removal by an etching action, but a change to copper by reduction of the oxide layer 28, and does not involve a decrease in deposition.
Therefore, even if such a reduction treatment is performed, the film thickness of the wiring 14 does not decrease, and the resistance value does not decrease. Further, since no etching action is involved, the connection holes 25
Also, the shape of the wiring groove 26 is not changed. This is in line with the demands of future technology that requires more precise microfabrication, and has the effect of being one of the technologies that facilitates high integration of semiconductor integrated circuit devices.
Further, the side walls of the connection hole 25 and the wiring groove 26 are sputtered, and there is no reattachment of spatter to the bottom of the connection hole 25. This eliminates the occurrence of reattachment due to sputtering, which may cause a reduction in the reliability of the electrical connection, thereby further improving the reliability of the semiconductor integrated circuit device.

[0093] When oxygen is removed from the oxide layer 28 by applying plasma energy, a sputtering action utilizing the self-bias of plasma can be used in combination. Sputtering reduces the oxide layer 28 by reduction. After that, what can be performed is the same as in the first embodiment.

Also, the semiconductor substrate 1 is heated after the reduction of the oxide layer 28, and the copper of the wiring 14 at the bottom of the connection hole 25 can be fluidized and recrystallized as in the first embodiment. It is.

Next, a titanium nitride film 27c is deposited on the entire surface of the semiconductor substrate 1, and a seed film 27b of the same material as the main conductive layer 27a is deposited (FIG. 21).

Titanium nitride film 27c can be deposited by, for example, a CVD method or a sputtering method, and seed film 27b can be deposited by, for example, a sputtering method or a CVD method. The deposition of the titanium nitride film 27c
This is to improve the adhesion of the copper film and prevent the diffusion of copper, which will be described later. Note that, other than the titanium nitride film, a metal film such as tantalum may be used. Also, the seed film 27
It is also possible to sputter-etch the surface of the titanium nitride film 27c immediately before b deposition. By such sputter etching, water, oxygen molecules, and the like adsorbed on the surface of the titanium nitride film 27c can be removed, and the adhesion of the seed film 27b can be improved.

The seed film 27b is a film serving as a crystal growth nucleus for forming a main conductive layer 27a described later by a plating method.

Next, a metal to be the main conductive layer 27a, for example, copper is deposited by a plating method (FIG. 22). Examples of the plating method include electrolytic plating and electroless plating. In the second embodiment, since the main conductive layer 27a is deposited by the plating method, the step coverage is excellent, and the connection hole 25 and the wiring groove 26 can be satisfactorily embedded. Further, since a large amount of processing can be performed in one step, the throughput of the step can be improved and the manufacturing cost can be reduced.
It is needless to say that a normal sputtering method, a vapor deposition method, or the like may be used similarly to the first embodiment without using the plating method. In the case of electroless plating, the seed film 27b is used.
Is not particularly necessary, and the main conductive layer 27a may be formed directly on the titanium nitride film 27c.

Next, the extra titanium nitride film 27c, seed film 27b and main conductive layer 27a on the interlayer insulating film 24 are removed, and the wiring 27 is formed (FIG. 23). Titanium nitride film 2
7c, the removal of the seed film 27b and the main conductive layer 27a
For example, a CMP method can be exemplified, but an etch-back method may be used. When the wiring 27 is formed, for example, by using the CMP method, the process is performed in an air atmosphere, and the wiring
Is exposed to the atmosphere and oxidized. As a result,
An oxide layer 29 is generated on the surface of the wiring 27. This oxide layer 29 is a high-resistance body, and if left as it is,
Although this may cause an increase in the resistance value of the wiring 27, it can be reduced and eliminated as in the first embodiment. As a result, a semiconductor integrated circuit device as shown in FIG. 19 can be almost completed.

According to the method of manufacturing the semiconductor integrated circuit device of the second embodiment, no oxide layer is formed on the surface of wiring 27, and no oxide layer is formed on wiring 14 on the bottom surface of connection hole 25. . As a result, it is possible to secure a predetermined function of the semiconductor integrated circuit device and improve the reliability and performance of the semiconductor integrated circuit device. Further, in Embodiment 2, since a member having copper as the main conductive layer is used as the connection member,
The resistance value of the connection member can be reduced, and the performance of the semiconductor integrated circuit device can be improved.

(Embodiment 3) FIG. 24 is a sectional view showing an example of a semiconductor integrated circuit device manufactured by applying a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention. is there.

The semiconductor integrated circuit device of the third embodiment is
As in the first embodiment, an n-type MISFET is
The structure up to the formation of Qn and the provision of the wiring 14 as the first-layer wiring in the wiring groove 15 of the interlayer insulating film 11b thereover is the same as in the first embodiment. Therefore, the description of that part is omitted. The semiconductor integrated circuit device according to the third embodiment is different from the semiconductor integrated circuit device according to the first embodiment in that the connection between the wiring 14 as the first wiring layer and the two-layer wiring is made of a plug having copper as a main conductive layer. And a point that a copper wiring patterned using photolithography is used for the second wiring layer. Therefore, in the following description, only the differences will be described.

An interlayer insulating film 30 is formed on the upper surfaces of the wiring 14 and the interlayer insulating film 11b, and a copper plug 32 having copper as a main conductive layer is formed in a connection hole 31 opened in the interlayer insulating film 30. The copper plug 32 includes a titanium nitride film 32b acting as a copper blocking layer and a main conductive layer 32a made of copper.

The interlayer insulating film 30 and the copper plug 32
In the upper layer, a copper wiring 33 is formed, and an interlayer insulating film 34 covering the copper wiring 33 is formed.

As the interlayer insulating films 30 and 34, a silicon oxide film formed by a CVD method or a sputtering method as in the first embodiment can be exemplified.

Further, no oxide layer is formed on the interface between the wiring 14 and the copper plug 32 at the bottom of the connection hole 31, the interface between the copper plug 32 and the copper wiring 33, and the upper and side surfaces of the copper wiring 33. . This is similar to the first and second embodiments.
This is for reducing and eliminating the oxide layer generated after the step of forming each member, whereby the contact resistance in the connection hole 31 can be reduced and the reliability of the electrical connection can be improved. The performance and reliability of the semiconductor integrated circuit device can be improved by reducing the resistance value of the copper wiring 33.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to the drawings. 25 to 30 are sectional views showing an example of a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention in the order of steps.

The manufacturing method of the third embodiment is the same as the steps up to FIG. 13 in the first embodiment. Therefore, the description of that part will be omitted, and the subsequent steps will be described.

A silicon oxide film is deposited on the interlayer insulating film 11b and the wiring 14 by a sputtering method or a CVD method to form an interlayer insulating film 30. Thereafter, a connection hole 31 is opened in the interlayer insulating film 30 at a predetermined position by using a known photolithography technique (FIG. 25). The bottom of the connection hole 31 is formed by ashing for removing a resist mask used for photolithography after the formation of the connection hole 31 or by exposure to the air atmosphere after the formation of the connection hole 31.
As in the first embodiment, oxide layer 35 is formed. This oxide layer 35 is a high-resistance body as in the first and second embodiments, and if left as it is, the electrical connection at the bottom of the connection hole 31 becomes defective, and the normal operation of the semiconductor integrated circuit device Cannot be ensured, and the reliability is reduced.

Therefore, as in the first and second embodiments, the oxide layer 35 is reduced to be changed to copper, which disappears.
Thus, electrical connection at the bottom of the connection hole 31 can be secured. Since the reduction reaction is the same as in Embodiments 1 and 2, detailed description will be omitted.

As described above, since the oxide film can be removed in the third embodiment, the electrical connection at the bottom of the connection hole 31 can be reliably performed, and the normal operation of the semiconductor integrated circuit device can be achieved. Operation can be ensured, and its reliability and performance can be improved. Moreover, the removal of the oxide layer 35 is not the removal by etching, but the removal of the oxide layer 35.
Are the same as in the first and second embodiments in that the change to copper by reduction does not involve a decrease in deposition, does not change the shape of the connection hole 31, and there is no reattachment. Further, it is the same as the first and second embodiments that the sputtering action can be used together when applying the plasma energy, and that the sputtering can be performed even after the oxide layer 35 is eliminated by reduction. Furthermore, after the reduction of the oxide layer 35, the semiconductor substrate 1 can be heated and the copper of the wiring 14 at the bottom of the connection hole 31 can be fluidized and recrystallized as in the first and second embodiments. is there.

Next, a titanium nitride film 32b is deposited on the entire surface of the semiconductor substrate 1 (FIG. 26). The titanium nitride film 32b is
For example, it can be deposited by a CVD method or a sputtering method. The deposition of the titanium nitride film 32b is performed to improve the adhesion of the copper film and prevent the diffusion of copper, which will be described later. Note that, other than the titanium nitride film, a metal film such as tantalum may be used.

Next, main conductive layer 32a made of, for example, copper
Is deposited (FIG. 27). The main conductive layer 32a can be deposited by a usual sputtering method, vapor deposition method, or plating method.

Next, excess titanium nitride film 32b and main conductive layer 32a on interlayer insulating film 30 are removed, and copper plug 3
2 is formed (FIG. 28). The removal of the titanium nitride film 32b and the main conductive layer 32a can be exemplified by a CMP method, for example, but may be performed by an etch-back method. In addition,
When the copper plug 32 is formed, for example, when a CMP method is used, the process is performed in an air atmosphere, and the surface where copper is exposed is exposed to the air atmosphere and oxidized. As a result, an oxide layer 36 is formed on the surface of the copper plug 32. This oxide layer 36 is a high-resistance body, and if left as it is, there is a possibility that the connection resistance between the copper plug 32 and the copper wiring 33 is increased. It is possible to reduce this to make it disappear.

Next, a copper thin film 37 is deposited on the entire surface of the semiconductor substrate 1 (FIG. 29). The copper thin film 37 can be deposited by a sputtering method or a CVD method. The copper thin film 3
7 may be provided with an anti-reflection film.

Next, the copper thin film 37 is patterned using known photolithography and etching techniques.
A copper wiring 33 is formed (FIG. 30). After this patterning, the copper wiring 33 is exposed to the air, so that an oxide layer 38 is formed on the upper surface and side surfaces thereof. This oxide layer 38 can be eliminated by reduction as described above. . Thereby, it is possible to suppress an increase in the resistance value of the copper wiring 33 and improve the performance of the semiconductor integrated circuit device.

Finally, an interlayer insulating film 34 is deposited on the entire surface of the semiconductor substrate 1, and the semiconductor integrated circuit device shown in FIG. 24 is almost completed.

According to the method of manufacturing the semiconductor integrated circuit device of the third embodiment, no oxide layer is formed on the upper and side surfaces of copper wiring 33, and the upper surface of copper plug 32 formed in connection hole 31 is formed. Also, no oxide layer is formed on the bottom surface. As a result, it is possible to secure a predetermined function of the semiconductor integrated circuit device and improve the reliability and performance of the semiconductor integrated circuit device.

(Embodiment 4) FIG. 31 is a conceptual diagram showing an example of a semiconductor integrated circuit device manufacturing apparatus according to another embodiment of the present invention.

FIG. 31A has a load chamber 39 and an unload chamber 40, and includes a pre-processing chamber 41, a reduction processing chamber 42,
A sputter etch chamber 43, a tungsten sputter chamber 44,
This is a metal film forming apparatus provided with a blanket tungsten CVD chamber 45, and each processing chamber is provided with a gate valve 47 in a transfer chamber 46.
Are connected via

In the pretreatment chamber 41, the substrate can be heated, and the adsorbed water molecules and adsorbed oxygen can be released.
In the reduction treatment chamber 42, heating, plasma treatment, or ultraviolet irradiation in a hydrogen atmosphere or an ammonia atmosphere can be performed. Although the sputter etching chamber 43 is not essential, plasma processing of a rare gas such as argon can be performed. Tungsten sputtering chamber 44
Then, the tungsten film 18a described in the first embodiment can be deposited, and blanket tungsten CVD is performed.
In the chamber 45, the tungsten film 1 described in Embodiment 1 is used.
8c can be deposited.

According to such a semiconductor integrated circuit device manufacturing apparatus, the pretreatment chamber 41, the reduction treatment chamber 42, the sputter etch chamber 43, the tungsten sputter chamber 44, the blanket tungsten C
Since the substrates are sequentially transported to the VD chamber 45, the processing substrate can be kept in a non-oxidizing atmosphere. Therefore, the oxide layer generated on the wiring 14 and the like in the first embodiment is
2, the tungsten film 18a and the tungsten film 18c can be deposited without oxidizing the portions, and a semiconductor integrated circuit device having high electrical connection reliability in the connection hole can be manufactured. .

It is preferable that each of the processing chambers and the transfer chambers 46 is in a reduced pressure or vacuum state, but may be in a non-oxidizing atmosphere such as an inert gas.

In the fourth embodiment, the metal plug 13
Although the example of the manufacturing apparatus in the case of forming the b is shown, when forming the wiring 27 made of copper or the copper plug 32 in the second and third embodiments, the tungsten sputtering chamber 44 is used.
By replacing the blanket tungsten CVD chamber 45 with a copper sputter chamber. Note that, instead of titanium nitride as a barrier layer, tantalum nitride, tungsten, tungsten nitride, or a silicide film thereof may be used. These barrier films may be deposited by any of the CVD method and the sputtering method.

Also, in a device in which a plurality of processing chambers 48 are connected via a gate valve 49 as shown in FIG. 31B, the pre-processing chamber 41, the reduction processing chamber 42, the sputter etching chamber 43 , A tungsten sputtering chamber 44 and a blanket tungsten CVD chamber 45 can be assigned to the respective processing chambers 48 to perform the processing alternately.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the first to fourth embodiments, the sputtering method has been mainly described, but the present invention may be applied to a vapor deposition method or an ionization sputtering method.

Also, the case where the main conductive layer is made of copper has been exemplified,
The present invention can be applied to a case where silver or aluminum may be used, and when a metal or a metal compound which causes trouble by oxidation is used for the wiring or the connecting member.

In the fourth embodiment, an example of a manufacturing apparatus having a plurality of processing chambers has been described. However, each processing may be performed in a single processing chamber.

[0130]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) The contact resistance at the connection hole of a semiconductor integrated circuit device having a wiring having Cu or the like as a main conductor layer can be reduced.

(2) The wiring resistance of a semiconductor integrated circuit device having a wiring whose main conductor layer is Cu or the like can be reduced.

(3) The operation of a semiconductor integrated circuit device having a wiring whose main conductor layer is Cu or the like can be ensured, its reliability can be improved, and its performance can be improved.

(4) A semiconductor integrated circuit device which can easily remove an oxide film formed at the time of forming a wiring or a connection hole using Cu or the like as a main conductor layer and can realize the same. A manufacturing apparatus can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an example of a semiconductor integrated circuit device manufactured by applying a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps;

FIG. 3 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps;

FIG. 4 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps;

FIG. 5 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 6 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps;

FIG. 7 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 8 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 9 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 10 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 11 is a sectional view showing an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 12 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 13 is a sectional view showing an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 14 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 15 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 16 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 17 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 18 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in the order of steps.

FIG. 19 is a cross-sectional view illustrating an example of a semiconductor integrated circuit device manufactured by applying a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 20 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps.

FIG. 21 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps.

FIG. 22 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps.

FIG. 23 is a cross-sectional view showing one example of a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention in the order of steps;

FIG. 24 is a cross-sectional view showing an example of a semiconductor integrated circuit device manufactured by applying a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention.

FIG. 25 is a sectional view showing an example of a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention in the order of steps.

FIG. 26 is a cross-sectional view showing an example of a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention in the order of steps.

FIG. 27 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention in the order of steps.

FIG. 28 is a sectional view showing an example of a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention in the order of steps.

FIG. 29 is a cross-sectional view showing an example of a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention in the order of steps.

FIG. 30 is a sectional view illustrating an example of a method of manufacturing a semiconductor integrated circuit device according to still another embodiment of the present invention in the order of steps.

FIGS. 31 (a) and 31 (b) are conceptual diagrams each showing an example of a semiconductor integrated circuit device manufacturing apparatus according to another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 SOI insulating layer 3 U-groove element isolation region 4 p-well 6 gate insulating film 7 gate electrode 8 impurity semiconductor region 9 sidewall spacer 10 cap insulating film 11a interlayer insulating film 11b interlayer insulating film 12 connection hole 13 metal plug 13a Tungsten film 13b Metal plug 13c Tungsten film 14 Wiring 14a Main conductive layer 14b Titanium nitride film 15 Wiring groove 16 Interlayer insulating film 17 Connection hole 18a Tungsten film 18b Metal plug 18c Tungsten film 19 Interlayer insulating film 20 Wiring 20a Main conductive layer 20b Titanium nitride Film 21 wiring groove 22 oxide layer 23 oxide layer 24 interlayer insulating film 25 connection hole 26 wiring groove 27 wiring 27a main conductive layer 27b seed film 27c titanium nitride film 28 oxide layer 29 oxide layer 30 interlayer insulating film 31 connection hole 32 copper plug 32a Main conductive layer 32b Titanium nitride film 33 Copper wiring 34 Interlayer insulating film 35 Oxide layer 36 Oxide layer 37 Copper thin film 38 Oxide layer 39 Load chamber 40 Unload chamber 41 Pretreatment chamber 42 Reduction treatment chamber 43 Sputter etch chamber 44 Tungsten sputter chamber 45 Blanket tungsten CVD chamber 46 Transfer chamber 47 Gate valve 48 Processing chamber 49 Gate valve Qn n-type MISFET

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hideki Yamaguchi 2326 Imai, Ome-shi, Tokyo Inside the Hitachi, Ltd.Device Development Center (72) Inventor Nobuo Owada 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Inside the center

Claims (11)

[Claims] 1. A semiconductor integrated circuit element is formed on a main surface of a semiconductor substrate, and a wiring made of copper, silver, aluminum, or an alloy thereof is formed on an upper layer of the semiconductor integrated circuit element. A method of manufacturing a semiconductor integrated circuit device having a multi-layer wiring structure, comprising: (a) a step of opening a connection hole or a groove in an interlayer insulating film covering the wiring; and (b) holding the semiconductor substrate in a reducing atmosphere. And (c) forming a conductive member in the connection hole or the groove while applying heat, plasma or light energy. 2. A semiconductor integrated circuit element is formed on a main surface of a semiconductor substrate, and a wiring made of copper, silver, aluminum, or an alloy thereof is formed on an upper layer of the semiconductor integrated circuit element, and the wiring is formed in a plurality of layers. A method of manufacturing a semiconductor integrated circuit device having a multi-layer wiring structure, comprising: (a) forming a groove or a connection hole in an interlayer insulating film covering the semiconductor integrated circuit element or the wiring, and including the groove or the connection hole; After depositing a thin film made of copper, silver or aluminum or an alloy thereof on the surface of the interlayer insulating film,
Removing the thin film on the interlayer insulating film excluding the groove or the connection hole to form a connection member for connecting the wiring or the wiring and a lower wiring, (b) holding the semiconductor substrate in a reducing atmosphere Applying a heat, plasma or light energy to the semiconductor integrated circuit device. 3. A semiconductor integrated circuit element is formed on a main surface of a semiconductor substrate, and a wiring made of copper, silver, aluminum, or an alloy thereof is formed on an upper layer of the semiconductor integrated circuit element, and the wiring is formed in a plurality of layers. (A) forming a thin film made of copper, silver, aluminum, or an alloy thereof on an upper surface of the semiconductor integrated circuit element or an interlayer insulating film covering the wiring; Forming a wiring by patterning the thin film after deposition; and (b) applying heat, plasma or light energy while maintaining the semiconductor substrate in a reducing atmosphere. A method for manufacturing an integrated circuit device. 4. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein the thin film in the step (a) is deposited by a sputtering method, a CVD method, or a plating method,
A method for manufacturing a semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is deposited by a plating method on a seed film made of copper, silver, or aluminum by a sputtering method. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the reducing atmosphere is a hydrogen atmosphere or an ammonia atmosphere. Method. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the bottom of the connection hole, the top surface of the connection member, or before or after the step (b). A method for manufacturing a semiconductor integrated circuit device, comprising a step of exposing the wiring portion or the connecting member portion exposed to the reducing atmosphere on the upper surface or the side surface of the wiring, or performing a sputter etching by plasma sputtering. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the wiring is formed when patterning the wiring or on the wiring. A method for manufacturing a semiconductor integrated circuit device, comprising an anti-reflection film for preventing reflection of exposure light when forming a connection hole or a groove in an interlayer insulating film. 8. The method of claim 1, 2, 3, 4, 5, 6, or 7.
The method for manufacturing a semiconductor integrated circuit device according to the above, wherein after the step (b), the semiconductor substrate is heated to bring the semiconductor substrate into the reducing atmosphere at the bottom of the connection hole, the upper surface of the connection member, or the upper surface or side surface of the wiring. A method of manufacturing a semiconductor integrated circuit device, comprising a step of recrystallizing the exposed wiring portion or the connecting member portion. 9. A first reaction chamber to which heat, plasma or light energy can be applied while holding a semiconductor substrate in a reducing atmosphere, and a second reaction chamber to which metal or a metal compound can be deposited. A first configuration in which the first reaction chamber and the second reaction chamber are the same reaction chamber, and wherein the first reaction chamber and the second reaction chamber are the same. A second configuration in which the reaction chamber and the reaction chamber are combined in a non-oxidizing atmosphere or a reduced-pressure atmosphere. 10. The apparatus for manufacturing a semiconductor integrated circuit device according to claim 9, wherein the apparatus for manufacturing a semiconductor integrated circuit device further comprises a third reaction chamber capable of sputter etching a semiconductor substrate by plasma sputtering. A first configuration in which the first reaction chamber, the second reaction chamber, and the third reaction chamber are the same reaction chamber; and the first reaction chamber, the second reaction chamber, and the like. A second configuration in which the third reaction chamber and the third reaction chamber are combined in a non-oxidizing atmosphere or a reduced-pressure atmosphere. 11. A semiconductor integrated circuit element is formed on a main surface of a semiconductor base, and copper is formed on the semiconductor integrated circuit element.
A method of manufacturing a semiconductor integrated circuit device having a wiring formed of silver or aluminum or an alloy thereof and having a multilayer wiring structure in which the wiring is formed in a plurality of layers, wherein a connection hole is formed in an interlayer insulating film covering the wiring. Heating the semiconductor substrate having the connection hole or the wiring after forming the wiring or after forming the wiring.