JP2000208627A - Production of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To satisfactorily develop a plating film with a technique for forming wiring by plating processing. SOLUTION: After a wiring groove 9a1 is formed on an inter-layer insulating film 5b on the inter-layer insulating film 5b and in the wiring groove 9a1, a barrier conductor film 10a and a seed conductor film 11a are deposited in the order from the lower layer. Furthermore, before depositing a conductor film on that seed conductor film 11a by plating, an oxide film 12 formed on the surface of the seed conductor film 11a is removed by reduction processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly to a technology effective when applied to a wiring forming technology by plating.

[0002]

2. Description of the Related Art A wiring forming technique studied by the present inventors is, for example, a wiring forming technique called a damascene method or a dual-damascene method.
In the damascene method, after forming grooves for wiring formation in the insulating film,
A conductive film for forming a wiring is applied on the insulating film and in the groove for forming the wiring, and furthermore, for example, a chemical mechanical polishing method (CM) is used to leave the conductive film only in the groove for forming the wiring.
This is a method of forming a buried wiring in a wiring forming groove by polishing by P (Chemical Mechanical Polishing). In addition, the dual damascene method is a method to which the damascene method is applied. After forming a groove for forming a wiring and a connection hole for connection with a lower layer wiring in an insulating film, the insulating film is formed on the insulating film. A conductive film for forming a wiring is deposited in the groove and the connection hole, and further, the conductive film is polished by CMP so as to remain only in the groove and the connection hole, so that the embedded wiring is formed in the groove for forming the wiring. And a plug is formed in the connection hole. For example, VMDubin, CHTing, and RC
heung, in Proceedings of 1997 International VLSI Mu
ltilevel Interconnection Conference, edited by T.
In E. Wade, Santa Clara, pp 69-74 (1997), a semiconductor substrate is introduced into a sputtering apparatus, and a plating seed layer is formed on the main surface of the semiconductor substrate 1 by a sputtering method. There is disclosed a technique in which a conductor film made of copper is formed on a plating seed layer by electrolytic plating by being introduced into a plating apparatus.

[0003]

However, the present inventor has found that there are the following problems in the wiring forming technology by the plating method.

That is, oxidation of the plating seed layer starts immediately after the semiconductor substrate on which the plating seed layer is formed is taken out of the sputtering apparatus. When the electrolytic plating is performed in this state, the etching of the oxide film formed on the surface of the plating seed layer proceeds. If the oxide film remains, the plating seed layer is inactive, and the plating film does not grow well. On the other hand, if the oxide film is excessively removed by etching, the plating seed layer becomes thin or partially discontinuous, and in this case, the plating film does not grow well. Further, when the surface of the plating seed layer is contaminated with an organic substance, the surface of the plating seed layer becomes inactive, and there is a problem that the plating film does not grow well. In the above damascene method and dual damascene method, the conductor film is buried in the fine wiring grooves and connection holes. There is a problem that voids are easily generated, which leads to poor connection and an increase in wiring resistance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique for forming a wiring by plating, in which a plated film can be favorably grown.

Another object of the present invention is to provide a technique capable of improving the reliability of wiring formed by plating.

A further object of the present invention is to provide a technique for forming a wiring by plating, which can satisfactorily embed a plating film in a wiring groove or a connection hole.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

The method of manufacturing a semiconductor device according to the present invention includes a step of forming a conductor film for forming a wiring of the semiconductor device by a plating method after the reduction treatment.

The method of manufacturing a semiconductor device according to the present invention comprises the steps of (a)
Forming a barrier conductor film; (b) forming a seed conductor film on the barrier conductor film; (c) performing a reduction treatment on the seed conductor film; Forming a conductive film on the seed conductive film after the step by a plating method.

Further, a method of manufacturing a semiconductor device according to the present invention
(A) forming a wiring groove in the insulating film; (b) forming a barrier conductive film on the insulating film and in the wiring groove; and (c) forming a seed conductive film on the barrier conductive film. (D) performing a reduction treatment on the seed conductive film, (e) forming a conductive film on the seed conductive film after the (d) process by a plating method, Shaving the conductive film to form a buried wiring in the wiring groove.

Further, a method of manufacturing a semiconductor device according to the present invention
(A) forming a wiring groove and a connection hole in an insulating film;
(B) a step of forming a barrier conductor film on the insulating film, in the wiring groove and in the connection hole, (c) a step of forming a seed conductor film on the barrier conductor film, and (d) the seed conductor film (E) forming a conductive film on the seed conductive film after the (d) step by plating, and (f) shaving the conductive film to remove the inside of the wiring groove and Forming a buried wiring in the connection hole.

Further, a method of manufacturing a semiconductor device according to the present invention
The reduction treatment is a treatment for performing a heat treatment, a plasma treatment, or a light irradiation treatment in a reducing atmosphere.

Further, a method of manufacturing a semiconductor device according to the present invention
The reduction treatment is a treatment in which the seed conductor film is immersed in a reducing liquid, a treatment in which the reducing liquid is vaporized by spraying and sprayed on the seed conductor film, or a vapor formed by boiling the reducing liquid. This is a process of immersing the seed conductor film in a phase atmosphere.

Further, a method of manufacturing a semiconductor device according to the present invention
Prior to the reduction treatment, a heat treatment, a plasma treatment, or a light irradiation treatment is performed on the seed conductor film in an oxidizing atmosphere.

Further, in the method of manufacturing a semiconductor device according to the present invention, there are provided (a) a step of forming a barrier conductor film, and (b) a step of forming a seed conductor film on the barrier conductor film.
(C) forming an oxidation suppression film on the surface of the seed conductor film; and (d) forming a conductor film on the seed conductor film by plating after removing the oxidation suppression film. It is.

The outline of typical inventions other than those described above among the inventions disclosed in the present application will be briefly described as follows.

That is, the method of manufacturing a semiconductor device according to the present invention comprises: (a) forming a barrier conductor film; and (b) forming a seed conductor film on the barrier conductor film.
(C) a step of performing a reduction treatment on the seed conductor film; (d) a step of forming an oxidation suppressing film on the surface of the seed conductor film after the step (c); Forming a conductive film on the seed conductive film by a plating method after the removal.

Further, a method of manufacturing a semiconductor device according to the present invention
(A) forming a wiring groove in the insulating film; (b) forming a barrier conductive film on the insulating film and in the wiring groove; and (c) forming a seed conductive film on the barrier conductive film. (D) performing a reduction treatment on the seed conductor film, (e) forming an oxidation suppressing film on the surface of the seed conductor film after the (d) step, and (f) performing the oxidation. Forming a conductive film on the seed conductive film by plating after removing the suppression film; and (g) shaving the conductive film;
Forming a buried wiring in the wiring groove.

Further, the method of manufacturing a semiconductor device according to the present invention
(A) forming a wiring groove and a connection hole in an insulating film;
(B) a step of forming a barrier conductor film on the insulating film, in the wiring groove and in the connection hole, (c) a step of forming a seed conductor film on the barrier conductor film, and (d) the seed conductor film (E) forming an oxidation suppression film on the surface of the seed conductor film after the step (d), and (f) removing the oxidation suppression film, A step of forming a conductor film on the film by a plating method,
(G) shaving the conductive film to form a buried wiring in the wiring groove.

Further, a method of manufacturing a semiconductor device according to the present invention
The plating film is made of Cu.

Further, the method of manufacturing a semiconductor device according to the present invention
The plating film is made of Ag.

Further, a method of manufacturing a semiconductor device according to the present invention
The plating film is Pt.

Further, a method of manufacturing a semiconductor device according to the present invention
The seed conductor film is a copper-based material.

Further, a method of manufacturing a semiconductor device according to the present invention
The seed conductor film is a silver-based material.

Further, a method of manufacturing a semiconductor device according to the present invention
The seed conductor film is a platinum-based material.

Also, in the plating apparatus of the present invention, the plating section and the reduction section of the seed conductor film are integrated through a transport path capable of forming a non-oxidizing atmosphere, a reducing atmosphere or a reduced pressure atmosphere. Things.

In the plating apparatus of the present invention, a reduction processing section capable of performing a reduction processing of the seed conductor film is integrally provided in the plating processing section.

[0030]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted. In the present embodiment, a p-channel type MISFET (Me
tal Insulator Semiconductor Field Effect Transisto
r) is abbreviated as pMIS, and an n-channel MISFET is abbreviated as nMIS.

(Embodiment 1) In the present embodiment, the technical idea of the present invention is described by, for example, pMIS and nMI.
A case where the present invention is applied to a method of manufacturing a semiconductor device having a CMIS (Complimentary MIS) circuit composed of S will be described. 1 to 18 show a semiconductor substrate (semiconductor wafer at this stage) 1 during the manufacturing process. As shown in FIG. 1, a semiconductor substrate 1 is made of, for example, a p-type silicon single crystal, and a part thereof includes p wells 2P and n
Well 2N is formed. For example, boron (B) is introduced into the p-well 2P. Also, n-well 2N
Has, for example, phosphorus (P) or arsenic (As) introduced. On the main surface of the semiconductor substrate 1, for example, a trench-type isolation portion 3 (trench isolation) is formed. The separation portion 3 is formed by burying a separation film 3b made of, for example, a silicon oxide (SiO ₂ ) film in a separation groove 3a dug in the thickness direction of the semiconductor substrate 1. The plane area of the active region L is defined by the separating portion 3.
This separation unit 3 is formed, for example, by selective oxidation (LOCOS; Loca).
l Oxidization of Silicon method).

Active regions L in p well 2P and n well 2N have nMISQn and pMIS, respectively.
Qp is formed. nMISQn and pMISQ
p is a pair of semiconductor regions 4n formed on the semiconductor substrate 1.
d, 4nd, 4pd, 4pd, gate insulating films 4i, 4i formed on the semiconductor substrate 1, and gate electrodes 4g, 4g formed thereon. The pair of semiconductor regions 4nd, 4nd, 4pd, and 4pd have nMI
This is a region where the source and drain of SQn and pMISQp are formed. The semiconductor region 4nd is made n-type by, for example, introducing phosphorus or arsenic. In addition, the semiconductor region 4pd is, for example, boron-doped, and has a p-type. Each of the pair of semiconductor regions 4nd and the pair of semiconductor regions 4pd is composed of two semiconductor regions having different impurity concentrations, and the semiconductor region having a relatively low impurity concentration is formed adjacent to the channel of each MISFET. You can also. Thereby, the hot electron effect can be suppressed. In each of the pair of semiconductor regions 4nd and the pair of semiconductor regions 4pd,
A semiconductor region having a conductivity type opposite to the conductivity type of the semiconductor regions 4nd and 4pd may be formed at an end of each MISFET adjacent to the respective channel. Thereby, the short channel effect can be suppressed. Further, a silicide layer such as tungsten silicide (WSi ₂ ) can be formed on the pair of semiconductor regions 4nd and 4pd. Thereby, the wiring and the semiconductor region 4nd,
The contact resistance with 4 pd can be reduced.

The gate insulating films 4i and 4i of the nMISQn and the pMISQp are both made of, for example, a silicon oxide film and formed in the same step. This gate insulating film 4
After the formation of the gate insulating films 4i and 4i, the semiconductor substrate 1 is subjected to a heat treatment in, for example, an NO (nitrogen oxide) or N ₂ O (nitrogen oxide) atmosphere. Nitrogen can be segregated at the interface with the substrate (oxynitriding treatment). Gate insulating films 4i, 4
When i is reduced to about 8 nm, the distortion generated at the interface between the two due to the difference in thermal expansion coefficient with the semiconductor substrate 1 becomes apparent,
Induces hot carriers. Since nitrogen segregated at the interface with the semiconductor substrate 1 relaxes this distortion, the above-described oxynitridation improves the reliability of the ultra-thin gate insulating films 4i, 4i, and suppresses hot carriers by improving the MISF.
The reliability of ET can be improved.

The gate electrodes 4g and 4g of the nMISQn and pMISQp are formed by forming a silicide layer such as tungsten silicide on a low resistance polysilicon film, for example, and are patterned in the same step. The gate electrodes 4g, 4g can be formed of a single film of a low-resistance polysilicon film, or a barrier such as tungsten nitride (WN) or titanium nitride (TiN) is formed on the low-resistance polysilicon film. A so-called polymetal structure in which a metal film such as tungsten (W) or the like is formed via a metal film can also be used. By forming the gate electrodes 4g, 4g in a polymetal structure, the gate electrodes 4g, 4g
g can be reduced. At one end of each of the gate electrodes 4g, 4g, a wide area is formed in a plane. This is a region for electrically connecting the upper layer wiring and the gate electrodes 4g, 4g. On such gate electrodes 4g, 4g, for example, a silicon oxide film or silicon nitride (Si
N) A cap insulating film made of a film may be provided.
Further, a sidewall insulating film made of, for example, a silicon oxide film or a silicon nitride film may be provided on the side surfaces of the gate electrodes 4g, 4g and the cap insulating film.

On the main surface of such a semiconductor substrate 1, an interlayer insulating film 5a is formed, thereby forming an nMISQ.
n and pMISQp are coated. Interlayer insulating film 5
a is made of, for example, a silicon oxide film, and its upper surface is subjected to a flattening process. A connection hole 6a is formed in the interlayer insulating film 5a so that a part of the pair of semiconductor regions 4nd and 4pd is exposed, and a plug 7 is formed therein. The plug 7 is made of, for example, low-resistance polysilicon.

In this state, first, as shown in FIG. 2, an insulating film 8a made of, for example, silicon nitride is formed on the interlayer insulating film 5a by CVD so that the upper surface of the plug 7 is also covered.
It is deposited by a method or the like. Subsequently, on the insulating film 8a,
After depositing an interlayer insulating film 5b made of, for example, silicon oxide by a CVD method or a coating method, the upper surface thereof is subjected to CMP.
(Chemical Mechanical Polishing) method or the like. Thereafter, as shown in FIGS. 3A and 3B, the wiring grooves 9a (9a1) are formed in the interlayer insulating film 5b and the insulating film 8a by photolithography and etching.
To 9a3). In this etching treatment, first, silicon oxide is etched under conditions that are easier to remove than silicon nitride, and then, at the stage where the insulating film 8a made of silicon nitride is exposed, silicon nitride is more likely than silicon oxide. The wiring groove 9a is formed by changing to a condition in which the wiring groove 9a is easily removed. Note that the wiring groove 9a may be formed by a method such as control of the etching time without using the insulating film 8a made of silicon nitride. Further, the interlayer insulating film 5a has a structure in which a silicon nitride film is laminated on a silicon oxide film, for example, and the dry etching at the time of forming the wiring groove is completed when the silicon nitride film is exposed, and the wiring groove 9 is formed.
a may be formed. The wiring groove 9a is formed such that its depth is larger than its width, and its aspect ratio is, for example,
It is about 1.1 to 2.5. The upper surface of the plug 7 is exposed from the bottom surface of the wiring groove 9a. FIG. 3B is an enlarged sectional view of a main part of the wiring groove 9a1 in FIG.

Then, as shown in FIGS. 4 and 5, a barrier conductor film 10a and a seed conductor film 11a are sequentially deposited on the main surface of the semiconductor substrate 1 from a lower layer by a sputtering method, a CVD method, or a combination thereof. Thereby, the inside of the wiring groove 9a and the exposed surface of the interlayer insulating film 5a are covered. The barrier conductor film 10a has a function of suppressing diffusion of a copper-based (copper or copper alloy) wiring described later, and is made of, for example, tantalum, tantalum nitride, tungsten, or tungsten nitride, and has a thickness of, for example, about 50 nm. Or less. The seed conductor film 11a is
Seed when forming copper-based wiring by plating
Is a conductive film, for example, made of copper or copper alloy,
Its thickness is, for example, about 100 to 200 nm. FIG. 5 is an enlarged sectional view of a main part of the wiring groove 9a1 in FIG. By including copper, Pt, and Pd in the barrier conductor film 10a, the seed conductor film 11a can be easily formed by electrolytic or electroless plating.

FIG. 6 shows that after the barrier conductor film 10a and the seed conductor film 11a are formed, the seed conductor film 11a is formed.
Shows a case where the oxide film 12 has been formed on the surface (exposed surface) of FIG. Such an oxidation phenomenon occurs when the semiconductor substrate 1
From the seed conductor film 11a immediately after being taken out of the film forming apparatus. In the state where the oxide film 12 is formed on the surface of the seed conductor film 11a, if the semiconductor substrate 1 is immersed in a plating solution for forming wiring, the etching of the oxide film 12 proceeds. However, if the oxide film 12 is left without being removed satisfactorily, the surface of the seed conductor film 11a is in an inactive state, and the plating film does not grow well. If the oxide film 12 is excessively removed by the etching process, the seed conductor film 11a itself becomes thin or partially discontinuous, so that the plating film does not grow well in such a case.

Therefore, in the first embodiment, for example, the following processing is performed prior to the plating processing for forming the wiring.

In the first method, the semiconductor substrate 1 is heated at a temperature of, for example, 200 to 450 ° C. in a reducing atmosphere such as hydrogen (H ₂ ) or ammonia (NH ₃ ).
A short-time heat treatment of about 5 minutes is performed. Thereby, the oxide film 12 is removed, and the surface of the seed conductor film 11a can be exposed. This is because hydrogen and ammonia are converted to oxide film 1
This is because it has the property of dissociating the oxygen in 2 and by performing this treatment oxygen can be extracted from the oxide film 12 and returned to the original copper. Therefore, the surface of the seed conductive film 11a can be activated without impairing the thickness of the seed conductive film 11a. Further, instead of the above-described reducing atmosphere, a non-oxidizing atmosphere such as nitrogen (N ₂ ) or argon (Ar) can be used. Although nitrogen and argon themselves do not have the property of dissociating oxygen in the oxide film 12, the seed conductor film 11
Since the composition of the oxide film 12 on the surface of a is unstable, only the oxygen can be removed even in the heat treatment in a non-oxidizing atmosphere to restore the original copper. Furthermore, the same effect can be obtained even if heat treatment is performed on the semiconductor substrate 1 in a vacuum. In these cases, it is necessary to set the processing temperature higher than in the case of the above-mentioned reducing atmosphere, but there is an effect that foreign substances are hardly adhered and the environment is friendly.

In a second method, the semiconductor substrate 1 is subjected to a plasma treatment or a light irradiation treatment in the reducing atmosphere or the non-oxidizing atmosphere. In this case, the same effect as that of the first method can be obtained, and at the same time, the processing can be performed at room temperature and the low-temperature processing can be performed.

In the third method, the semiconductor substrate 1 is
-Immerse in a reducing liquid such as ascorbic acid or formaldehyde. Thus, the oxide film 12 on the surface of the seed conductor film 11a can be reduced and returned to copper. Therefore, also in this case, the surface of the seed conductive film 11a can be activated without impairing the thickness of the seed conductive film 11a.

In the fourth method, the reducing liquid is sprayed on the surface of the semiconductor substrate 1 on which the seed conductor film 11a is formed. Accordingly, the same effects as those of the third method can be obtained, and a relatively small processing device can be used.

In a fifth method, the semiconductor substrate 1 is immersed in saturated vapor obtained by boiling the reducing liquid (vapor treatment: reduction treatment in a vapor phase). Thus, the same effects as those of the third and fourth methods can be obtained, the adhesion of foreign substances can be reduced, and the reducing action is caused in a relatively uniform and non-uniform state on the surface of the seed conductor film 11a. be able to.

In a sixth method, after forming the seed conductor film 11a, the semiconductor substrate 1 is subjected to a heat treatment, a plasma treatment or a light irradiation treatment in an oxidizing atmosphere. Thereby, the main surface of the semiconductor substrate 1, that is, the seed conductor film 11
The organic substance deposited on the surface on which a is formed is CO / CO ₂
Etc. and can be removed. Then, the first
The oxide film 12 formed on the surface of the seed conductor film 11a is removed by performing any one of the methods from (5) to (5).

In a seventh method, immediately after the formation of the seed conductor film 11a, an oxidation suppressing film such as benzotriazole (BTA) is applied to the surface of the seed conductor film 11a by a spin coating method or the like. The oxidation of the film 11a is suppressed. Then, immediately after the oxidation suppression film is removed by the heat treatment, the process proceeds to a later-described conductor film plating process.
As a modified example, after performing the first to sixth reduction treatments, the oxidation suppression film may be covered, and the oxidation suppression film may be removed immediately before plating the conductor film.

By employing the first to seventh methods as described above, as shown in FIG.
It is possible to remove the oxide film on the surface and to expose the surface of the seed conductor film while keeping the thickness of the seed conductor film. In the present embodiment, after exposing the surface (active surface) of seed conductor film 11a in this way, as shown in FIGS. 8 and 9, copper or copper alloy is formed on seed conductor film 11a. The conductor film 13a is formed by an electrolytic plating method. In the present embodiment, since oxide film 12 on seed conductor film 11a has been removed, conductor film 13a can be grown almost uniformly on seed conductor film 11a. Alternatively, in the case where a plating solution having characteristics such that the preferential growth is performed in the wiring groove is used, the preferential growth can be performed as originally intended. Therefore, generation of voids and the like in the conductor film 13a in the wiring groove 9a can be suppressed. As a result, the occurrence rate of wiring connection failure can be reduced, and fluctuation and increase in wiring resistance can be suppressed. FIG. 9 is an enlarged sectional view of a main part of the wiring groove 9a1 in FIG. Further, the conductor film 13a can be formed by an electroless plating method.

Subsequently, the barrier conductor film 10a, the seed conductor film 11a and the conductor film 13a are formed by CMP (Chemical Mec.).
hanical Polishing)
As shown in FIG. 10, the barrier conductor film 10 is formed in the wiring groove 9a.
a, a first layer buried wiring 14a composed of the seed conductor film 11a and the conductor film 13a is formed. The buried wiring 14a has its bottom part in contact with the upper surface of the plug 7 and is electrically connected to the plug 7.

Thereafter, as shown in FIG. 11, an insulating film 8b made of, for example, silicon nitride is formed on the interlayer insulating film 5b.
After depositing an interlayer insulating film 5c made of silicon oxide or the like and an insulating film 8c made of silicon nitride or the like in order from the bottom by a CVD method or the like, as shown in FIG. 12, a photoresist film 15a patterned on the insulating film 8c is removed. As an etching mask, a connection hole 6b is formed in the insulating film 8c by performing a selective etching process under a condition in which silicon nitride is more easily removed by etching than silicon oxide. The connection hole 6b is a pattern for forming a connection hole for connecting different wiring layers, and is formed, for example, in a plane circular shape.

Next, as shown in FIG. 13, the insulating film 8c
After depositing an interlayer insulating film 5d made of, for example, silicon oxide by a CVD method so as to cover the connection holes 6b,
A photoresist film 15b for forming a wiring groove is formed thereon. Subsequently, by using the photoresist film 15b as an etching mask, an etching process is performed under the condition that silicon oxide is more easily etched and removed than silicon nitride, thereby forming the wiring groove 9b in the interlayer insulating film 5d as shown in FIG. To form The planar shape of the wiring groove 9b is formed, for example, in a rectangular shape or a band shape extending in a direction perpendicular to the paper surface of FIG. Subsequently, by continuing the etching process, as shown in FIG. 15, connection holes 6c are formed in the interlayer insulating film 5c using the insulating film 8c as a mask. At this time, the insulating film 8b functions as an etching stopper so that the connection hole 6c is not excessively cut. Further, by performing an etching process under conditions in which silicon nitride is more easily removed by etching than silicon oxide, the insulating film 8b remaining at the bottom of the connection hole 6c is removed,
As shown in FIG. 16, a connection hole 6d is formed in the insulating film 8b. From the bottom of the connection hole 6d, the embedded wiring 14 of the first layer is formed.
a is partially exposed. In this case, the silicon nitride 8b was used as an etching stopper. However, without using this, a wiring groove was formed by drilling a connection hole using the photoresist film as an etching mask and then again using the photoresist film as an etching stopper and controlling the etching time. Alternatively, the pattern may be formed in the order of the wiring groove and the connection hole.

Next, after removing the photoresist film 15b, as shown in FIG. 17, the barrier conductor film 10b, the seed conductor film 11b, and the conductor film 13b are formed in the same manner as described above (the same material, the same thickness, and the same (Using any one of the first to seventh methods), and is deposited on the semiconductor substrate 1. In this case, the barrier conductor film 10b, the seed conductor film 11b, and the conductor film 13b are connected to the inside of the wiring groove 9b and the connection holes 6b, 6c,
Embedded in 6d. After that, the barrier conductor film 10b,
By polishing the seed conductor film 11b and the conductor film 13b by the CMP method as described above, as shown in FIG.
A second-layer buried wiring 14b is formed in the wiring groove 9b. The buried wiring 14b is electrically connected to the underlying buried wiring 14a through the barrier conductor film 10b, the seed conductor film 11b, and the conductor film 13b buried in the connection holes 6b, 6c, 6d.

Next, an example of a semiconductor manufacturing apparatus used in the manufacturing process of the semiconductor device of the present embodiment will be described.

FIGS. 19A and 19B show the conductive film 13.
It is explanatory drawing of the electrolytic plating apparatus 15 at the time of the electrolytic plating processing for forming 13a and 13b. Each apparatus has a plating solution tank 15a, a plating material electrode 15b, a DC power supply 15c, and a contact terminal 15d, and a plating solution made of, for example, sulfuric acid or the like is stored in the plating solution tank 15a. . The plating material electrode 15b is
This is a material for forming a and 13b, for example, copper. The plating material electrode 15b is immersed in a plating solution, and the main surface of the semiconductor substrate 1 (the seed conductor film 11)
a, 11b). A positive voltage is applied to the plating material electrode 15b from a DC power supply 15c. The semiconductor substrate 1 is placed with its main surface, that is, the seed conductor films 11a and 11b immersed in a plating solution. During the plating process, a DC power supply 15 is applied to the seed conductor films 11a and 11b.
A negative voltage or a voltage of 0 V is applied from c through the contact terminal 15d. The difference between the devices of FIGS. 19A and 19B is that the contact portion between the contact terminal 15d and the seed conductor films 11a and 11b is outside the plating solution tank 15a (FIG. 19A). Is it in the tank 15a (Fig. (B))
It is. In the apparatus shown in FIG. 19A, an insulating shield member 15a2 is interposed between the liquid tank wall 15a1 of the plating liquid tank 15a and the main surface of the semiconductor substrate 1.
The plating solution in 5a does not leak to the outside.

FIGS. 20 and 21 are explanatory views of a semiconductor manufacturing apparatus 16 in which a plating apparatus and the reduction apparatus are integrated with a transfer chamber therebetween. FIG. 20 shows each processing block 16a and the flow of processing of the semiconductor substrate (semiconductor wafer) 1. The positioning processing unit 16a is a processing unit that performs centering of the semiconductor substrate 1 carried into the semiconductor manufacturing apparatus 1 and sets a planar position.
However, it may not be necessary depending on the structure of the plating section. The pre-processing unit 16b is a processing unit that performs the above-described reduction processing. When performing the decompression processing, it is necessary to provide a gate valve for isolation from the outside. The plating section 16c
This is a processing section for forming the conductor films 13a and 13b. Wash /
The drying processing unit 16d is a processing unit that performs a washing process and a drying process on the semiconductor substrate 1 after the plating process. In some cases, the plating section and the washing / drying section can be integrated. The transfer chamber 16e is a component that transfers the semiconductor substrate 1. The inside of the transfer chamber 16e can be set to the non-oxidizing atmosphere, the reducing atmosphere, or the reduced-pressure atmosphere. By performing the above-described reduction processing in the transfer chamber 16e, the size of the semiconductor manufacturing apparatus can be reduced. In addition, since the time from the reduction process to the plating process can be shortened, reoxidation and adhesion of foreign substances after the reduction process can be suppressed, and the growth of plating can be improved.

FIG. 21 shows a specific example of the configuration of the semiconductor manufacturing apparatus 16 of FIG.
6 is shown. The cassette 17 is a storage container that can store a plurality of semiconductor substrates 1. The semiconductor substrates 1 of the cassette 17 are structured to be extracted and processed one by one. Near the center of the transfer chamber 16e, each processing unit 16
A transfer robot 16e1 for transferring the semiconductor substrate 1 to each processing section 16b, 16c, 16d is provided so as to be surrounded by b, 16c, 16d. The transfer robot 16e1 is shown as a frog-leg type,
The present invention is not limited to this, and various types such as a linear type can be used. Although the positioning processing unit is not shown in FIG. 21, it is needless to say that the positioning processing unit may be provided. In addition, as shown in FIG. 22, which will be described later, a plurality of processing units may be provided to simultaneously process a plurality of semiconductor substrates.

FIG. 22 shows a case where the semiconductor manufacturing apparatus 16 has no pretreatment chamber. The semiconductor manufacturing apparatus 16 has a structure in which individual processing is performed on the semiconductor substrate 1 one by one. However, the semiconductor manufacturing apparatus 16 includes a plurality of plating units 16c and a cleaning / drying unit 16d. The structure is such that the semiconductor substrate 1 can be processed. The reduction treatment is performed separately, the atmosphere in the transfer chamber 16e is set to a reduction treatment atmosphere (however, in this case, heat treatment or light irradiation treatment), or the plating treatment unit 1
A reduction processing unit may be integrally provided in 6c to perform the reduction processing immediately before the plating processing.

FIGS. 23 and 24 show the plating section 16c.
2 shows a structure in which a reduction processing unit is integrally provided. FIG. 23 illustrates a reduction process, and FIG. 24 illustrates a plating process. The hatching in FIG. 24 indicates a plating solution. The plating section 16c is formed by the chamber walls 16c1 to
16c3, a reduction chamber 16c4, a plating outer chamber 16c5, a plating inner chamber 16c6, a substrate holder 16c7, a processing liquid supply nozzle 16c8, and a plating material electrode 16c9. I have. Openings 18a to 18c are formed in the upper portions of the chamber walls 16c1 to 16c3.
18c are formed, of which openings 18b, 1
8c through the reduction chamber 16c4, the plating chamber 16
c5 and the inner plating processing chamber 16c6 communicate with each other. The openings 18a and 18b of the chamber walls 16c1 and 16c2 are formed with dimensions larger than the substrate holding surface of the substrate holder 16c7. It is possible to move to 16c5. On the other hand, the opening 18c of the chamber wall 16c3 is formed to have a size smaller than the substrate holding surface (the plane size of the semiconductor substrate 1) of the substrate holder 16c7. A step is formed near the opening 18c on the outer upper portion of the chamber wall 16c3 so that the semiconductor substrate 1 is cut along the outer periphery of the opening 18c so as to fit in a plane. On the upper surface of this step, the shield member 19 and the contact terminal 2 are arranged in order from the inside to the outside.
0 extends along the outer periphery of the opening 18c. As shown in FIG. 24, when the semiconductor substrate 1 is fitted into the step near the opening 18c and the opening 18c is closed, when the plating solution is supplied into the plating inner chamber 16c6, the shielding member 19 Is a member that closes so as not to leak out from between the semiconductor substrate 1 and the step portion. Further, the contact terminal 20 is a contact terminal 15 of the plating apparatus 15.
Since it corresponds to d, the description is omitted. In addition, room wall 1
A drainage pipe 21a is provided below 6c1 so that the reduction processing liquid can be discharged to the outside during the reduction processing. Also, in the lower part of the room wall 16c2,
A drain pipe 21b is provided, through which the plating solution can be removed to the outside during the plating process. Further, an opening 18d is provided on a side surface of the chamber wall 16c3, through which the outer plating processing chamber 16c5 and the inner plating processing chamber 16c6 communicate. In addition, the room wall 16
An inflow pipe 21c is provided below c3, through which the plating solution can flow into the plating inner chamber 16c6.

The substrate holder 16c7 is a member for holding the semiconductor substrate 1, and the lower surface (substrate holding surface) of the substrate holder 16c7 in FIGS.
Is the main surface (the surface on which the seed conductor films 11a and 11b are formed)
Is held downward, for example, by vacuum suction. The substrate holder 16c7 can rotate in parallel with the main surface of the semiconductor substrate 1 in addition to the above-described vertical movement.

The processing liquid supply nozzle 16c8 is a member for spraying the reducing liquid in the form of a mist onto the main surfaces (seed conductor films 11a and 11b) of the semiconductor substrate 1 in the reduction processing. 24 (in a direction parallel to the main surface of the semiconductor substrate 1). Further, the processing liquid supply nozzle 16c8 may be used as follows. That is, after the plating process is performed, the conductor films 13a, 13
The liquid for forming the oxidation-suppressing film may be sprayed on the surface of b through the processing liquid supply nozzle 16c8. This makes it possible to suppress oxidation of the surfaces of the conductor films 13a and 13b. The plating material electrode 16
c9 is the plating material electrode 15 of the plating apparatus 15.
Since it corresponds to b, the description is omitted.

In such a plating section 16c,
During the reduction process, the semiconductor substrate 1 is rotated while the substrate holder 16c7 is rotated in parallel with the main surface of the semiconductor substrate 1.
The reducing liquid is sprayed from the tip of the processing liquid supply nozzle 16c8 onto the surface on which the shield conductor films 13a and 13b are formed. Thereby, the shield conductor film 11a,
The oxide film on the surface of 11b is removed.

In the subsequent plating process, the rotation of the substrate holder 16c7 is stopped, and the processing liquid supply nozzle 16c8 is moved away from the vertical movement path of the substrate holder 16c7 in FIG.
24, the substrate holder 16c7 is lowered as shown in FIG. 24 until the semiconductor substrate 1 on the lower surface of the substrate holder 16c7 fits into the step of the chamber wall 16c3. This allows
The shield conductor films 11a and 11b on the main surface of the semiconductor substrate 1 are electrically connected to the contact terminals 20, and the openings 18 are formed.
Block c. In this state, the plating solution flows into the plating chamber 16c3 through the inflow pipe 21c. At this time, the plating solution flows to such an extent that the plating solution comes into contact with the seed conductor films 11a and 11b of the semiconductor substrate 1. Thereafter, by applying a predetermined voltage to the contact terminal 20 and the plating material electrode 16c9 as described above, the seed conductor films 11a, 11b
The conductor films 13a and 13b are grown thereon.

FIGS. 25 and 26 show a modification of the semiconductor manufacturing apparatus, and show a structure in which the semiconductor substrate 1 is processed with its main surface facing upward. The hatching in FIG. 26 indicates a plating solution. In this semiconductor manufacturing apparatus, the reduction processing chamber and the plating processing chamber are upside down as compared with the structure of FIGS.
The difference is that the plating solution is supplied from above, and the reduction process and the plating process are performed with the main surface of the semiconductor substrate 1 facing upward. Otherwise, the description is omitted because it is the same. In the plating section 16c shown in FIGS. 24 to 26, the substrate holder 16c7 moves up and down. However, the plating chamber side may move up and down.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say,

For example, in the above embodiment, the case where the seed conductor films (11a, 11b) for forming the wiring are made of a copper-based (copper or copper alloy) material has been described, but the present invention is not limited to this. For example, the present invention can be applied to silver (Ag) or platinum (Pt).

In the above embodiment, after the barrier conductor film and the seed conductor film are formed in this order, a reduction treatment is performed.
Although the case where the plating process is performed has been described,
The present invention is not limited to this, and various changes can be made. For example, after a barrier conductor film is formed, a reduction treatment is performed, and then, the conductor film can be formed by a plating method. This is achieved by adding an active metal (catalyst) to the barrier conductor film.
This is an example in which a seed conductor film is not required. Alternatively, after forming the seed conductor film directly without forming the barrier conductor film, a reduction treatment may be performed and a plating treatment may be performed. In any case, since the growth surface of the plated conductor film can be activated, the plated conductor film can be favorably formed.

In the above description, the invention made mainly by the present inventor is described in the field of application MIS which is the background of the application.
The case where the present invention is applied to a semiconductor device technology having an FET has been described. However, the present invention is not limited to this. For example, the present invention can be applied to a semiconductor device technology having another semiconductor element such as a bipolar transistor. Of course, DRAM
(Dynamic Random Access Memory), SRAM (Static
Random Access Memory) or flash memory (E
EPROM (Electrically Erasable Programmable RO
The present invention can be applied to semiconductor memory products such as M)) and logic circuit products such as microprocessors.

[0067]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, prior to forming a conductor film for forming a wiring by plating, a reduction treatment is performed to activate the growth surface of the conductor film. Therefore, the conductive film can be favorably grown.

(2) According to the present invention, prior to forming the wiring conductor film by plating, the seed conductor film is subjected to a reduction treatment so that the thickness of the seed conductor film is maintained. Since the oxide film on the surface of the seed conductor film can be removed and the active surface of the seed conductor film can be exposed, the conductor film can be favorably grown on the seed conductor film. For this reason, it is possible to suppress the occurrence of voids and the like in the conductive film in the wiring groove, and it is possible to satisfactorily embed the plated conductive film in the wiring groove. As a result, the occurrence rate of wiring connection failure can be reduced, and fluctuation and increase in wiring resistance can be suppressed. Therefore, the yield and reliability of the semiconductor device can be improved.

(3) According to the present invention, prior to the reduction treatment, the seed conductor film is subjected to heat treatment, plasma treatment or light irradiation treatment in an oxidizing atmosphere, so that the seed conductor film is deposited on the seed conductor film. Organic matter can be removed. Therefore, the growth failure of the plated conductor film due to the organic substance can be suppressed, and the conductor film can be favorably grown on the seed conductor film. For this reason, it is possible to suppress the occurrence of voids and the like in the conductive film in the wiring groove, and it is possible to satisfactorily embed the plated conductive film in the wiring groove. As a result, the occurrence rate of wiring connection failure can be reduced, and fluctuation and increase in wiring resistance can be suppressed. Therefore, the yield and reliability of the semiconductor device can be improved.

(4) According to the present invention, after the seed conductor film is formed on the barrier conductor film, an oxidation suppressing film is formed on the surface thereof, and after removing the oxidation suppressing film, the seed film is removed. By forming the conductive film on the conductive film by the plating method, the conductive film can be grown on the active surface of the seed conductive film without the oxide film by the plating method. Therefore, the conductive film is favorably grown on the seed conductive film. be able to. For this reason, it is possible to suppress the occurrence of voids and the like in the conductive film in the wiring groove, and it is possible to satisfactorily embed the plated conductive film in the wiring groove. As a result, the occurrence rate of wiring connection failure can be reduced, and fluctuation and increase in wiring resistance can be suppressed. Therefore, the yield and reliability of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor device according to an embodiment of the present invention during a manufacturing step thereof;

FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1;

3A is a cross-sectional view of a main part of the semiconductor device during a manufacturing step following that of FIG. 2, and FIG. 3B is an enlarged cross-sectional view of the main part of FIG.

4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3;

FIG. 5 is an enlarged sectional view of a main part of FIG.

6 is an enlarged cross-sectional view of a main part of the semiconductor device after a predetermined time has elapsed after the step of FIG. 5;

FIG. 7 is an enlarged cross-sectional view of a main part after a manufacturing step of the semiconductor device after the reduction process, following FIG. 6;

8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7;

FIG. 9 is an enlarged sectional view of a main part of FIG.

10 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8;

11 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 10;

12 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 11;

13 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12;

14 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 13;

15 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 14;

16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15;

17 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 16;

18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 17;

FIGS. 19A and 19B are explanatory diagrams of a plating apparatus used during a manufacturing process of a semiconductor device.

FIG. 20 is an explanatory diagram of a configuration of a semiconductor manufacturing apparatus used during a manufacturing process of a semiconductor device according to an embodiment of the present invention;

FIG. 21 is a specific explanatory view of the semiconductor manufacturing apparatus of FIG. 20;

FIG. 22 is another specific explanatory view of the semiconductor manufacturing apparatus used during the manufacturing process of the semiconductor device according to one embodiment of the present invention;

FIG. 23 is an explanatory diagram of a plating section applicable to the semiconductor manufacturing apparatus of FIG. 22;

FIG. 24 is an explanatory diagram of a plating section in FIG. 23;

FIG. 25 is an explanatory diagram of another plating section applicable to the semiconductor manufacturing apparatus of FIG. 22;

FIG. 26 is an explanatory diagram of the plating section of FIG. 25;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2P p well 2N n well 3 Separation part 3a Separation groove 3b Separation film 4nd Semiconductor region 4pd Semiconductor region 4i Gate insulating film 4g Gate electrode 5a-5d Interlayer insulating film 6a-6d Connection hole 7 Plug 8a-8c Insulating film 9a , 9a1 to 9a3 Wiring groove 10a, 10b Barrier conductive film 11a, 11b Seed conductive film 12 Oxide film 13a, 13b Conductive film 14a, 14b Embedded wiring 15 Plating apparatus 15a Plating liquid tank 15a1 Liquid tank wall 15a2 Shielding member 15b Plating material Electrode 15c DC power supply 15d Contact terminal 16 Semiconductor manufacturing equipment 16a Positioning processing section 16b Preprocessing section 16c Plating processing section 16c1 to 16c3 Room wall 16c4 Reduction processing chamber 16c5 Plating processing outer chamber 16c6 Plating processing chamber 16c7 Substrate holder 16c8 Processing liquid supply nozzle 1 c9 plated material electrodes 16d washing / drying processing unit 16e transfer chamber 16e1 transfer robot 17 cassette 18a~18d opening 19 the shield member 20 contact terminals 21a drain pipe 21b drain pipe 21c inflow pipe L active region

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Hiji Yamaguchi, Inventor Device Development Center, Hitachi, Ltd. 6-16, Shinmachi, Ome City, Tokyo (72) Inventor Nobuo Owada 6-16, Shinmachi, Ome City, Tokyo F-term in Hitachi, Ltd. Device Development Center Co., Ltd. (Reference) 4K024 BB12 CB01 CB04 CB08 CB19 GA16 4M104 BB01 CC01 DD06 DD22 DD37 DD43 DD52 DD86 FF16 FF22 GG10 5F033 HH11 HH12 HH19 HH21 HH32 JJ11 JJ11 JJ11 JJ11 JJ11 JJ11 JJ11 JJ01 JJ11 JJ11 JJ11 JJ11 JJ11 JJ11 JJ11 JJ11 JJ11 JJ11 JJ11 JJ11 KK12 KK19 KK21 KK32 KK34 MM01 MM02 MM12 MM13 NN06 NN07 PP06 PP15 PP27 PP28 QQ09 QQ11 QQ28 QQ37 QQ48 QQ53 QQ92 RR04 RR06 SS11 SS21

Claims (12)

[Claims] 1. A method for manufacturing a semiconductor device, comprising a step of forming a conductor film for forming a wiring of a semiconductor device by a plating method after the reduction treatment. (A) forming a barrier conductor film;
(B) forming a seed conductor film on the barrier conductor film, (c) performing a reduction treatment on the seed conductor film, and (d) forming a seed conductor film on the seed conductor film after the (c) step. Forming a conductive film by a plating method. 3. A step of forming a wiring groove in the insulating film, a step of forming a barrier conductive film on the insulating film and in the wiring groove, and a step of forming a seed on the barrier conductive film. Forming a conductive film, (d) performing a reduction treatment on the seed conductive film, and (e) forming a conductive film on the seed conductive film after the (d) process by a plating method. And (f) shaving the conductor film to form a buried wiring in the wiring groove. 4. A step of (a) forming a wiring groove and a connection hole in an insulating film; (b) a step of forming a barrier conductor film on the insulating film, in the wiring groove and in the connection hole; Forming a seed conductor film on the barrier conductor film; (d)
Performing a reduction treatment on the seed conductor film;
(E) a step of forming a conductor film on the seed conductor film after the step (d) by plating, and (f) shaving the conductor film to form a buried wiring in the wiring groove and the connection hole. And a method for manufacturing a semiconductor device. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the reduction treatment is a treatment of performing a heat treatment, a plasma treatment, or a light irradiation treatment in a reducing atmosphere. Semiconductor device manufacturing method. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the gas used for forming the reducing atmosphere is hydrogen or ammonia. Method. 7. The method for manufacturing a semiconductor device according to claim 1, wherein said reducing treatment is a treatment in which said seed conductor film is immersed in a reducing liquid, and said reducing liquid is vaporized by spraying. A process of spraying the seed conductor film or immersing the seed conductor film in a vapor phase atmosphere formed by boiling the reducing liquid. 8. A method for manufacturing a semiconductor device, wherein the reducing liquid according to claim 7 is L-ascorbic acid or formaldehyde. 9. A heat treatment, a plasma treatment, or a light irradiation treatment on the seed conductor film in an oxidizing atmosphere prior to the reduction treatment according to claim 1, 2, 3, 4, 5, 6, 7, or 8. A method for manufacturing a semiconductor device, comprising a step of applying. 10. A step of forming a barrier conductor film, (b) a step of forming a seed conductor film on the barrier conductor film, and (c) forming an oxidation suppressing film on the surface of the seed conductor film. And (d) forming a conductive film on the seed conductive film by a plating method after removing the oxidation suppressing film. 11. The method for manufacturing a semiconductor device according to claim 10, wherein said oxidation suppressing film is benzotriazole. 12. The method of claim 1, 2, 3, 4, 5, 6, 7,
12. The method for manufacturing a semiconductor device according to 8, 9, 10 or 11, wherein the conductive film formed by the plating method is made of Cu,
A method for manufacturing a semiconductor device, comprising Ag and Pt.