JP2006156486A - Substrate processing method and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reliable semiconductor device wherein holes, trenches, etc. can be formed with high accuracy without requiring a process such as Ar sputtering which gives heavy damage. <P>SOLUTION: An interlayer dielectric 207 is etched with a resist pattern 208 as a mask, and then an insulation film 206 for preventing Cu diffusion is etched to form a concave portion 220 to expose a lower-layer interconnection 205. Next, a plasma treatment is carried out using a treatment gas containing either hydrogen, nitrogen, or oxygen to delaminate the resist pattern 208 and remove impurities mixed in a surface layer of Cu. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a substrate processing method and a semiconductor device manufacturing method, and more particularly, in a semiconductor device manufacturing, a substrate processing method and a semiconductor device manufacturing characterized by forming a hole and a wiring groove for connecting wirings. Regarding the method.

  In manufacturing a semiconductor device, contact plugs for wiring connection and vias / wirings in Cu wiring are generally formed by forming holes and grooves in an interlayer insulating film and then embedding metal. In particular, a Cu wiring embedding method is known as a damascene process (for example, Patent Document 1). Therefore, a conventional method will be described by taking as an example a case where wiring is formed by a single damascene process.

  First, a Cu diffusion preventing insulating film made of SiC, SiN or the like and an interlayer insulating film are deposited and formed on the lower layer wiring. Next, a resist pattern corresponding to the groove pattern formed in the interlayer insulating film is formed on the interlayer insulating film. Thereafter, using this resist pattern as a mask, the interlayer insulating film is etched to form a wiring groove pattern in the interlayer insulating film. At this stage, the Cu diffusion preventing insulating film is not removed.

  Next, after removing the resist and performing a cleaning process for removing the residue, etching of the Cu diffusion preventing insulating film is performed to expose the lower wiring metal composed of Cu or the like. Thereafter, cleaning is performed to remove residues remaining on the surface by etching of the Cu barrier insulating film, and a barrier metal and Cu are formed into a groove pattern by sputtering, PVD (Physical Vapor Deposition), or electroplating. Embed in. Thereafter, excess Cu is removed and planarization is performed to form metal wiring.

As described above, in the conventional technique, the resist is removed before the lower wiring metal such as Cu is exposed, and damage such as oxidation of the lower wiring metal due to the resist peeling process is prevented. However, in this procedure, after etching the Cu diffusion preventing insulating film, cleaning is the only process for removing the residue left on the Cu surface, which is the exposed lower wiring metal. For this reason, the impurity elements made of carbon and fluorine implanted into the Cu surface cannot be completely removed, and these impurities are removed using a physical impact such as Ar sputtering as a pretreatment prior to the deposition of the barrier metal. The process to do was inserted.
JP 2000-114368 A (FIG. 11 etc.)

The conventional damascene technology has the following problems.
After etching the Cu diffusion prevention insulating film, the residue left on the upper part of the Cu, which is the exposed lower wiring metal, can be removed by cleaning, but the impurities implanted in the Cu surface layer cannot be completely removed. Therefore, a process of cleaning the Cu surface using a physical impact such as Ar sputtering treatment before barrier metal deposition is required. In this Ar sputtering process, there is a problem of shape deterioration (so-called shoulder drop) in which the upper part of the formed hole or groove pattern is scraped, and causes of poor via resistance due to reattachment of the scraped particles to the Cu surface. There were problems such as becoming. Also, during the Ar sputtering process, Cu, which is the lower wiring metal, is sputtered and reattached to the hole and groove pattern, thereby deteriorating the adhesion and film quality (orientation, etc.) of the barrier metal to be formed later, There has also been a problem of reducing the reliability of the wiring. The Ar sputter process itself has been optimized in the direction to reduce the physical impact as much as possible, but the impact is alleviated and the impurities implanted in the Cu surface layer that is the exposed lower layer metal are removed. Efficiency has a trade-off relationship, and selection of optimum conditions has been difficult in practice.

  In addition, Ar sputtering treatment, when a low dielectric constant insulating film is used as an interlayer insulating film, causes damage by destroying the structure of the surface of the low dielectric constant interlayer film exposed on the side wall or the like. There has been a problem in that the generation, adhesion, and electrical characteristics of the insulating film are deteriorated.

  Furthermore, after removing the resist pattern, a process for etching the diffusion preventing insulating film is performed, so that a strong residue by etching remains on the exposed surface, and the cleaning chemical used for removing these remains powerful. Necessary. Therefore, the film shape changes due to this cleaning process, and particularly when a low dielectric constant interlayer insulating film is used, the adhesion changes and the electrical characteristics deteriorate due to the structural change due to the chemical reaction. Was inviting problems.

  Furthermore, since etching is performed in the absence of a resist pattern, the shape of the formed hole or groove pattern deteriorates during the etching of the diffusion preventing insulating film, and the accuracy of the shape of the hole or groove is impaired. There is also. This problem of pattern deterioration may occur not only in the damascene process but also in the case where, for example, a contact is formed on the gate electrode of a transistor.

  The present invention has been made in order to solve the above-described problems, and does not require a large damage process such as an Ar sputtering process, and can form holes and grooves with high accuracy. It is an object of the present invention to provide a processing method and a manufacturing method of a semiconductor device capable of manufacturing a highly reliable semiconductor device.

In order to solve the above problems, the present invention provides the following (1) to (24).
(1) At least a connected portion connected to another part on the substrate, an etched layer formed thereon, and a mask layer formed on the etched layer and patterned, A concave portion corresponding to the pattern of the mask layer is formed in the etched layer by etching, and the substrate to be processed has a structure in which the connected portion is exposed in the concave portion.
Substrate processing characterized by performing plasma treatment using plasma of a gas containing at least one of hydrogen, nitrogen, and oxygen to remove the mask layer and remove impurities mixed in the connected portion Method.
(2) The substrate processing method according to (1), wherein the connected portion is a metal wiring embedded in a wiring layer below the etching target layer.
(3) The substrate processing method according to (1), wherein the connected portion is a source / drain region or a gate electrode of a transistor.
(4) The substrate processing method according to any one of (1) to (3), wherein the plasma processing is performed while applying a bias voltage to a support on which a substrate to be processed is placed.

(5) forming a lower layer metal wiring on the substrate;
Forming an interlayer insulating film on the lower metal wiring;
Forming a resist having an opening pattern on the interlayer insulating film;
Etching using the resist as a mask, forming a recess in the interlayer insulating film, exposing the lower layer metal wiring,
Removing the resist;
Cleaning the surface of the substrate after removing the resist;
A method for manufacturing a semiconductor device, comprising:
(6) In the step of removing the resist, plasma treatment is performed in which plasma of a gas containing at least one of hydrogen, nitrogen, and oxygen is used to remove the resist and remove impurities mixed in the lower metal wiring. (5) The method for manufacturing a semiconductor device according to (5) above.
(7) The semiconductor according to (5) or (6) above, further including a step of recovering crystal defects of the lower layer metal wiring exposed in the recess after the step of cleaning the surface of the substrate. Device manufacturing method.
(8) In the step of recovering crystal defects in the lower layer metal wiring, heat treatment is performed at a temperature of 100 ° C. to 450 ° C. in a gas atmosphere containing at least one of hydrogen and nitrogen. 7) A method for manufacturing a semiconductor device.
(9) The semiconductor device according to (8), further including a step of cleaning the surface of the lower layer metal wiring exposed in the concave portion after the step of recovering crystal defects of the lower layer metal wiring. Production method.
(10) The method for manufacturing a semiconductor device according to (9), wherein, in the step of cleaning the surface of the lower metal wiring, the oxide film formed on the exposed surface of the lower metal wiring is reduced.
(11) After the step of cleaning the surface of the lower layer metal wiring, the method further includes the step of forming a multilayer metal wiring by depositing a barrier metal layer and a conductor layer in the recess formed in the interlayer insulating film. The method for manufacturing a semiconductor device according to (10), characterized in that it is characterized in that

(12) forming a lower layer metal wiring on the substrate;
Forming an interlayer insulating film on the lower metal wiring;
Forming a first resist having an opening pattern on the interlayer insulating film;
Etching using the first resist as a mask, forming a first recess in the interlayer insulating film, and exposing the lower layer metal wiring;
Removing the first resist;
Forming a second resist having an opening pattern on the interlayer insulating film;
Etching using the second resist as a mask to form a second recess in the interlayer insulating film;
Removing the second resist;
Cleaning the surface of the substrate after removing the resist;
A method for manufacturing a semiconductor device, comprising:
(13) In the step of removing the first resist and / or the second resist, plasma of a gas containing at least one of hydrogen, nitrogen, and oxygen is used to remove the resist and the lower layer metal wiring (12) The method for manufacturing a semiconductor device according to (12), wherein plasma treatment is performed to remove impurities mixed in the semiconductor device.
(14) The step (12) or (13) further comprising a step of recovering crystal defects of the lower layer metal wiring exposed in the second recess after the step of cleaning the surface of the substrate. ) Semiconductor device manufacturing method.
(15) In the step of recovering crystal defects of the lower layer metal wiring, heat treatment is performed at a temperature of 100 ° C. to 450 ° C. in a gas atmosphere containing at least one of hydrogen and nitrogen. 14) A method for manufacturing a semiconductor device.
(16) After the step of recovering crystal defects in the lower layer metal wiring, the method further includes a step of cleaning the surface of the lower layer metal wiring exposed in the second recess. A method for manufacturing a semiconductor device.
(17) The method for manufacturing a semiconductor device according to (16), wherein, in the step of cleaning the surface of the lower metal wiring, the oxide film formed on the exposed surface of the lower metal wiring is reduced.
(18) After the step of cleaning the surface of the lower layer metal wiring, a barrier metal layer and a conductor layer are further deposited in the first recess and the second recess formed in the interlayer insulating film to form a multilayer The method for manufacturing a semiconductor device according to (17), further comprising a step of forming a metal wiring.

(19) a plasma supply source for generating plasma;
A processing container for partitioning a processing chamber for performing plasma processing on an object to be processed by the plasma;
A support for placing the object to be processed in the processing container;
An exhaust means for decompressing the inside of the processing vessel;
Gas supply means for supplying gas into the processing vessel;
A control unit that controls the substrate processing method of any one of (1) to (4) to be performed;
A plasma processing apparatus comprising:
(20) A control program that operates on a computer and controls the plasma processing apparatus so that the substrate processing method according to any one of (1) to (4) is performed at the time of execution.
(21) A computer storage medium storing a control program that runs on a computer,
A computer storage medium characterized in that, when executed, the control program controls a plasma processing apparatus used in any of the substrate processing methods (1) to (4).

(22) A plasma processing apparatus that performs plasma processing on a substrate, a film forming apparatus that performs a film forming process, a resist coating / developing apparatus that performs a resist coating process and a developing process, an exposure apparatus that performs an exposure process, and a heat treatment The semiconductor device manufacturing method according to any one of the above (5) to (18) is performed using the heat treatment apparatus for performing the above, the cleaning apparatus for performing the cleaning process, the polishing apparatus for performing the polishing process, and these apparatuses. And a control unit for controlling the semiconductor device.
(23) Control that operates on a computer and controls a plurality of semiconductor manufacturing apparatuses so that the semiconductor device manufacturing method according to any one of (5) to (18) is performed at the time of execution. program.
(24) A computer storage medium storing a control program that runs on a computer,
A computer storage medium characterized in that, when executed, the control program controls a plurality of semiconductor manufacturing apparatuses used in the method for manufacturing a semiconductor device according to any one of (5) to (18).

In the present invention, at least a connected portion connected to another region on the substrate, an etched layer formed thereon, and a mask layer such as a resist formed and patterned on the etched layer, The substrate to be processed is first etched to form a recess corresponding to the pattern of the mask layer, and then the connected portion is exposed, and then the plasma treatment is performed to remove the mask layer and simultaneously perform the etching process. It is possible to remove the impurities mixed in the surface layer by being driven into the connected portion exposed in step (1). By removing impurities at this stage, a method involving physical impact such as Ar sputtering is not required in the subsequent process. Also, Cu and other deposits scattered during the plasma treatment can be easily removed by subsequent wet cleaning, so there is no obstacle to adhesion to the barrier metal, and the cleaning itself is performed under mild conditions. it can.
Therefore, for example, when forming a via or wiring by a damascene process, or when forming a contact on a diffusion region called a source / drain of a transistor or a gate electrode, the resistance is low and the yield is high and the reliability is high. Multi-layer wiring can be formed. Further, the total number of steps can be substantially reduced, which can contribute to a reduction in manufacturing cost.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
First, the outline of the invention will be described by taking as an example the case where the present invention is applied to a damascene process. FIG. 1 is an example showing a processing flow of a single damascene process. In this example, steps S101 to S111 are shown as typical steps of the single damascene process.

  First, in step S101, a Cu diffusion preventing insulating film is formed on a semiconductor substrate or the like in a state where Cu is embedded and a lower metal wiring is formed. Next, in step S102, an interlayer insulating film is formed on the Cu diffusion preventing insulating film, and in step S103, a resist pattern corresponding to a via or a trench is formed using, for example, a photolithography technique.

  In step S104, the interlayer insulating film is etched using the resist pattern formed in step S103 as a mask to form a recess (opening). This etching is performed until the Cu surface of the lower layer metal wiring is exposed. Next, in the plasma processing step of step S105, plasma processing is performed under a predetermined condition using a plasma processing apparatus as will be described later, and resist removal (ashing) is performed. In this step S105, simultaneously with the removal of the resist, plasma acts on the exposed Cu surface, so that impurities such as C and F implanted in the Cu surface layer during the etching in step S104 are removed.

  Subsequently, in step S106, wet cleaning is performed to remove deposits on the substrate surface. At this time, Cu or the like adhering to the side wall of the recess is also removed by the sputtering action in the plasma processing in step S105.

  After cleaning, annealing (heat treatment) is performed in step S107 to recover the crystal disorder (crystal defects) in the surface layer of the lower metal wiring generated in the plasma processing in step S105. Further, in step S108, prior to the formation of the barrier metal, the oxide film formed on the surface of the lower layer metal wiring is reduced and cleaned. Steps S107 and S108 are optional steps that can be performed as necessary.

  Next, in step S109, a barrier metal is formed in the recess formed by the etching in step S104. In step S110, Cu as a conductor is embedded. In step S111, for example, CMP (Chemical Mechanical Polishing); Perform planarization by

  Next, a case where the present invention is applied to a dual damascene process will be described as an example. FIG. 2 is an example showing a processing flow of a dual damascene process. In this example, steps S201 to S214 are shown as typical steps of the dual damascene process. Among these steps, steps S201 to S203 and steps S212 to S214 are common to the single damascene process of FIG. The description is omitted here.

  In step S204, the interlayer insulating film is etched using the first resist pattern formed in step S203 as a mask to form a first recess (opening). This etching is performed until the Cu surface of the lower layer metal wiring is exposed. Next, in the first plasma processing step of step S205, plasma processing is performed under a predetermined condition using a plasma processing apparatus as will be described later, and resist removal (ashing) is performed. In this step S205, simultaneously with the removal of the resist, plasma acts on the exposed Cu surface, thereby removing impurities such as C and F implanted into the Cu surface layer during the etching in step S204.

Subsequently, in step S206, a second resist pattern corresponding to the via and the groove is formed by photolithography. Next, in step S207, the interlayer insulating film is etched using the second resist pattern formed in step S206 as a mask to form a second recess (opening). Usually, this 2nd recessed part is formed in cross sectional view substantially T-shape.
Next, in the second plasma processing step of step S208, plasma processing is performed using a plasma processing apparatus as will be described later, and the resist is stripped (ashed) under predetermined conditions. In step S208, not only the resist is removed, but also plasma acts on the exposed Cu surface, so that impurities such as C and F implanted in the Cu surface layer during the etching in step S207 are removed.

  Subsequently, in step S209, wet cleaning is performed to remove deposits on the substrate surface. At this time, Cu or the like adhering to the side wall of the recess is also removed by the sputtering action in the second plasma processing in step S208.

  After cleaning, annealing (heat treatment) is performed in step S210 to recover crystal disorder (crystal defects) in the lower metal wiring surface layer generated in the plasma processing in steps S205 and S208. Furthermore, in step S211, prior to the formation of the barrier metal, the oxide film formed on the surface of the lower metal wiring is reduced and cleaned. Steps S210 and S211 are optional steps that can be performed as necessary.

  Next, in step S212, a barrier metal is formed in the second recess formed as described above. In step S213, Cu as a conductor is buried, and in step S214, planarization is performed by, for example, CMP. The dual damascene process is performed through the above series of steps.

  Thus, the present invention can be applied to a dual damascene process as well as a single damascene process. Here, a damascene process for embedding a Cu film is taken as an example, but the present invention can also be applied to a process using other metals such as an Al film and a W film.

FIG. 3 is a diagram showing a configuration of a semiconductor device manufacturing system 100 that can be suitably used in applying the method of the present invention to a damascene process, for example, according to the procedure shown in FIGS. 1 and 2. The semiconductor device manufacturing system 100 includes a plasma processing apparatus 101 that combines an etching apparatus that performs etching with plasma and an ashing apparatus that performs ashing on a semiconductor substrate, a sputtering method, a PVD method, a CVD method, an electroplating method, and the like. A film forming apparatus 102 for performing a film, a resist coating / developing apparatus 103 having a coater and a developer for performing resist coating / developing in a photolithography process, an exposure apparatus 104 for performing exposure processing in a photolithography process, and heat treatment A heat treatment apparatus 105 for performing (annealing or baking), a cleaning apparatus 106 for performing wet cleaning with a chemical solution, a processing unit 110 including a polishing apparatus 107 for performing CMP, a process controller 111, and a user interface 1 2, and a main control unit 120 including a storage unit 113.
In addition, as a plasma processing apparatus 101, a film forming apparatus 102, a resist coating / developing apparatus 103, an exposure apparatus 104, a heat treatment apparatus 105, a cleaning apparatus 106, and a polishing apparatus 107, apparatuses having known configurations can be used without any particular limitation. In addition, each device of the processing unit 110 does not mean a single device. For example, in the case of the film forming device 101, a plurality of devices such as a plasma CVD device, a thermal CVD, a PVD device, and an electroplating device are used. Used to include devices.

  Each device of the processing unit 110 is connected to and controlled by a process controller 111 having a CPU. The process controller 111 includes a keyboard that allows a process manager to input commands to manage each device of the processing unit 110, a display that visualizes and displays the operating status of each device of the processing unit 110, and the like. A user interface 112 is connected to a storage unit 113 that stores a recipe in which a control program and processing condition data for realizing various processes executed by the processing unit 110 are controlled by the process controller 111. ing.

Then, if necessary, the processing unit 110 receives an instruction from the user interface 112, calls an arbitrary recipe from the storage unit 113, and causes the process controller 111 to execute the desired recipe under the control of the process controller 111. Various processes are performed. In addition, for example, the recipe may be stored in a readable storage medium such as a CD-ROM, a hard disk, a flexible disk, or a nonvolatile memory, or between recipes in the processing unit 110, or It is also possible to transmit the data from an external device as needed via, for example, a dedicated line and use it online.
Note that the overall control by the main control unit 120 is not performed, or a control including a process controller, a user interface, and a storage unit for each device of the processing unit 110 in a manner superimposed on the overall control by the main control unit 120. It is also possible to adopt a configuration in which the parts are individually deployed.

The present invention is characterized by a plasma processing step performed after the etching step in the processing procedure of FIGS. 1 and 2, for example. Therefore, hereinafter, the etching process and the plasma processing process will be described in detail together with the configuration of the plasma processing apparatus 101.
4 shows an etching process (for example, step S104 in FIG. 1, step S204 in FIG. 2, step S207) and a plasma processing process (for example, step S105 in FIG. 1, step S205 in FIG. 2, step S208) in the method of the present invention. ) Schematically shows a configuration example of a plasma processing apparatus that can be suitably used for the implementation of (1). The plasma processing apparatus 101 is configured as a capacitively coupled parallel plate type plasma processing apparatus in which electrode plates face each other in parallel in the vertical direction and a high frequency power source is connected to both of them.

  The plasma processing apparatus 101 has a chamber 2 formed into a cylindrical shape made of, for example, aluminum whose surface is anodized (anodized), and the chamber 2 is grounded. In the chamber 2, a wafer W made of, for example, silicon and having a predetermined film formed thereon as a substrate to be processed is horizontally placed, and a susceptor 5 that functions as a lower electrode is supported by the susceptor support 4. It is provided in the state. A high pass filter (HPF) 6 is connected to the susceptor 5.

  A temperature control medium chamber 7 is provided inside the susceptor support 4, and the temperature control medium is introduced into the temperature control medium chamber 7 through the introduction pipe 8 and circulated so that the susceptor 5 can be controlled to a desired temperature. It is like that.

  The upper center portion of the susceptor 5 is formed into a convex disk shape, and an electrostatic chuck 11 having substantially the same shape as the wafer W is provided thereon. The electrostatic chuck 11 has a configuration in which an electrode 12 is interposed between insulating materials. When a DC voltage of, for example, 1.5 kV is applied from a DC power source 13 connected to the electrode 12, the electrostatic chuck 11 is subjected to Coulomb force. The wafer W is electrostatically adsorbed.

  The insulating plate 3, the susceptor support 4, the susceptor 5, and the electrostatic chuck 11 are heated to a predetermined pressure (back pressure) with a heat transfer medium, such as He gas, on the back surface of the wafer W, which is the substrate to be processed. A gas passage 14 is formed for supply, and heat transfer is performed between the susceptor 5 and the wafer W via the heat transfer medium so that the wafer W is maintained at a predetermined temperature. .

  An annular focus ring 15 is disposed at the upper peripheral edge of the susceptor 5 so as to surround the wafer W placed on the electrostatic chuck 11. The focus ring 15 is made of an insulating material such as ceramics or quartz and acts to improve the uniformity of the plasma processing.

  An upper electrode 21 is provided above the susceptor 5 so as to face the susceptor 5 in parallel. The upper electrode 21 is supported on the upper portion of the chamber 2 via an insulating material 22, constitutes a surface facing the susceptor 5, and has a number of discharge holes 23, for example, an electrode plate 24 made of aluminum, The electrode plate 24 is composed of a conductive material, for example, an electrode support 25 made of aluminum whose surface is anodized. The interval between the susceptor 5 and the upper electrode 21 can be adjusted.

A gas introduction port 26 is provided at the center of the electrode support 25 in the upper electrode 21, and a gas supply pipe 27 is connected to the gas introduction port 26. Further, a valve is connected to the gas supply pipe 27. 28 and a mass flow controller 29 are connected to a processing gas supply source 30, and a processing gas for etching and resist stripping (ashing) is supplied from the processing gas supply source 30. In FIG. 4, only one processing gas supply source 30 is representatively illustrated. However, a plurality of processing gas supply sources 30 are provided, and a plurality of types of gases are independently flow controlled, It is configured so that it can be supplied into the chamber 2. Here, as the etching gas, for example, C ₄ F ₈ , C ₅ F ₈ , CF ₄ , CHF ₃ , CH ₂ F ₂ , CH ₃ F, etc., and these, N ₂ , Ar, O ₂ , He, etc. A mixed gas or the like can be used. As the ashing gas, for example, a gas containing hydrogen, nitrogen, or oxygen, specifically, CO, CO ₂ , N ₂ , H ₂ , O ₂ , NH _3, or a mixed gas thereof, or the above-described gas A gas and a mixed gas of He, Ar, or the like can be used.

  An exhaust pipe 31 is connected to the bottom of the chamber 2, and an exhaust device 35 is connected to the exhaust pipe 31. The exhaust device 35 includes a vacuum pump such as a turbo molecular pump, and is configured so that the inside of the chamber 2 can be evacuated to a predetermined reduced pressure atmosphere, for example, a predetermined pressure of 1 Pa or less. Further, a gate valve 32 is provided on the side wall of the chamber 2 so that the wafer W is transferred to and from an adjacent load lock chamber (not shown) with the gate valve 32 opened. It has become.

  A first high frequency power supply 40 is connected to the upper electrode 21, and a matching unit 41 is provided on the feeder line. Further, a low pass filter (LPF) 42 is connected to the upper electrode 21. The first high-frequency power supply 40 has a frequency in the range of 50 to 150 MHz, and forms a high-density plasma in a preferable dissociated state in the chamber 2 by applying such a high frequency. And plasma processing under low-pressure conditions is possible. The frequency of the first high frequency power supply 40 is preferably 50 to 80 MHz, and typically, a condition of 60 MHz or the vicinity thereof is adopted as shown in FIG.

  A second high frequency power supply 50 is connected to the susceptor 5 as the lower electrode, and a matching unit 51 is provided on the power supply line. The second high-frequency power supply 50 has a frequency in the range of several hundreds kHz to several tens of MHz. By applying power having a frequency in such a range, the wafer W is not damaged. Appropriate ion action can be provided. As the frequency of the second high frequency power supply 50, for example, a condition such as 13.56 MHz or 800 KHz is adopted as shown in FIG.

Next, the plasma processing apparatus 101 configured as described above can continuously perform etching and ashing on the wafer W.
First, in the etching process (step S104 in FIG. 1, step S204, step S207 in FIG. 2), the wafer W is loaded into the chamber 2 from a load lock chamber (not shown) with the gate valve 32 opened, and an electrostatic chuck. 11 is mounted. The wafer W is electrostatically adsorbed on the electrostatic chuck 11 by applying a DC voltage from the DC power source 13.

Next, the gate valve 32 is closed, and the inside of the chamber 2 is evacuated to a predetermined vacuum level by the exhaust device 35. Thereafter, the valve 28 is opened, and, for example, CF ₄ is adjusted as a processing gas for etching from the processing gas supply source 30 to a predetermined flow rate by the mass flow controller 29, while the processing gas supply pipe 27, the gas inlet 26, It is introduced into the hollow portion of the electrode 21 and is uniformly discharged onto the wafer W through the discharge holes 23 of the electrode plate 24 as indicated by arrows in FIG.

  In this etching step, the pressure in the chamber 2 is maintained at a predetermined pressure, and a predetermined high frequency is supplied from the first high frequency power supply 40 to the upper electrode 21 and from the second high frequency power supply 50 to the susceptor 5 as the lower electrode. Etching is performed based on a pattern formed on the wafer W by applying electric power and turning the processing gas into plasma.

Next, in the ashing process (the plasma process in step S105 in FIG. 1, the first plasma process in step S205 in FIG. 2, and the second plasma process in step S208), the valve 28 is opened and the process gas supply source 30 is used. As the ashing gas, a gas containing at least hydrogen, nitrogen, or oxygen, for example, N ₂ and H ₂ is adjusted to a predetermined flow rate by the mass flow controller 29, and the processing gas supply pipe 27, the gas inlet 26, the upper electrode 21 are adjusted. And is uniformly discharged onto the wafer W through the discharge holes 23 of the electrode plate 24 as indicated by arrows in FIG.

  In this ashing process, the pressure in the chamber 2 is maintained at a predetermined pressure, and a predetermined pressure is applied from the first high-frequency power source 40 to the upper electrode 21 and from the second high-frequency power source 50 to the susceptor 5 as a lower electrode. The resist is peeled off by applying high-frequency power and converting the ashing gas into plasma. At this time, it is preferable that high-frequency power is applied to the susceptor 5 so that ions generated from the plasma are accelerated and drawn into the wafer W by the generated self-bias voltage. As a result, the sputtering effect on the exposed surface of the lower layer metal wiring is strengthened, and impurities such as C and F mixed in the metal during the etching process can be efficiently removed.

Next, the present invention will be described in more detail with reference to more specific embodiments, but the present invention is not limited thereto.
<First Embodiment>
FIG. 5 shows an embodiment in which the present technology is applied to a single damascene process.
As shown in FIG. 5A, a wiring layer 203 made of, for example, an interlayer insulating film 202 such as SiO ₂ and a low dielectric constant film HSQ (Hydrogen Siliconesquioxane) is laminated on the Si substrate 201. In 203, a Cu lower layer wiring 205 is formed through a barrier metal 204 such as a TiN film. First, in order to form an upper layer wiring, a Cu diffusion preventing insulating film 206 such as a silicon nitride film is formed on the wiring layer 203, and an interlayer insulating film 207 is deposited thereon. These steps are performed by the film forming apparatus 102.
As the interlayer insulating film 207, for example, SiO ₂ , FSG (Fluorinated Silicate Glass) obtained by adding fluorine to SiO ₂ to reduce the dielectric constant, or a low dielectric constant interlayer insulating film is used. Here, examples of the low dielectric constant interlayer film include organic films such as CDO (Carbon Doped Oxide) obtained by adding carbon to SiO ₂ and SiLK (registered trademark; manufactured by Dow Chemical Co.). Further, a hard mask (SiO ₂ , SiN, SiC, etc.) for further processing is deposited on the interlayer insulating film.

  Next, as shown in FIG. 5B, a resist pattern 208 corresponding to the via pattern is formed on the interlayer insulating film 207. The resist pattern 208 can be formed by a photolithography technique using the resist coating / developing apparatus 103, the exposure apparatus 104, the heat treatment apparatus 105, and the like.

  As shown in FIG. 5C, using the resist pattern 208 as a mask, the interlayer insulating film 207 is etched, and the Cu diffusion preventing insulating film 206 is further etched to form a recess 220, thereby exposing the lower wiring 205. At this time, a by-product due to etching exists as a residue on the wafer W, and the residue adheres to the side wall of the recess 220 constituting the pattern and the exposed Cu surface. Further, impurities such as carbon and fluorine are mixed with a certain depth in the surface layer portion of Cu exposed by etching.

Subsequently, as shown in FIG. 5D, the resist pattern 208 is peeled off. The plasma treatment process can be performed using, for example, a plasma treatment apparatus 101 and a treatment gas containing any element of hydrogen, nitrogen, or oxygen. Further, as described above, it is preferable to carry out under a bias condition that ions in the plasma composed of these gases are drawn onto the wafer W.
Further, when the process gas contains at least oxygen, it is important to select low pressure and low temperature conditions so that the exposed Cu surface is not oxidized.

  By performing the plasma treatment in this manner, it is possible to remove impurities implanted in the Cu surface layer portion of the exposed lower layer wiring 205 at the same time as the resist pattern 208 is peeled off. At the same time as the resist is stripped, the exposed Cu is sputtered and adheres to the sidewalls, which can be removed in a subsequent cleaning step.

  After the plasma treatment process, a cleaning process by wet cleaning is performed using the cleaning device 106. In the present invention, since the etching process is not performed immediately before, the wet cleaning can be performed under mild conditions, and the type of the chemical solution is not particularly limited. Therefore, it is not necessary to use a strong chemical solution. When the film shape changes due to the cleaning process, or when a low dielectric constant interlayer insulating film is used, the adhesion change or electrical It is possible to avoid the problem of deterioration of the physical characteristics.

Further, in order to recover crystal defects introduced into the Cu surface layer portion of the lower layer wiring 205, it is preferable to perform annealing following the cleaning step. Annealing can be performed at a temperature of 100 ° C. to 450 ° C. using a heat treatment apparatus 105 in a gas atmosphere containing, for example, hydrogen or nitrogen. Examples of the gas containing hydrogen and nitrogen include a mixed gas of N ₂ and H ₂ , NH ₃ , N ₂ , and H ₂ .

Next, prior to the formation of the barrier metal 209, it is preferable to perform a reduction treatment on the Cu surface of the oxidized lower wiring 205 to prepare a clean Cu surface. At this time, the Cu surface of the lower layer wiring 205 is oxidized, but since the impurities have already been removed, a method involving physical impact like the Ar sputtering process in the prior art is not required. Therefore, in this embodiment, the Cu of the oxidized lower layer wiring 205 is not caused without causing deterioration of the shape of the formed via pattern and without being sputtered and reattached to the side wall of the recess 220 by Cu of the exposed lower layer wiring 25. Reduction can be performed.
As a method of cleaning treatment (reduction treatment) of the Cu surface of the lower layer wiring 205, for example, a method of reducing in a high temperature of about 100 ° C. to 450 ° C. in a hydrogen or NH ₃ atmosphere, a chemistry with NH ₃ , HF or the like For example, a technique of reducing copper oxide by a chemical reaction. In the case where low dielectric constant insulating films are used as the interlayer insulating film, a technique that does not damage these films, for example, a technique that exposes to a reducing atmosphere at a high temperature of about 100 ° C. to 400 ° C., He, H It is preferable to select a method of exposing to a plasma atmosphere made of a gas such as ₂ .

  Then, as shown in FIG. 5E, a barrier metal 209 is formed in the concave portion 220 as a via pattern by a sputtering method, a PVD method, an electroplating method or the like using a film forming apparatus 102, and further a Cu film 210 Then, finally, planarization by CMP is performed as shown in FIG. 5F, thereby forming a multilayer wiring structure in which vias are formed.

  In the embodiment shown in FIG. 5, the case where vias are formed by a single damascene method is illustrated, but this is only one example of application of the present invention, and the same applies to the case where wiring is formed by a single damascene method. Is possible. Further, even when a hard mask is stacked on the interlayer insulating film 207, the same can be implemented. Further, the same process can be performed even when a metal diffusion prevention layer is formed on the surface of the lower wiring 205 or when the Cu diffusion prevention insulating film 206 is not provided.

Second Embodiment
FIG. 6 shows an embodiment in which the present invention is suitable for a dual damascene process. Note that description of matters common to the single damascene process of FIG. 5 is omitted as appropriate.
As shown in FIG. 6A, an interlayer insulating film 202 and a wiring layer 203 are laminated on a Si substrate 201, and a Cu lower layer wiring 205 is formed on the wiring layer 203 through a barrier metal 204. ing. First, in order to form an upper layer wiring, a Cu diffusion preventing insulating film 206 is formed on the wiring layer 203, and an interlayer insulating film 207 is deposited thereon.

  Next, as shown in FIG. 6B, a resist pattern 208 corresponding to the via pattern is formed on the interlayer insulating film 207. The resist pattern 208 can be formed by a photolithography technique.

  As shown in FIG. 6C, using the resist pattern 208 as a mask, the interlayer insulating film 207 is etched, and further, the Cu diffusion preventing insulating film 206 is etched to form a recess 221 to expose the lower layer wiring 205. At this time, a by-product due to etching exists as a residue on the wafer W, and the residue adheres to the side wall of the recess 221 constituting the pattern and the exposed Cu surface. Further, impurities such as carbon and fluorine are mixed with a certain depth in the surface layer portion of Cu exposed by etching.

Subsequently, as shown in FIG. 6D, the resist pattern 208 is peeled off. The plasma processing step can be performed using, for example, the plasma processing apparatus 101 and using a gas containing any element of hydrogen, nitrogen, or oxygen, and ions in the plasma composed of these gases are formed on the wafer W. It is preferable to carry out the conditions so as to be drawn.
Further, when the process gas contains at least oxygen, it is important to select low pressure and low temperature conditions so that the exposed Cu surface is not oxidized. As a result, it is possible to remove the impurities implanted in the Cu surface layer portion of the lower wiring 205 exposed at the same time as the resist pattern 208 is peeled off.

  Subsequently, as shown in FIG. 6E, a resist pattern 211 corresponding to the trench pattern is formed. Note that a sacrificial film (not shown) made of an inorganic material such as Si—O may be embedded in the recess 221 before the resist pattern 211 is formed. In this way, the bottom of a new recess 222 (described later) formed in the interlayer insulating film 207 when etching is performed in the next step can be made flat.

  Thereafter, etching is performed using the resist pattern 211 as a mask to form a recess 222 in the interlayer insulating film 207 as shown in FIG. Subsequently, the resist pattern 211 is removed as shown in FIG. This step can be performed, for example, using the plasma processing apparatus 101, for example, using a gas containing any element of hydrogen, nitrogen, or oxygen. Further, as described above, it is preferable to carry out the process under such a condition that ions in the plasma are attracted onto the wafer W. Further, when the process gas contains at least oxygen, it is important to select low pressure and low temperature conditions so that the exposed Cu surface is not oxidized. As a result, it is possible to remove the impurities implanted into the Cu surface layer portion of the lower layer wiring 205 exposed at the same time as the resist pattern 211 is peeled off. At the same time as the resist pattern 211 is peeled off, the exposed Cu is sputtered and adheres to the side walls, but these may be removed in a subsequent cleaning step.

  After the plasma treatment process, a cleaning process such as wet cleaning is performed using the cleaning apparatus 106. Further, in order to recover crystal defects introduced into the Cu surface layer portion of the lower layer wiring 205, it is preferable to perform annealing using the heat treatment apparatus 105 following the cleaning step.

Next, prior to the formation of the barrier metal 209, it is preferable to perform a reduction treatment on the Cu surface of the oxidized lower wiring 205 to prepare a clean Cu surface. At this time, the Cu surface of the lower layer wiring 205 is oxidized, but since the impurities have already been removed, a method involving physical impact like the Ar sputtering process in the prior art is not required. Therefore, in the present embodiment, reduction of Cu in the oxidized lower layer wiring 205 without causing deterioration of the shape of the formed via pattern and without reattaching Cu in the exposed lower layer wiring 25 to the sidewall of the recess 222 by sputtering. Can be performed.
The Cu surface cleaning process (reduction process) of the lower layer wiring 205 is the same as described above.

Next, as shown in FIG. 6 (h), a barrier metal 209 is formed in the recess 222 by sputtering, PVD, electroplating, etc., using a film forming apparatus 102, and a Cu film 210 is embedded, followed by CMP. By performing the planarization, a multilayer wiring structure in which an upper layer wiring and a via are formed is formed.
The method described here is an example of an embodiment of the present technology, and can be applied to, for example, a dual damascene forming method in which a via is formed after forming a trench groove first. Further, a case where a hard mask is stacked on the interlayer insulating film 207 can be similarly implemented. Further, the present invention can be similarly implemented even when a metal diffusion preventing film is formed on the Cu surface of the lower layer wiring 205 or when the Cu diffusion preventing insulating film 206 is not provided.

<Third Embodiment>
FIG. 7 shows an embodiment in which the present invention is applied to contact formation of a gate electrode. As shown in FIG. 7A, a source 302 and a drain 303 are formed on a Si substrate 301, and a gate insulating film 304 such as SiO ₂ and a gate electrode 305 such as polysilicon are formed to constitute a transistor. ing. A silicon nitride film 306 is deposited on the semiconductor substrate, and a silicon oxide film 307 is deposited thereon as an interlayer insulating film. Note that here, the source 302, the drain 303, and the gate electrode 305 are connected portions.

Next, as shown in FIG. 7B, a resist pattern 308 corresponding to the contact hole is formed on the silicon oxide film 307. Next, as shown in FIG. 7C, the silicon oxide film 307 and the silicon nitride film 306 are etched using the resist pattern 308 as a mask to form a recess 320 and a recess 321, and a source 302 (drain) which is a diffusion region of the transistor. 303. The same applies hereinafter) and the surface of the gate electrode 305 is exposed. At this time, by-products due to etching are present as residues on the wafer W. The residues are the side walls of the recesses 320 and 321 constituting the pattern, the exposed surface of the source 302 (drain 303), and the gate electrode 305. Adhering to the surface.
Further, impurities such as carbon and fluorine are mixed with a certain depth in the surface layer portion of the source 302 (drain 303) and the surface layer portion of the gate electrode 305 exposed by etching.

  Subsequently, the resist pattern 308 is removed as shown in FIG. This plasma processing step is performed, for example, in plasma using a plasma processing apparatus 101 using a gas containing any one element of hydrogen, nitrogen, or oxygen, and ions composed of these gases are biased on the wafer W. It is preferable to carry out under the condition of being pulled in. In the case of containing at least oxygen, it is necessary to select low-pressure and low-temperature conditions so that the exposed surface of the source 302 (drain 303) and the surface of the gate electrode 305 are not oxidized. As a result, it is possible to remove impurities implanted in the surface layer portion of the source 302 (drain 303) and the surface layer portion of the gate electrode 305 which are exposed at the same time as the resist pattern 308 is peeled off.

  At the same time as removing the resist, metal atoms and metal compounds formed on the exposed surface of the source 302 (drain 303) and the surface of the gate electrode 305, for example, Si, Ti, TiSix, Co, CoSix, Ni, NiSix, W , WSi, WNx, Ta, TaNx, TaSixNy and the like are sputtered and adhere to the side walls of the recesses 320 and 321, and these can be removed in the subsequent cleaning step.

After the plasma treatment process, a cleaning process such as wet cleaning is performed. After the cleaning step, annealing is preferably performed after the cleaning in order to recover crystal defects introduced into the surface layer portion of the source 302 (drain 303) and the surface layer portion of the gate electrode 305. The annealing can be performed in a gas atmosphere containing at least one of hydrogen and nitrogen, for example, at a temperature of 200 ° C. to 650 ° C.
The annealing temperature and annealing time are set to conditions for sufficiently reducing the resistance of silicide and metal deposited on the source 302 (drain 303) and the gate electrode 305.

Subsequently, as shown in FIG. 7E, a contact plug can be formed by embedding a metal 309 such as tungsten (W) in the formed contact hole (recessed portion 320, 321).
This embodiment is an example to which the present invention is applied. For example, the metal for forming the contact plug is not limited to tungsten, and can be applied even when another metal is embedded.

As mentioned above, although embodiment of this invention was described, this invention is not restrict | limited to the said embodiment, A various deformation | transformation is possible.
For example, in the above embodiment, as the plasma processing apparatus 101, a capacitively coupled parallel plate type plasma processing apparatus that applies high frequency power to the upper electrode 21 and the susceptor 5 as the lower electrode, respectively, is used. Alternatively, a plasma processing apparatus that applies high-frequency power only to the lower electrode may be used. In addition, the plasma processing apparatus is not limited to a parallel plate type apparatus, for example, a plasma processing apparatus using an inductive coupling method, a planar antenna having a plurality of slots, particularly RLSA (Radial Line).
Utilizing a RLSA microwave plasma processing apparatus that can generate microwave plasma with high density and low electron temperature by introducing microwaves into the processing chamber using a slot antenna (radial line slot antenna). You can also.
Moreover, in the said embodiment, although it was set as the structure which performs the plasma processing for an etching and resist peeling with the same plasma processing apparatus 101, it can also be performed with a separate apparatus.

The flowchart which shows the process example which applied this invention to the single damascene process. The flowchart which shows the process example which applied this invention to the dual damascene process. The figure which shows the structural example of the processing system used for implementation of this invention. BRIEF DESCRIPTION OF THE DRAWINGS Drawing which shows the outline | summary of the plasma processing apparatus used for implementation of this invention. BRIEF DESCRIPTION OF THE DRAWINGS Drawing which shows the structure of a wafer cross section typically in order to demonstrate the process of 1st Embodiment of this invention. The figure which shows typically the structure of a wafer cross section in order to demonstrate the process of 2nd Embodiment of this invention. The figure which shows typically the structure of a wafer cross section in order to demonstrate the process of 3rd Embodiment of this invention.

Explanation of symbols

2; chamber 101; plasma processing apparatus 111; process controller 112; user interface 113; storage unit 201: Si substrate 202: interlayer insulating film 203: wiring layer 204: barrier metal 205: lower layer wiring 206: insulating film for preventing Cu diffusion 207 : Interlayer insulating film 208: Resist pattern 209: Barrier metal 210: Cu film 211: Resist pattern 220, 221, 222: Recess

Claims (24)

At least a connected portion connected to another part on the substrate, a layer to be etched formed thereon, and a patterned mask layer formed on the layer to be etched; A concave portion corresponding to the pattern of the mask layer is formed in the layer by etching, and the substrate to be processed having a structure in which the connected portion is exposed in the concave portion,
Substrate processing characterized by performing plasma treatment using plasma of a gas containing at least one of hydrogen, nitrogen, and oxygen to remove the mask layer and remove impurities mixed in the connected portion Method.   The substrate processing method according to claim 1, wherein the connected portion is a metal wiring embedded in a wiring layer below the layer to be etched.   The substrate processing method according to claim 1, wherein the connected portion is a source / drain region or a gate electrode of a transistor.   The substrate processing method according to claim 1, wherein the plasma processing is performed while applying a bias voltage to a support on which a substrate to be processed is placed. Forming a lower layer metal wiring on the substrate;
Forming an interlayer insulating film on the lower metal wiring;
Forming a resist having an opening pattern on the interlayer insulating film;
Etching using the resist as a mask, forming a recess in the interlayer insulating film, exposing the lower layer metal wiring,
Removing the resist;
Cleaning the surface of the substrate after removing the resist;
A method for manufacturing a semiconductor device, comprising:   In the step of removing the resist, plasma of a gas containing at least one of hydrogen, nitrogen, and oxygen is used, and plasma treatment is performed to remove the resist and remove impurities mixed in the lower metal wiring. The method for manufacturing a semiconductor device according to claim 5, wherein:   The semiconductor device according to claim 5, further comprising a step of recovering crystal defects of the lower layer metal wiring exposed in the recess after the step of cleaning the surface of the substrate. Production method.   8. The heat treatment is performed at a temperature of 100 ° C. to 450 ° C. in an atmosphere of a gas containing at least one of hydrogen and nitrogen in the step of recovering crystal defects in the lower layer metal wiring. Semiconductor device manufacturing method.   9. The method of manufacturing a semiconductor device according to claim 8, further comprising a step of cleaning the surface of the lower metal wiring exposed in the recess after the step of recovering crystal defects of the lower metal wiring. .   10. The method of manufacturing a semiconductor device according to claim 9, wherein, in the step of cleaning the surface of the lower metal wiring, a reduction process is performed on the oxide film formed on the exposed surface of the lower metal wiring.   After the step of cleaning the lower surface metal wiring surface, the method further includes a step of forming a multilayer metal wiring by depositing a barrier metal layer and a conductor layer in the recess formed in the interlayer insulating film. A method for manufacturing a semiconductor device according to claim 10. Forming a lower layer metal wiring on the substrate;
Forming an interlayer insulating film on the lower metal wiring;
Forming a first resist having an opening pattern on the interlayer insulating film;
Etching using the first resist as a mask, forming a first recess in the interlayer insulating film, and exposing the lower layer metal wiring;
Removing the first resist;
Forming a second resist having an opening pattern on the interlayer insulating film;
Etching using the second resist as a mask to form a second recess in the interlayer insulating film;
Removing the second resist;
Cleaning the surface of the substrate after removing the resist;
A method for manufacturing a semiconductor device, comprising:   In the step of removing the first resist and / or the second resist, plasma of a gas containing at least one of hydrogen, nitrogen, and oxygen is used to remove the resist and mix with the lower metal wiring. The method for manufacturing a semiconductor device according to claim 12, wherein plasma treatment for removing impurities is performed.   14. The method according to claim 12, further comprising a step of recovering crystal defects of the lower layer metal wiring exposed in the second recess after the step of cleaning the surface of the substrate. A method for manufacturing a semiconductor device.   The step of recovering crystal defects of the lower layer metal wiring is characterized in that heat treatment is performed at a temperature of 100 ° C. to 450 ° C. in a gas atmosphere containing at least one of hydrogen and nitrogen. Semiconductor device manufacturing method.   16. The semiconductor device according to claim 15, further comprising a step of cleaning the surface of the lower metal wiring exposed in the second recess after the step of recovering crystal defects in the lower metal wiring. Manufacturing method.   17. The method of manufacturing a semiconductor device according to claim 16, wherein, in the step of cleaning the surface of the lower metal wiring, the oxide film formed on the exposed surface of the lower metal wiring is reduced.   After the step of cleaning the lower surface metal wiring surface, a multilayer metal wiring is further formed by depositing a barrier metal layer and a conductor layer in the first recess and the second recess formed in the interlayer insulating film. The method of manufacturing a semiconductor device according to claim 17, comprising a forming step. A plasma source for generating plasma;
A processing container that divides a processing chamber for performing plasma processing on an object to be processed by the plasma;
A support for placing the object to be processed in the processing container;
An exhaust means for decompressing the inside of the processing vessel;
Gas supply means for supplying gas into the processing vessel;
A controller that controls the substrate processing method according to any one of claims 1 to 4 to be performed;
A plasma processing apparatus comprising:   A control program which operates on a computer and controls the plasma processing apparatus so that the substrate processing method according to any one of claims 1 to 4 is performed at the time of execution. A computer storage medium storing a control program that runs on a computer,
5. The computer storage medium according to claim 1, wherein the control program controls a plasma processing apparatus used in the substrate processing method according to claim 1 at the time of execution.   Plasma processing apparatus for performing plasma processing on substrate, film forming apparatus for performing film forming process, resist coating / developing apparatus for performing resist coating process and developing process, exposure apparatus for performing exposure process, and heat treatment for performing heat treatment The semiconductor device manufacturing method according to any one of claims 5 to 18 is performed using the apparatus, the cleaning apparatus that performs the cleaning process, the polishing apparatus that performs the polishing process, and these apparatuses. And a control unit for controlling the semiconductor device.   A control which operates on a computer and controls a plurality of semiconductor manufacturing apparatuses so that the semiconductor device manufacturing method according to any one of claims 5 to 18 is performed at the time of execution. program. A computer storage medium storing a control program that runs on a computer,
A computer storage medium characterized in that, when executed, the control program controls a plurality of semiconductor manufacturing apparatuses used in the method for manufacturing a semiconductor device according to any one of claims 5 to 18.

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