KR20210031414A - Substrate processing method - Google Patents

Abstract

According to an embodiment of the present invention, provided is a substrate processing method, which comprises the steps of: providing a substrate on which doped polycrystalline silicon is formed; and removing the doped polycrystalline silicon by a gas phase etching method using an etching gas containing an interhalogen compound gas consisting of chlorine (Cl) and fluorine (F). According to an embodiment of the present invention, the substrate processing method uses an etching gas containing ClF3 gas, so that polycrystalline silicon doped with a fast etch rate can be selectively removed from the underlying structure without causing damage due to plasma.

Description

Substrate processing method {SUBSTRATE PROCESSING METHOD}

The present invention relates to a substrate processing method, and more particularly, to a substrate processing method including a method of selectively removing a film made of impurity-doped silicon.

Further, the present invention relates to a substrate processing method including a method of removing fluorine from a surface of a lower structure after removing a film made of impurity-doped silicon.

The process of manufacturing a semiconductor device includes etching processes for etching various materials.For example, an amorphous carbon layer (ACL) is mainly used as a hard mask in the process of etching a silicon oxide layer, a silicon nitride layer, etc. Became.

On the other hand, as the degree of integration of semiconductor devices increases, an etching process in which holes having a high aspect ratio of tens: 1 or more must be etched in DRAM, 3D NAND flash memory, etc., so-called HARC (High Aspect Ratio Contact) etching process is required.

The thickness of the amorphous carbon film (ACL) used as a hard mask to etch the high aspect ratio holes is inevitably thicker. When the thickness of the amorphous carbon film (ACL) increases, the warpage of the wafer becomes severe, and when the warpage of the wafer becomes severe, it is difficult to form an accurate pattern during a subsequent photolithography process.

In order to solve this problem, development of a new hard mask material having a higher etch selectivity than an amorphous carbon layer for a lower layer (eg, a silicon oxide layer, a silicon nitride layer, etc.) is required. Recently, development of an amorphous carbon film doped with boron (B) is in progress.

In addition, after the dry etching process is completed, a method of selectively removing a new hard mask material having an etching selectivity higher than that of the amorphous carbon layer without affecting the lower layer is also being developed.

An object of the present invention is to provide a substrate processing method capable of selectively removing a hard mask made of polycrystalline silicon doped with impurities.

Another object of the present invention is to provide a substrate treatment method capable of removing fluorine from a surface of a lower structure after removing a hard mask.

In order to solve the above problem, a substrate processing method according to an embodiment of the present invention includes: preparing a substrate on which a polycrystalline silicon layer doped with impurities is formed; And removing the polycrystalline silicon layer by a gas phase etching method using an etching gas including an interhalogen compound gas composed of chlorine (Cl) and fluorine (F). .

The polycrystalline silicon layer may be a boron (B) doped polycrystalline silicon layer.

The polycrystalline silicon layer may be a patterned hard mask layer.

In addition, the interhalogen compound gas _{may be chlorine trifluoride (ClF 3} ) gas.

In addition, the step of etching the polycrystalline silicon layer may be performed at a temperature of 10°C to 100°C.

In addition, a lower structure is included under the polycrystalline silicon layer, and in the step of etching the polycrystalline silicon layer, an etching selectivity of the polycrystalline silicon and the lower structure may be 8:1 or more.

The lower structure may include at least one of silicon oxide, silicon nitride, silicon carbonitride (SiCN), and titanium nitride.

After removing the polycrystalline silicon layer, the step of removing fluorine (F) remaining on the surface of the lower structure using heat treatment or plasma may be further included.

The step of removing the fluorine may include one or more of the following steps.

1) heating the lower structure to a temperature of 150 ℃ ~ 400 ℃,

2) repeatedly performing the process of heating and cooling the lower structure to a temperature of 150°C to 250°C,

3) Exposing the lower structure to a plasma containing _{O 2} , H ₂ , N ₂ or Ar at a temperature of 100°C to 400°C.

In order to solve the above problems, a substrate processing method according to another embodiment of the present invention includes forming a lower structure including silicon oxide or silicon carbonitride and a polycrystalline silicon layer doped with impurities on a substrate; Etching the lower structure using the polycrystalline silicon layer as a hard mask; Removing the polycrystalline silicon layer by a gas phase etching method using an etching gas including an interhalogen compound gas consisting of chlorine (Cl) and fluorine (F); And removing fluorine (F) remaining on the surface of the lower structure by using a plasma containing _{O 2.}

According to the substrate processing method according to the present invention, _{by using an etching gas containing an interhalogen compound such as ClF 3} gas, a hard mask made of impurity-doped polycrystalline silicon is formed without causing damage to the underlying structure by plasma. It can be selectively removed from the underlying structure. In particular, a hard mask made of polycrystalline silicon doped with impurities by a vapor phase etching method may be selectively removed from the underlying structure.

According to the substrate processing method according to the present invention, a hard mask made of polycrystalline silicon doped with impurities can be removed at a low temperature and at a high etching rate by a vapor phase etching method using an etching gas containing _{ClF 3 gas.} The time required for the process of removing is shortened, and the throughput of the processing apparatus for removing the hard mask layer may be improved.

According to the substrate processing method according to the present invention, by removing the fluorine (F) remaining on the surface of the lower structure when the hard mask is removed, the reliability of the finally manufactured semiconductor device can be secured. In addition, when the lower structure includes a silicon oxide film or a silicon carbonitride film, fluorine from the surface of the lower structure can be effectively removed by using _{O 2 plasma.}

1 is a flow chart showing a substrate processing method according to an embodiment of the present invention.
2A to 2C are diagrams illustrating a substrate processing method according to an exemplary embodiment of the present invention.
3 is a graph showing etching amounts of various materials by an etching gas including _{ClF 3 gas according to temperature.}
FIG. 4 is a graph showing etching amounts of doped polycrystalline silicon and undoped polycrystalline silicon by an etching gas including _{ClF 3 gas according to temperature.}
5A is a diagram showing data obtained by analyzing the amount of fluorine (F) on the surface of a lower silicon oxide film by a secondary ion mass spectrometer (SIMS) under various process conditions.
5B is a diagram showing data obtained by analyzing the amount of fluorine (F) on the surface of a lower silicon carbonitride film by a secondary ion mass spectrometer (SIMS) under various process conditions.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used to indicate the same or similar elements.

As described above, in manufacturing a semiconductor device, a new hard mask having a higher etch selectivity than an amorphous carbon film is required, and a method of selectively removing the hard mask from the lower film after the dry etching process is completed. Need for development.

The present invention is a material that can replace an amorphous carbon layer, and performs a dry etching process using an impurity-doped polycrystalline silicon layer as a hard mask, and after the dry etching process is completed, the impurity-doped polycrystalline silicon layer is selectively removed from the lower layer. Includes how to do it.

1 is a flow chart showing a substrate processing method according to an embodiment of the present invention. 2A to 2C are diagrams illustrating a substrate processing method according to an exemplary embodiment of the present invention. Hereinafter, a substrate processing method according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2A to 2C.

In the embodiment of the present invention, a case where impurity-doped polycrystalline silicon is used as the hard mask layer is exemplified, but is not limited to being used as the hard mask layer as described below.

A method of processing a substrate according to an exemplary embodiment of the present invention includes the steps of preparing a substrate on which polycrystalline silicon doped with impurity is formed (S100); And removing impurity-doped polycrystalline silicon by a gas phase etching method using an etching gas including an interhalogen compound gas composed of chlorine (Cl) and fluorine (F) (S300). Includes.

Referring to FIGS. 1 and 2A, the step of preparing a substrate on which polycrystalline silicon doped with impurity is formed (S100) includes: providing a lower structure 120 on the substrate 110; Providing a hard mask layer 130 on the lower structure 120; And patterning the hard mask layer 130.

The substrate 110 includes a semiconductor material, and may be, for example, a silicon wafer.

The lower structure 120 may be formed on the substrate 110 by using a chemical vapor deposition (CVD) process. The lower structure 120 may include at least one of silicon oxide, silicon nitride, silicon carbonitride (SiCN), and titanium nitride (TiN). Preferably, the lower structure 120 includes at least one of silicon oxide and silicon carbonitride. For example, the lower structure 120 may be formed by alternately stacking a silicon oxide layer and a silicon carbonitride layer alternately stacked on the substrate 110. The silicon oxide film and the silicon carbonitride film may be stacked on the substrate 110 in tens to hundreds of layers, respectively.

The hard mask layer 130 may be formed by depositing impurity-doped polycrystalline silicon on the lower structure 120 using a chemical vapor deposition (CVD) process. For example, the doped polycrystalline silicon layer may be formed of polycrystalline silicon doped with impurities such as boron (B), indium (In), gallium (Ga), and phosphorus (P). For example, the impurity-doped polycrystalline silicon may be polycrystalline silicon doped with phosphorus (P) or polycrystalline silicon doped with boron (B) and phosphorus (P). The impurity is preferably boron (B). As the silicon source gas used in the chemical vapor deposition (CVD) process, various sources such as _{SiH 4} , Si ₂ H ₆ , and Si ₃ H _{8 may be used.} As the boron source gas, a gas such as _{B 2} H _{6 may be used.}

Meanwhile, the use of the doped polycrystalline silicon of the present invention is not necessarily limited to the hard mask layer 130. The doped polycrystalline silicon of the present invention is a unit film constituting the lower structure 120 including at least one of silicon oxide, silicon nitride, silicon carbonitride (SiCN), and titanium nitride (TiN) as a non-limiting example. It can be located in the longitudinal or transverse direction between them. Further, the doped polycrystalline silicon positioned between the unit layers of the present invention may be selectively removed through a subsequent etching process, if necessary.

The hard mask layer 130 may be patterned using a photolithography process and an etching process. For a photolithography process, a photoresist film may be formed on the hard mask layer 130. The photoresist layer may be removed after patterning of the hard mask layer 130 is completed. In addition, depending on the process, an antireflection film may be additionally formed between the hard mask layer and the photoresist film.

1 and 2C, the step of removing the hard mask layer 130 made of doped polycrystalline silicon (S300) is an interhalogen compound gas containing chlorine (Cl) and fluorine (F) in the processing chamber. It may be performed by supplying an etching gas including, and reacting the interhalogen compound gas with the material of the hard mask layer 130 and doped polycrystalline silicon in a gas phase. The processing chamber may be the same processing chamber as the processing chamber in which the dry etching process of the lower structure 120 is performed, or may be a separate processing chamber.

The interhalogen compound gas may include at least one of chlorine monofluoride (ClF), chlorine trifluoride (ClF ₃ ), and chlorine pentafluoride (ClF _{5) gas.} For example, the interhalogen compound gas _{may be chlorine trifluoride (ClF 3} ) gas. The etching gas may further include a carrier gas such as _{nitrogen (N 2) and argon (Ar).}

The step of removing the hard mask 130 (S300) may be performed at a temperature of 10°C to 100°C. At a temperature of less than 10° C., there is a problem that the hard mask 130 is not etched by the interhalogen compound gas, for example, chlorine trifluoride (ClF _{3) gas.} In addition, it is expected that the etching amount of the hard mask 130 increases and the etching amount of the lower structure 120 exceeds the target value at a temperature exceeding 100°C.

In the step of removing the hard mask 130, an etching selectivity ratio of the hard mask 130 and the lower structure 120 may be 8:1 or more. Specifically, an etching selectivity ratio of the hard mask 130 and the lower structure 120 may be 8:1 or more.

In the present invention, by using an interhalogen compound gas consisting of chlorine (Cl) and fluorine (F), for example, _{an etching gas including ClF 3} gas, polycrystalline silicon doped by a gas phase etching method (for example, The hard mask made of boron (B) doped polycrystalline silicon) may be selectively removed from the underlying structure.

In addition, in the present invention, by removing the hard mask layer 130 by a gas phase etching method using _{ClF 3 gas without forming plasma in the processing chamber, damage caused by plasma, that is, activated by plasma.} Physical and electrical damage to the lower structure 120 due to the generated ions can be minimized. In addition, since the hard mask can be removed at a high etch rate at a low temperature (for example, 100° C. or less) without using plasma, the throughput of the processing apparatus for removing the hard mask layer 130 is improved, The maintenance of the processing unit is easier.

In the substrate processing method according to an embodiment of the present invention, before the step of removing the hard mask layer 130 (S300), the lower structure 120 is formed by using the patterned hard mask layer 130 as an etching mask. A dry etching step (S200) may be further included.

Referring to FIGS. 1 and 2B, in the step of dry etching the lower structure 120 (S200), for example, a hard mask layer 130 made of doped polycrystalline silicon by supplying an etching gas into a processing chamber. It may be a step of dry etching the silicon oxide layer and the silicon nitride layer alternately stacked on the substrate 110 by using as an etching mask. In this step, holes having a high aspect ratio of tens: 1 or more may be formed in the lower structure 120.

The substrate processing method according to the exemplary embodiment of the present invention may further include removing fluorine (F) remaining on the surface of the lower structure 120 (S400).

When the hard mask layer 130 is removed using an interhalogen compound gas composed of chlorine (Cl) and fluorine (F), for example, ClF ₃ gas, fluorine (F) is formed on the surface of the lower structure 120. Can survive. However, the remaining fluorine (F) may be _{combined with hydrogen (H 2} ) during a subsequent process to form hydrogen fluoride (HF). The hydrogen fluoride (HF) generated in this way may cause an unexpected process failure by etching the surrounding silicon oxide film, or may deteriorate the reliability of a finally manufactured semiconductor device. In addition, there is a possibility that the remaining fluorine combines or reacts with C, O, and the like to generate fume. Therefore _{, after removing the hard mask layer using ClF 3} gas, it is necessary to remove fluorine (F) remaining on the surface of the lower structure to a certain level or less.

The step of removing the fluorine may be performed by heating the lower structure 120 to a temperature of 150°C to 400°C. By heating the lower structure for several minutes to several tens of minutes by increasing the temperature of the substrate disposed in the processing chamber to 150°C to 400°C, fluorine (F) remaining on the surface of the lower structure 120 after the hard mask layer is removed is removed. Can be removed. The processing chamber may be the same processing chamber as the processing chamber in which the process of removing the hard mask layer 130 is performed, or may be a separate processing chamber.

The step of removing fluorine may be a process of repeatedly heating and cooling the lower structure 120 to a temperature of 150° C. to 250° C. using a lamp in the processing chamber (lamp cycle). The step of removing fluorine is repeated several times by repeatedly performing a cycle of rapidly heating and cooling to a temperature of about 200 degrees by a lamp (for example, a halogen lamp), thereby removing the hard mask layer and then removing the lower structure 120. Fluorine (F) remaining on the surface can be removed. The processing chamber may be the same processing chamber as the processing chamber in which the process of removing the hard mask layer 130 is performed, or may be a separate processing chamber.

In the processing chamber in which the process of removing the hard mask layer 130 is performed both when a lamp is used or when the substrate above is heated, there is a high possibility that the fluorine component of the etching gas remains in the processing chamber. Therefore, it is more preferable to use a separate processing chamber as the chamber in the step of removing fluorine due to contamination of the processing chamber due to the remaining fluorine component. In addition, since the step of removing fluorine is performed at a temperature higher than room temperature, it takes time to increase or decrease the temperature of the substrate. Therefore, if a separate processing chamber is used in the step of removing the fluorine, the etching step can be performed without a waiting time, thereby improving the throughput of the entire process.

In the case of using a lamp, the process time of the step of removing the fluorine may be shortened compared to the case of heating the substrate. Accordingly, when the step of removing the fluorine is performed in a processing chamber different from the processing chamber in which the process of removing the hard mask layer 130 is performed, the number of processing chambers for removing the fluorine can be reduced.

In the present invention, after removing the hard mask 130 by the heat treatment process described above, fluorine (F) remaining on the surface of the lower structure 120 can be removed, thereby preventing process defects and finally manufacturing the semiconductor device. The reliability of can be secured.

Alternatively, fluorine (F) remaining on the surface of the lower structure 120 may be removed through a substrate treatment using a plasma containing _{O 2} , H ₂ , N _{2 or Ar.} In order to increase the fluorine removal efficiency, the lower structure 120 is heated to a temperature of 100°C to 400°C, and a process of removing fluorine is performed through plasma treatment containing at least one of _{O 2} , H ₂ , N _{2, and Ar.} Can be.

3 is a graph showing etching amounts of various materials by an etching gas including _{ClF 3 gas according to temperature.}

3 and Table 1 below, polycrystalline silicon (B_poly) doped with boron (B) was not etched at -10°C, and was etched at a temperature of 10°C or higher. In addition, as the temperature increased from 10°C to 50°C, the amount of etch of polycrystalline silicon doped with boron (B) increased rapidly.

Silicon nitride (SiN) is etched even at a temperature of -10°C, and as the temperature increases, the etching amount of silicon nitride gradually increases. Silicon carbonitride (SiCN) was not etched when the temperature was less than 30°C, but began to be etched at 50°C. Silicon oxide (SiOx) was not etched regardless of temperature. Titanium nitride (TiN) had a lower etch amount than silicon nitride (SiN), but showed a similar tendency to that of silicon nitride (SiN).

[Table 1]

The etching amount of the polycrystalline silicon doped with boron (B) per unit time may increase as the process pressure in the processing chamber increases, _{the flow rate of ClF 3} gas increases, and the flow rate of nitrogen gas, which is a carrier gas, decreases.

In addition, as the etching conditions of the polycrystalline silicon doped with boron (B) per unit time are higher, the etching amount of silicon nitride (SiN) decreases, and the polycrystalline silicon doped with boron (B) is The etch selectivity may increase.

FIG. 4 is a graph showing etching amounts of doped polycrystalline silicon and undoped polycrystalline silicon by an etching gas including _{ClF 3 gas according to temperature.}

Referring to FIG. 4, as described above with reference to FIG. 3, polycrystalline silicon (B_poly) doped with boron (B) is not etched at -10°C, and as the temperature increases from 10°C to 50°C, boron The amount of etching of polycrystalline silicon (U_poly) doped with (B) increased rapidly.

However, despite being etched under the same etching conditions, in the case of undoped polycrystalline silicon (U_poly), unlike polycrystalline silicon (B_poly) doped with boron (B), the largest etching amount at -10°C. It was observed, and the etch amount of undoped polycrystalline silicon (U_poly) gradually decreased as the temperature increased to 50°C.

At 30° C., the etch amount of undoped polycrystalline silicon (U_poly) and that of boron (B) doped polycrystalline silicon (B_poly) were almost the same. At temperatures below 30°C, the etch amount of undoped polycrystalline silicon (U_poly) is greater than that of polycrystalline silicon (B_poly) doped with boron (B), and at temperatures above 30°C, boron (B) The etch amount of undoped polycrystalline silicon (B_poly) was greater than that of undoped polycrystalline silicon (U_poly).

In other words, at a temperature of less than 30°C, the etch selectivity of undoped polycrystalline silicon (U_poly) to silicon nitride is greater than that of polycrystalline silicon (B_poly) doped with boron (B), and 30 It can be seen that the etch selectivity of polycrystalline silicon (B_poly) doped with boron (B) to silicon nitride is greater than that of undoped polycrystalline silicon (U_poly) at a temperature exceeding °C.

The phenomenon in which the tendency of the etch selectivity according to the temperature of undoped polycrystalline silicon (U_poly) and boron (B) doped polycrystalline silicon (B_poly) varies with each other is very peculiar and at the same time the substrate processing method of the present invention It presents the possibility to increase the usability of the product.

As a non-limiting example, if one layer is undoped polycrystalline silicon (U_poly) and the other layer is doped polycrystalline silicon (B_poly), a multi-layered hard mask is simply controlled by temperature as needed. By doing so, it becomes possible to be selectively etched. In addition, as another non-limiting example, a single-layer hard mask including undoped polycrystalline silicon (U_poly) and doped polycrystalline silicon (B_poly) depending on the location is a spatial section (for example, , Left/center/right) can be selectively etched.

Meanwhile, FIG. 5 is an exemplary diagram, and the etch amount graph of undoped polycrystalline silicon (U_poly) and the etch amount graph of boron (B) doped polycrystalline silicon (B_poly) cross each other according to the etching conditions. The temperature can be varied.

5A is a diagram showing data obtained by analyzing the amount of fluorine (F) on the surface of a lower silicon oxide film by a secondary ion mass spectrometer (SIMS) under various process conditions.

5B is a diagram showing data obtained by analyzing the amount of fluorine (F) on the surface of a lower silicon carbonitride film by a secondary ion mass spectrometer (SIMS) under various process conditions.

5A and 5B, the reference (Ref.) state is the surface of the silicon oxide film (Fig. 5A) and the surface of the silicon carbonitride film (Fig. 5B) before the hard mask layer made of polycrystalline silicon doped with boron (B) is formed. ) Is a SIMS analysis of the amount of fluorine (F) present. 5A and 5B show the intensity of fluorine (F) in the reference state (Ref.) as 1, and the intensity of fluorine in the other state as a relative intensity to the intensity of fluorine in the reference state.

Referring to FIG. 5A, immediately after the hard mask layer is removed, the intensity of fluorine (F) present on the surface of the silicon oxide film increased to about 3.2 (see “HM removal” in FIG. 5A). When the silicon oxide layer was heat-treated at 200° C. for 4 minutes after removing the hard mask layer, the strength of fluorine (F) present on the surface of the silicon oxide layer was reduced to about 1.8 (refer to “200° C.” in FIG. 5A). On the other hand, when the silicon oxide layer was heat-treated at 350° C. for 4 minutes after removing the hard mask, the strength of fluorine (F) present on the surface of the silicon oxide layer was reduced to about 1.6 (see “350° C.” in FIG. 5A). In addition, when the cycle of rapidly heating and cooling the silicon oxide film to a temperature of about 200°C by a lamp (for example, a halogen lamp) after removing the hard mask layer is repeatedly performed 10 times, it is present on the surface of the silicon oxide film. The intensity of fluorine (F) was reduced to about 1.3 (see'lamp cycle' in FIG. 5A).

Referring to FIG. 5B, immediately after removing the hard mask layer, the intensity of fluorine (F) present on the surface of the silicon carbonitride film increased to about 1.9 (see “HM removal” in FIG. 5A). Meanwhile, when the silicon carbonitride film is heat-treated at 300°C for 4 minutes after removing the hard mask layer (refer to '300°C' in FIG. 5B), the silicon carbonitride film is lamp (eg, halogenated) after removing the hard mask layer. When the cycle of rapidly heating and cooling to a temperature of about 200°C by a lamp) is repeatedly performed 10 times (refer to “lamp 10 cycles” in FIG. 5B), the silicon carbonitride film is removed at 300° C. In the case of exposure to plasma (Ar Plasma in Fig. 5B), the silicon carbonitride film _{is exposed to H 2} plasma at 300°C after removing the hard mask layer (H2 Plasma in Fig. 5B), the intensity of fluorine is not significantly reduced. Did. However, when the silicon carbonitride film is _{exposed to O 2} plasma at 300°C for 10 and 20 minutes after removing the hard mask layer (O2 Plasma 1X and 2X in FIG. 5B), the strength of fluorine present on the surface of the silicon carbonitride film is It can be seen that there is a significant decrease of 0.7 and 0.6 That is, when the lower structure under the impurity-doped polycrystalline silicon mask is silicon carbonitride, it can be seen that the method of removing fluorine by oxygen plasma after removing the polycrystalline silicon mask is the most effective.

The mechanism of fluorine removal by _{O 2 plasma is as follows.}

After removal of the polycrystalline silicon hardmask by ClF ₃ , the SiCN surface is in a state in which F such as Si-F is bonded to Si. In order to remove F, substrate heating or plasma exposure may be considered. As a result of the experiment, the F intensity did not decrease significantly in the case of substrate heating and other plasmas, but the F intensity decreased significantly in the case of _{O 2 plasma.} In _{the case of O 2} plasma, F can be removed by converting Si-F bonds into Si-O bonds due to the high reactivity of oxygen radicals. This is believed to be due to the highest electronegativity of O after F.

Even when the lower structure is a silicon oxide film, it is judged that a high fluorine removal effect can be obtained by the above mechanism.

Therefore, when the substructure exposed after removing the boron-doped polycrystalline silicon hardmask _{is made of SiO 2} , residual F can be removed through a ramp cycle process, and when the substructure is made of SiCN, O ₂ plasma is preferable. Do. In addition, if both SiO2 and SiCN are included in the exposed substructure, O ₂ plasma can be effective as described above.

In the above, the embodiments of the present invention have been mainly described, but various changes or modifications may be made at the level of the person skilled in the art. Accordingly, it will be understood that such changes and modifications are included within the scope of the present invention as long as they do not depart from the scope of the present invention.

110: substrate 120: lower structure
130: hard mask layer

Claims (11)

Preparing a substrate on which a polycrystalline silicon layer doped with impurities is formed; And
Including, removing the polycrystalline silicon layer by a gas phase etching method using an etching gas including an interhalogen compound gas composed of chlorine (Cl) and fluorine (F). Substrate processing method.
The method of claim 1,
The polycrystalline silicon layer is a boron (B) doped polycrystalline silicon layer.
The method of claim 1,
The polycrystalline silicon layer is a patterned hard mask layer.
The method of claim 1,
The interhalogen compound gas is chlorine trifluoride (ClF ₃ ) gas.
The method of claim 1,
The step of etching the polycrystalline silicon layer is performed at a temperature of 10 ℃ to 100 ℃, the substrate processing method.
The method of claim 1,
A substrate processing method comprising a lower structure under the polycrystalline silicon layer, wherein in the step of etching the polycrystalline silicon layer, an etching selectivity ratio between the polycrystalline silicon and the lower structure is 8:1 or higher.
The method of claim 6,
The lower structure includes at least one of silicon oxide, silicon nitride, silicon carbonitride (SiCN), and titanium nitride.
The method of claim 6,
After removing the polycrystalline silicon layer, the method further comprising removing fluorine (F) remaining on the surface of the lower structure using heat treatment or plasma.
The method of claim 8,
The step of removing the fluorine includes one or more of the following steps.
1) heating the lower structure to a temperature of 150 ℃ ~ 400 ℃,
2) repeatedly performing the process of heating and cooling the lower structure to a temperature of 150°C to 250°C,
3) Exposing the lower structure to a plasma containing _{O 2} , H ₂ , N ₂ or Ar at a temperature of 100°C to 400°C.
Forming a lower structure including silicon oxide or silicon carbonitride and a polycrystalline silicon layer doped with impurities on a substrate; And
Etching the lower structure using the polycrystalline silicon layer as a hard mask;
Removing the polycrystalline silicon layer by a gas phase etching method using an etching gas including an interhalogen compound gas consisting of chlorine (Cl) and fluorine (F); And
Using a plasma containing O ₂ , removing fluorine (F) remaining on the surface of the lower structure.
The method of claim 10,
The step of removing the fluorine,
The substrate processing method is performed while the lower structure is heated to a temperature of 100°C to 400°C.

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