JP2000200833A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, which is excellent in reliability and is suitable to miniaturization. SOLUTION: An organic SOG film 3 is formed on a silicon oxide film 2 and boron ions are implanted in the film 3. In such a way, the boron ions are introduced in the film 3, whereby organic components in the film 3 are decomposed, water and a hydroxyl group, which are contained in the film 3, are reduced. After metal wirings 6 are buried in a modified SOG film 4 using a damascene method, a modified SOG film 8 is formed on the film 4 and moreover, contact holes are formed in the film 8. After connection hole wirings 10 are buried in the contact holes, a modified SOG film 11 and an upper metal wiring layer 12 are formed using the damascene method.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a technique for forming an insulating film on a device.

[0002]

2. Description of the Related Art In recent years, in order to further increase the degree of integration of semiconductor integrated circuits, it has been required to advance wiring miniaturization and multilayering. In order to multi-layer the wiring, an interlayer insulating film is provided between each wiring. However, if the surface of the interlayer insulating film is not flat, the wiring formed above the interlayer insulating film will have a step and cause a failure such as disconnection. Is caused.

Therefore, the surface of the interlayer insulating film (that is, the surface of the device) must be as flat as possible. As described above, a technique for planarizing the surface of a device is called a planarization technique, and has become more and more important with miniaturization and multilayering of wiring.

[0004] In the planarization technique, there is an SOG film as an interlayer insulating film that is frequently used. In particular, active studies have been made on a planarization technique utilizing the flow characteristics of an interlayer insulating film material.

[0005] SOG is a general term for a solution in which a silicon compound is dissolved in an organic solvent and a film formed from the solution and containing silicon dioxide as a main component.

To form an SOG film, first, a solution in which a silicon compound is dissolved in an organic solvent is dropped on a substrate, and the substrate is rotated. Then, the film of the solution is formed thicker in the concave portion and thinner in the convex portion, so as to relieve the step on the substrate formed by the wiring.
As a result, the surface of the coating of the solution is planarized.

Next, when a heat treatment is performed, the organic solvent evaporates and the polymerization reaction proceeds to form an SOG film having a flat surface.

[0008] As shown in the general formula (1), the SOG film includes an inorganic SO containing no organic component in the silicon compound.
There are a G film and an organic SOG film containing an organic component in a silicon compound as represented by the general formula (2).

[SiO ₂ ] _n ··· (1) [R _X Si _Y O _Z ] _n ··· (2) (n, X, Y, Z: integer, R: alkyl group or aryl group) Inorganic SOG Films and organic SOG films have very good flatness, but inorganic SOG films contain a large amount of moisture and hydroxyl groups, which adversely affect metal wiring and the like, deteriorating electrical characteristics, corrosion, etc. Problem may occur.

Although the organic SOG film contains less moisture and hydroxyl groups than the inorganic SOG film, it has the same problem.

Therefore, usually, when an SOG film is used as an interlayer insulating film, it is formed by, for example, a plasma CVD method which has a property of relatively blocking moisture and hydroxyl groups and a property of high insulation and mechanical strength. An insulating film such as a silicon oxide film is interposed between the SOG film and the metal wiring (see, for example, Japanese Patent Application Laid-Open No. Hei 5-22).
No. 6334 (H01L21 / 3205).

[0012]

When an insulating film such as a silicon oxide film formed by a plasma CVD method is interposed between the SOG film and the metal wiring as in the conventional example, the distance between the patterns of the underlying metal wiring is reduced. Constrained by narrowing,
This hinders miniaturization of the device.

The present invention relates to a method for manufacturing a semiconductor device,
It is an object to solve such a problem.

[0014]

According to a method of manufacturing a semiconductor device of the present invention, a step of burying a first wiring in a first insulating film into which an impurity is introduced, and the step of forming the first insulating film. Forming a second insulating film on the second insulating film, forming a contact hole in the second insulating film that leads to the first wiring, at least in the contact hole;
Forming a second wiring electrically connected to the first wiring.

In the method of manufacturing a semiconductor device according to the present invention, a step of forming a first insulating film on a substrate, a step of introducing an impurity into the first insulating film, Embedding a first wiring in the insulating film; forming a second insulating film on the first insulating film; connecting the first wiring to the second insulating film; The gist thereof includes a step of forming a contact hole, and a step of forming a second wiring electrically connected to the first wiring at least in the contact hole.

In the method of manufacturing a semiconductor device according to the present invention, a step of burying a first wiring in a first insulating film into which an impurity is introduced, and a step of forming a first wiring on the first insulating film. Forming a second insulating film, forming a first mask pattern on the second insulating film, and forming a third insulating film on the second insulating film and the first mask pattern. Forming a second mask pattern on the third insulating film; and forming the third insulating film and the second mask pattern based on the first mask pattern and the second mask pattern. Forming a contact hole in the second insulating film, the contact hole communicating with the first wiring; and forming, in at least the contact hole, a second electrically connected to the first wiring.
And a step of forming the wiring described above.

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of burying a first wiring in the first insulating film into which the impurity is introduced, and a step of forming a first wiring on the first insulating film. Forming a second insulating film, forming a first mask pattern on the second insulating film, and forming a third insulating film on the second insulating film and the first mask pattern. Forming a second mask pattern having an opening larger than the first mask pattern on the third insulating film; and forming the second mask pattern on the basis of the second mask pattern. Forming a trench reaching the first mask pattern in the third insulating film; and forming a contact hole communicating with the first wiring in the second insulating film based on the first mask pattern. Forming,
Forming a third wiring electrically connected to the first wiring at least in the contact hole and the trench.

Further, a method of manufacturing a semiconductor device according to the present invention
Forming a first insulating film on the substrate, introducing an impurity into the first insulating film, embedding a first wiring in the first insulating film; Forming a second insulating film on the second insulating film, forming a first mask pattern on the second insulating film, forming a second mask on the second insulating film and the first mask pattern. Forming a third insulating film thereon; and forming a second insulating film on the third insulating film having an opening larger than the first mask pattern.
Forming a trench that reaches the first mask pattern in the third insulating film based on the second mask pattern; and forming a trench in the third insulating film based on the first mask pattern. Forming a contact hole in the second insulating film that communicates with the first wiring; and forming a third wiring electrically connected to the first wiring in at least the contact hole and the trench. And the step of forming

Preferably, the method further comprises a step of introducing impurities into the second insulating film and the third insulating film.

By introducing impurities into the first insulating film, the second insulating film, and the third insulating film, the respective films are reformed to reduce water and hydroxyl groups contained in the films and to absorb the water. It becomes difficult to do. Thereby, the insulating characteristics of the insulating film can be improved.

In particular, if impurities are introduced into the first insulating film before forming the first wiring, and if impurities are introduced into the second insulating film before forming the second wiring. ,Also,
If an impurity is introduced into the third insulating film before forming the third wiring, the impurity can be implanted to a substantially uniform depth over the entire film, and the entire film can be uniformly reformed. Can be.

In this case, a fourth insulating film is formed beforehand under the first insulating film, and impurities are introduced into the first insulating film by using the first insulating film and the fourth insulating film. By performing the process under the condition of reaching the interface with the first insulating film, the adhesion strength between the first insulating film and the fourth insulating film can be improved.

The first insulating film, the second insulating film, and the third insulating film preferably include a silicon oxide film containing 1% or more of carbon, such as an organic SOG film, or an inorganic SOG film.

Further, it is desirable that the organic component in the first insulating film is decomposed by introducing impurities.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A manufacturing method according to a first embodiment of the present invention will be described with reference to FIGS.

Step 1 (see FIG. 1): A silicon oxide film 2 is formed on a (100) p-type (or n-type) single-crystal silicon substrate 1.
(Thickness: 200 nm), and an organic SOG film 3 is formed thereon. The composition of the organic SOG film 3 is [(CH ₃ ) ₂ S
i ₄ O ₇ ] _n and the film thickness is 600 nm. Note that the silicon oxide film 2 corresponds to the fourth insulating film of the present invention, and the organic SOG film 3 corresponds to the first insulating film of the present invention.

The silicon oxide film 2 is formed by a plasma CVD method. As reaction gas, monosilane and nitrous oxide (SiH ₄ + N ₂ O), monosilane and oxygen (SiH ₄
+ O ₂ ), TEOS (Tetra-ethoxy-silane) and oxygen (T
EOS + O ₂ ) or the like, and the film formation temperature is 300 to 900
° C.

The silicon oxide film 2 has a plasma CV
Methods other than Method D (Normal pressure CVD, Low pressure CVD, ECR
Plasma CVD, photo-excited CVD, TEOS-CVD
Method, a PVD method, etc.). For example,
The gas used in the normal pressure CVD method is monosilane and oxygen (S
iH ₄ + O ₂ ), and the film formation temperature is 400 ° C. or lower.
The gas used in the low pressure CVD method is monosilane and nitrous oxide (SiH ₄ + N ₂ O), and the film formation temperature is 900
It is below ° C.

The method of forming the organic SOG film 3 is as follows. First, an alcohol-based solution of a silicon compound having the above composition (for example,
(PA + acetone) is dropped on the substrate 1 and the substrate is rotated at a rotation speed of 2300 rpm for 20 seconds to form a film of this solution on the substrate 1. At this time, the film of the alcohol-based solution is formed so as to be thicker in the concave portion and thinner in the convex portion than the step on the substrate 1 so as to reduce the step. As a result, the surface of the film of the alcohol-based solution is flattened.

Next, in a nitrogen atmosphere, 100 ° C. for 1 minute, 200 ° C. for 1 minute, 300 ° C. for 1 minute, 22 ° C.
For 1 minute at 430 ° C. for 30 minutes.
The polymerization reaction proceeds as the alcohol solvent evaporates, and an organic SOG film having a flat surface and a thickness of 300 nm is formed. By repeating this film formation-heat treatment operation once more, an organic SOG film 3 having a thickness of 600 nm is obtained.

The organic SOG film 3 is formed with a substantially uniform thickness over the entire surface of the substrate because the underlying surface is flat. The organic SOG film 3 is a silicon oxide film containing 1% or more of carbon.

Step 2 (see FIG. 2): An organic SOG film is formed by ion implantation using boron (boron) ions (B ⁺ ) at an acceleration energy of 140 KeV and a dose of 2 × 10 ¹⁵ atoms / cm ^2. Dope 3 When implanted under these conditions, boron ions reach the interface between the organic SOG film 3 and the silicon oxide film 2.

As described above, by introducing boron ions into the organic SOG film 3, the organic components in the film are decomposed and the moisture and hydroxyl groups contained in the film are reduced.

Further, by introducing boron ions to the interface with the silicon oxide film 2, the adhesion strength between them is increased.

As a result, the organic SOG film 3 contains no organic components, contains only a small amount of water and hydroxyl groups, and has a high adhesion strength to the underlying film (silicon oxide film 2) (hereinafter referred to as a modified SOG film). 4). As described above, since the organic SOG film 3 has a substantially uniform thickness over the entire surface of the substrate, the entire organic SOG film 3 is substantially uniformly reformed, and the adhesion strength to the underlying film is increased over substantially the entire surface. Note that this modified SOG film 4 also contains 1 carbon.
% Silicon oxide film.

Step 3 (see FIG. 3): Using a resist pattern (not shown) as a mask, anisotropic etching using a fluorocarbon-based gas as an etching gas is performed.
A trench 5 is formed in the modified SOG film 4.

Step 4 (see FIG. 4): After cleaning the inside of the trench 5 by sputter etching using an inert gas (eg, Ar), the inside of the trench 5 and the modified SO
A TiN film as an adhesion layer and a barrier layer is formed on the G film 4 by using a magnetron sputtering method or a CVD method,
Further, a CVD method or a plating method
After forming a film, CMP (Chemical Mechanical Po
The surface of the Cu film is polished using the lithography) method, and finally the metal wiring 6 made of TiN and Cu is formed only in the trench 5.
Is buried. This metal wiring embedding technology is
Generally, it is called a damascene method.

Since the organic SOG has a very good step coverage, for example, even if the organic SOG film 3 is applied after forming the metal wiring 6 in steps 1 to 4, Organic SOG can be sufficiently filled.
However, when the organic SOG film is applied to a place where there is unevenness like a wiring pattern on the base as described above, the thickness of the organic SOG film 3 may differ, for example, in a place where there is a wiring and in a place where there is no wiring. In this state, organic SOG
When ion implantation is performed to modify the film, a modified portion and a portion that is not modified are generated in a lower layer portion in the organic SOG film, and various problems described below occur.

On the other hand, according to the present embodiment, since the organic SOG film 3 is formed on the flat base surface before the metal wiring 6 is formed, the thickness of the organic SOG film 3 becomes substantially uniform, The entire film 3 is almost uniformly reformed.

Step 5 (see FIG. 5): On the modified SOG film 4 and the metal wiring 6, an organic SOG film 7 having a thickness of 600 nm is formed. The composition and forming method of the organic SOG film 7 are the same as those of the organic SOG film 3. The organic SOG film 7
Corresponds to the second insulating film of the present invention.

Step 6 (refer to FIG. 6): The organic SOG film 7 is doped with boron ions by ion implantation under the conditions of an acceleration energy of 140 KeV and a dose of 2 × 10 ¹⁵ atoms / cm ^2. Like the quality SOG film 4, the organic SOG film 7 is modified (hereinafter, referred to as a modified SOG film 8). When implanted under these conditions, boron ions reach the interface between the organic SOG film 7 and the modified SOG film 4.

Also at this time, since the organic SOG film 7 has a substantially uniform thickness over the entire surface of the substrate, the organic SOG film 7
The entire film 7 is reformed almost uniformly.

Step 7 (see FIG. 7): Using a resist pattern (not shown) as a mask, anisotropic etching using a fluorocarbon-based gas as an etching gas is performed.
Contact holes 9a and 9b communicating with the metal wiring 6 are formed in the modified SOG film 8. At this time, the position of the contact hole is shifted from the upper surface of the metal wiring 6 like the contact hole 9b due to the misalignment of the mask.
The contact failure does not occur even if is exposed.

For example, if the ion implantation into the organic SOG film 3 is insufficient and an unmodified portion is present in the film (especially in the lower portion), the position of the contact hole is shifted to the unmodified portion. In some cases, during the oxygen plasma ashing for removing the photoresist used as the etching mask for forming the contact holes, the unmodified portion may shrink. As a result, there is a concern that a recess may occur in the hole, and a contact failure may occur, such that the subsequent connection hole wiring cannot be sufficiently buried in the hole.

If an unmodified organic SOG film is exposed in the contact hole, H ₂ O or CH _{2 is} removed from the organic SOG when Cu is to be formed in the contact hole by using the CVD method. ₃ is desorbed, so that the source gas for forming Cu cannot sufficiently enter the contact hole, and there is a fear that incompletely formed Cu may be formed in the contact hole.

On the other hand, in the present embodiment, as described above, since the entire organic SOG film 3 is almost uniformly reformed, only the reformed portion is formed even if the contact hole formation position is shifted. It is exposed and there is no worry as mentioned above.

Step 8 (see FIG. 8): After cleaning the insides of the contact holes 9a and 9b by sputter etching using an inert gas (eg, Ar), the modified SOG film 8 including the insides of the contact holes 9a and 9b is removed. A TiN film as an adhesion layer and a barrier layer is formed thereon by using a magnetron sputtering method or a CVD method.
A Cu film is formed by using a plating method or a plating method.
By using the P method, the surface of the Cu film is polished, and finally, a contact hole wiring 10 made of TiN and Cu is buried in the contact holes 9a and 9b.

Step 9 (see FIG. 9): If necessary, an oxide film or the like on the surface of the connection hole wiring 10 is removed by sputter etching using an inert gas (eg, Ar).

Next, the modified SOG film 8 and the connection hole wiring 10
And the modified SOG film 11 in the same manner as in steps 1 to 4.
Embedded in the modified SOG film 11 and the connection hole wiring 10
The upper metal wiring 12 (lamination of TiN and Cu) electrically connected to the substrate is formed.

In this embodiment, when ions are implanted into the organic SOG film 3, boron ions are introduced into the interface with the silicon oxide film 2 as described above.
The film 4 is hardly peeled off from the silicon oxide film 2.

Table 1 shows the results of evaluating the adhesion strength between the SOG film and the silicon oxide film using a test device having a SOG film (600 nm thick) formed on the silicon oxide film using a tensile strength test apparatus. Is shown. The formed SOG films were of the four types shown in the table, and ten samples were produced for each type. The judgment of the film peeling rate is 5
A tensile test was performed with a tensile force of 00 Kg / cm ² to determine what percentage of the sample had film peeling.

[0052]

[Table 1]

The condition column in Table 1 shows the condition used as the SOG film. What is low pressure oxygen plasma treatment?
The G film was exposed to oxygen plasma. The modified SOG film is formed under the same conditions as in the present embodiment.

As described above, when the modified SOG film is used as the SOG film, the adhesion strength with the underlying silicon oxide film is increased, and the film does not peel off.

FIG. 10 shows the results of measuring the adhesion strength when boron (B ⁺ ) ions were implanted into the SOG film under different conditions in the same test device as in Table 1. The dose was fixed at 1 × 10 ¹⁵ atoms / cm ² and the acceleration energy was changed to 20, 60, 100 and 140 KeV, respectively. In the figure, “unprocessed” refers to a film that has not been subjected to ion implantation, that is, an organic SOG film.

As described above, those without ion implantation are S
Although the adhesion strength between the OG film and the silicon oxide film is low and easily peeled off, the adhesion strength of the ion-implanted film increases as the acceleration energy increases.
Above V, an adhesion strength exceeding 700 kgf / cm ² can be obtained. It is considered that this improvement in the adhesion strength was caused by ions reaching the interface between the SOG film and the silicon oxide film and mixing and recombination of elements at the interface.

The modified SOG films 4, 8, and 11 hardly shrink during oxygen plasma ashing when removing the photoresist used as the etching mask.

Therefore, a recess does not occur when forming the trench 5 and the contact holes 9a and 9b. Therefore, the trench 5 and the contact holes 9a, 9b
The metal wiring 6 and the connection hole wiring 10 can be sufficiently buried therein.

Here, the modified SOG film has excellent oxygen plasma resistance. FIG. 11 shows an index of oxygen plasma resistance, which is evaluated by focusing on the decrease in the thickness of the modified SOG film.
FIG. 3 shows a change in film thickness when a modified SOG film formed by implanting argon (Ar) ions into an organic SOG film is exposed to oxygen plasma. The conditions of ion implantation are as follows: acceleration energy: 140 KeV, dose: 1 × 10
¹⁵ atoms / cm ² .

When the organic SOG film is exposed to oxygen plasma (oxygen plasma treatment), the original organic SOG film (untreated)
When the modified SOG film is exposed to oxygen plasma (oxygen plasma treatment after Ar ion implantation), the original modified SOG film (Ar ion implantation) It was found that the film thickness was hardly reduced as compared with the film thickness of. However, the thickness of the modified SOG film is an organic SOG film.
It is 25% smaller than the film thickness.

From the above results, it was found that the modified SOG film was a film having excellent oxygen plasma resistance.

FIG. 12 shows that each of the organic SOG film (untreated) and the modified SOG film (Ar ion implantation) is subjected to a heat treatment in a nitrogen atmosphere for 30 minutes, and is subjected to a TDS method (Thermal Desor).
The result of evaluation using ption Spectroscopy) is shown. The ion implantation conditions were as follows: acceleration energy: 140 Ke
V, dose amount: 1 × 10 ¹⁵ atoms / cm ² .

This figure shows the amount of desorption with respect to H ₂ O (m / e = 18).
It can be seen that the modified SOG film has little desorption with respect to H ₂ O (m / e = 18). This indicates that by performing ion implantation on the organic SOG film to form a modified SOG film, moisture and hydroxyl groups contained in the organic SOG film are reduced.

FIG. 13 shows an organic SOG film (untreated), an organic SOG film exposed to oxygen plasma (oxygen plasma treatment), and a modified SOG film for the purpose of examining the hygroscopicity of the organic SOG film and the modified SOG film. (Ar ion implantation) is left in the air in a clean room, and the result of evaluating the moisture in the film is shown. The amount of water in the film was determined by the FT-IR method (FourierTr
Using ansform Infrared Spectroscopy), the absorption of the O-H group in the infrared absorption spectrum (around 3500 cm ^-1 )
Was used as an index. The ion implantation conditions are acceleration energy: 140 KeV and dose: 1 × 10 ¹⁵ atoms / cm ² .

It can be seen that when exposed to oxygen plasma, not only the water content before and after the treatment was increased, but also after one day. On the other hand, the modified SOG film not only has not increased after ion implantation, but also has a smaller increase in moisture than the organic SOG film even when left in the air in a clean room.

That is, it is understood that the modified SOG film has lower hygroscopicity than the organic SOG film.

FIG. 14 shows a pressure cooker test (PCT) (humidification test) in order to examine the moisture permeability of the modified SOG film and the organic SOG film.
As a condition, the measurement was carried out in a saturated steam atmosphere at 120 ° C. and 2 atm). Using the FT-IR method,
Absorption peak for O—H in the organic SOG film (3500
The area intensity (in the vicinity of cm ⁻¹ ) was determined, and the relationship with the PCT time was plotted.

A sample (Ar ion implantation: 20 KeV) in which only the surface was modified by ion implantation was prepared, and a sample in which the whole film was modified (Ar ion implantation: 140 KeV) and a sample in which the film was not modified (organic) were used. SOG film: untreated), the following was found.

(A) Unmodified organic SOG film is converted to PC
In the case of T, the absorption intensity around 3500 cm ^-1 (absorption for the OH group) shows a dramatic increase.

(B) In the modified SOG film, the increase in the absorption intensity around 3500 cm ⁻¹ (absorption related to the OH group) is small. A sample in which only the film surface was modified is comparable to a sample in which the entire film has been modified.

From the above results, it can be seen that a layer for suppressing moisture permeability can be formed by implanting ions.

As described above, in the present embodiment, the organic SOG
By introducing impurities into the film by ion implantation, the organic SOG films 3 and 7 become the modified SOG films 4 and 8, reducing the moisture and hydroxyl groups contained in the film and making the film less likely to absorb water. In addition, the adhesion strength with the silicon oxide film 2 in contact with the modified SOG film 4 is increased, and a highly reliable interlayer insulating film can be obtained. (Second Embodiment) A manufacturing method according to a second embodiment of the present invention will be described with reference to FIGS. Steps 1 to 6 (FIGS. 1 to 6) in the first embodiment are the same as those in the second embodiment, and thus description thereof will be omitted, and the subsequent steps will be described. The same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

Step 10 (see FIG. 15): Modified SOG film 8
A mask pattern 13 made of a silicon nitride film (referred to as a silicon nitride film mask 13) is formed on the substrate. Incidentally, the silicon nitride film mask 13 corresponds to the first mask pattern of the present invention.

Step 11 (see FIG. 16): Modified SOG film 8
And a thickness of 600 nm on the silicon nitride film mask 13.
The organic SOG film 14 is formed. This organic SOG film 14
Is the same as in the organic SOG film 3 described above. Incidentally, the organic SOG film 14 corresponds to the third insulating film of the present invention.

Step 12 (see FIG. 17): Organic SOG film 1
4 is subjected to ion implantation to form a modified SOG film 15. The composition and the forming method of the modified SOG film 15 are the same as those of the modified SOG film 4. Also at this time, since the organic SOG film 14 has a substantially uniform thickness over the entire surface of the substrate, the entire organic SOG film 14 is substantially uniformly reformed.

Step 13 (see FIG. 18): Modified SOG film 1
A resist pattern 16 having a stripe shape is formed on the resist pattern 5. The opening of the resist pattern 16 includes the opening of the silicon nitride film mask 13 and has an area larger than that of the silicon nitride film mask 13. Incidentally, the resist pattern 16 corresponds to the second mask pattern of the present invention.

Step 14 (see FIG. 19): Using the resist pattern 16 as a mask, anisotropic etching using a fluorocarbon-based gas as an etching gas is performed to etch the modified SOG film 15 and the modified SOG film 8.
In this case, the modified S has the same opening width as the resist pattern 16.
The OG film 15 is etched, and the silicon nitride mask 1
3, the etching of the modified SOG film 15 is completed, and first, the trenches 17 a and 17
b is formed. Subsequently, using the silicon nitride film mask 13 as a mask, the modified SOG film 8 is etched with the same opening diameter as this mask, and contact holes 17c and 17d communicating with the metal wiring 6 are formed in the modified SOG film 8.

As described above, by using the silicon nitride film mask 13 as an etching stopper, the trenches 17a and 17b and the contact holes 17c and 17d can be formed by one etching.

At this time, even if the formation position of the contact hole is shifted from the upper surface of the metal wiring 6 as in the contact hole 17c due to the misalignment of the mask and the modified SOG film 4 is exposed, the same as the contact hole 9b is formed. No contact failure occurs for that reason.

Step 15 (see FIG. 20): The trenches 17a and 17b and the contact holes 17c and 17 are formed by sputter etching using an inert gas (for example, Ar).
d, the modified SOG including the trenches 17a and 17b and the contact holes 17c and 17d.
A TiN film as an adhesion layer and a barrier layer is formed on the film 15 by using a magnetron sputtering method or a CVD method.
A Cu film is formed thereon by using a CVD method or a plating method, and the surface of the Cu film is polished by using a CMP method. Finally, the Cu film is formed in the trenches 17a and 17b and the contact holes 17c and 17d. Wiring 18 made of TiN and Cu
Is buried. (Third Embodiment) A manufacturing method according to a third embodiment of the present invention will be described with reference to FIGS. Steps 1 to 6 (FIGS. 1 to 6) in the first embodiment are the same as those in the third embodiment, and thus description thereof will be omitted, and the subsequent steps will be described. Further, the same reference numerals are used for the same configurations as the first embodiment and the second embodiment, and the detailed description is omitted.

Step 20 (see FIG. 21): Modified SOG film 8
(However, the film thickness is set to 1200 nm), a resist pattern 20 is formed. This resist pattern 2
The opening of “0” includes the opening of the trench 5 (metal wiring 6), and has an area larger than that of the trench 5.

Step 21 (see FIG. 22): Using the resist pattern 20 as a mask, anisotropic etching is performed using a fluorocarbon-based gas as an etching gas, and the modified SOG film 8 is etched until its film thickness becomes 600 nm. Then, trenches 8a and 8b are formed in the modified SOG film 8.

Step 22 (see FIG. 23): After removing the resist pattern 20, a resist pattern 21 is formed on the modified SOG film 8 again. This resist pattern 2
One opening 21a is located in trenches 8a and 8b.

Step 23 (see FIG. 24): Using the resist pattern 21 as a mask, anisotropic etching using a fluorocarbon-based gas as an etching gas is performed to etch the modified SOG film 8.

Step 24 (see FIG. 25): By removing the resist pattern 21, trenches 8a, 8b and contact holes 22a, 22b leading to the metal wiring 6 are formed in the modified SOG film 8. At this time, even if the formation position of the contact hole is shifted from the upper surface of the metal wiring 6 like the contact hole 22b due to misalignment of the mask when forming the resist pattern 22, the modified SOG film 4 is exposed. No contact failure occurs for the same reason as in the hole 9b.

Step 25 (see FIG. 26): After cleaning the insides of the trenches 8a, 8b and the contact holes 22a, 22b by sputter etching using an inert gas (for example, Ar), the trenches 8a, 8b and the contact holes 22a, 22a, On the modified SOG film 8 including the inside 22b, a TiN film as an adhesion layer and a barrier layer is formed by using a magnetron sputtering method or a CVD method.
A Cu film is formed by a CVD method or a plating method, and the surface of the Cu film is polished by a CMP method. Finally, a connection hole wiring 18 made of TiN and Cu is formed in the contact holes 22a and 22b. Is buried. (Fourth Embodiment) A manufacturing method according to a fourth embodiment of the present invention will be described with reference to FIGS. Steps 1 to 6 (FIGS. 1 to 6) in the first embodiment are the same as those in the fourth embodiment, and thus description thereof will be omitted, and the subsequent steps will be described. Further, the same components as those of the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

Step 30 (see FIG. 27): Modified SOG film 8
A resist pattern 30 is formed on the substrate.

Step 31 (see FIG. 28): Using the resist pattern 30 as a mask, anisotropic etching is performed using a fluorocarbon-based gas as an etching gas, and the modified SOG film 8 is provided with contact holes 31a, 31b is formed.

Step 32 (see FIG. 29): After removing resist pattern 30, contact holes 31a and 31b are formed.
A resist film 32 is applied on the modified SOG film 8 including the inside.

Step 33 (see FIG. 30): A contact hole 3 in the resist film 32 is formed by using a usual exposure technique.
Patterning the portions other than 1a and 31b and modifying SOG
A resist pattern 33 is formed on the film 8. The opening 33a of the resist pattern 33 includes the contact holes 31a and 31b, and has an area larger than that of the contact holes 31a and 31b.

Step 34 (see FIG. 31): Using the resist pattern 33 and the resist film 32 remaining in the contact holes 31a and 31b as a mask, anisotropic etching using a fluorocarbon-based gas as an etching gas is performed, and modified SOG is performed. The film 8 is etched until the film thickness becomes half, and trenches 8a and 8
b is formed.

Step 35 (see FIG. 32): By removing the resist pattern 33 and the resist film 32, the modified SOG film 8 is provided with trenches 8a and 8b communicating with the metal wiring 6.
Then, contact holes 31a and 31b are formed. At this time, even if the position of the contact hole is shifted from the upper surface of the metal wiring 6 like the contact hole 31b due to misalignment of the mask when forming the resist pattern 30, the modified SOG film 4 is exposed. No contact failure occurs for the same reason as in the hole 9b.

Step 36 (see FIG. 33): After cleaning the insides of the trenches 8a and 8b and the contact holes 31a and 31b by sputter etching using an inert gas (for example, Ar), the sputtering method or the CVD method is used. A TiN film as an adhesion layer and a barrier layer is formed, a Cu film is formed thereon using a CVD method or a plating method, and further, the surface of the Cu film is polished using a CMP method,
Finally, the trenches 8a and 8b and the contact holes 31
A connection hole wiring 18 made of TiN and Cu is buried in a and 31b. (Fifth Embodiment) A manufacturing method according to a fifth embodiment of the present invention will be described with reference to FIGS. Note that the fifth embodiment differs from the second embodiment only in steps 12 to 15 (FIGS. 17 to 20) in the second embodiment.
The other steps are the same as those in the second embodiment, and thus the description thereof will be omitted, and here, only the steps that replace steps 12 to 15 in the second embodiment will be described. Also,
The same components as those in the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

Step 40 (see FIG. 34): Organic SOG film 1
4, a silicon nitride film 40 is formed.

Step 41 (see FIG. 35): Over the silicon nitride film 40, ions are implanted into the organic SOG film 14 to form the modified SOG film 15. The modified SOG film 1
The composition and the forming method of 5 are the same as those of the modified SOG film 4. Also at this time, the organic SOG film 14 has a substantially uniform thickness over the entire surface of the substrate.
The whole is almost uniformly reformed.

Step 42 (see FIG. 36): A stripe-shaped resist pattern 16 is formed on the silicon nitride film 40. The opening of the resist pattern 16 includes the opening of the silicon nitride film mask 13 and has an area larger than that of the silicon nitride film mask 13.

Step 43 (see FIG. 37): The silicon nitride film 40 is etched using the resist pattern 16 as a mask. Note that the remaining silicon nitride film 40 corresponds to the second mask pattern of the present invention.

Step 44 (see FIG. 38): After the resist pattern 16 is removed, anisotropic etching using a fluorocarbon-based gas as an etching gas is performed using the patterned silicon nitride film 40 as a mask, and the modified SOG film 15 is removed. Then, the modified SOG film 8 is etched. In this case, the modified SOG has the same opening width as the silicon nitride film 40.
When the film 15 is etched and reaches the silicon nitride film mask 13, the etching of the modified SOG film 15 is completed. First, the trenches 17 a and 17 b are formed in the modified SOG film 15.
Is formed. Subsequently, using the silicon nitride film mask 13 as a mask, the modified SOG film 8 has the same opening diameter as this mask.
Are etched to form contact holes 17c and 17d communicating with the metal wiring 6 in the modified SOG film 8.

As described above, by using the silicon nitride film mask 13 as an etching stopper, the trenches 17a and 17b and the contact holes 17c and 17d can be formed by one etching.

At this time, even if the formation position of the contact hole is shifted from the upper surface of the metal wiring 6 like the contact hole 17c due to the misalignment of the mask and the modified SOG film 4 is exposed, the same as the contact hole 9b is formed. No contact failure occurs for that reason.

Step 45 (see FIG. 39): The trenches 17a and 17b and the contact holes 17c and 17 are formed by sputter etching using an inert gas (for example, Ar).
d, the modified SOG including the trenches 17a and 17b and the contact holes 17c and 17d.
A TiN film as an adhesion layer and a barrier layer is formed on the film 15 by using a magnetron sputtering method or a CVD method.
A Cu film is formed thereon by using a CVD method or a plating method, and the surface of the Cu film is polished by using a CMP method. Finally, the Cu film is formed in the trenches 17a and 17b and the contact holes 17c and 17d. Wiring 18 made of TiN and Cu
Is buried.

Although the embodiments have been described above, technical ideas other than the claims that can be grasped from the embodiments will be described below together with their effects.

(A) A first insulating film (organic SO
Forming a G film 3), introducing an impurity into the first insulating film, burying and forming a first wiring (metal wiring 6) in the first insulating film, Forming a second insulating film (organic SOG film 7) on the second insulating film, forming a third mask pattern (resist pattern 20) on the second insulating film, 3
A step of partially reducing the thickness of the second insulating film based on the mask pattern of (a), a step of forming a fourth mask pattern (resist pattern 21) on the thinned region, and A contact hole 2 communicating with the first wiring is formed in the second insulating film based on the mask pattern.
A semiconductor comprising: a step of forming 2a and 22b; and a step of forming a third wiring (wiring 18) electrically connected to the first wiring at least in the contact hole. Device manufacturing method.

(B) A first insulating film (organic SO) is formed on the substrate.
Forming a G film 3), introducing an impurity into the first insulating film, burying and forming a first wiring (metal wiring 6) in the first insulating film, Forming a second insulating film (organic SOG film 7) on the second insulating film, forming a fifth mask pattern (resist pattern 30) on the second insulating film, 5
In the second insulating film, based on the mask pattern of (1), the second contact holes 31a,
Forming a resist film 32b in the second contact hole and on the second insulating film after removing the fifth mask pattern; Forming a sixth mask pattern 33 having an opening larger than the second contact hole by patterning a portion above the insulating film, and based on the sixth mask pattern,
A step of partially thinning the second insulating film; a step of removing the resist film and the sixth mask pattern remaining in the second contact hole; Forming a third wiring (wiring 18) electrically connected to the first wiring.

(C) Before forming the third wiring (wiring 18) in the contact holes 22a, 22b or the second contact holes 31a, 31b formed in the second insulating film, the second insulating film is formed. A method for manufacturing a semiconductor device, further comprising a step of introducing an impurity into a film.

The present invention is not limited to the above embodiment, and the same operation and effect can be obtained even if the present invention is implemented as follows.

(1) Instead of the organic SOG film, a fluorocarbon film, polyimide, or siloxane-knitted polyimide is used.

(2) In place of Cu as a wiring material, formed of aluminum, gold, silver, silicide, high melting point metal, doped polysilicon, titanium nitride (TiN), tungsten titanium (TiW) or a laminated structure thereof. I do.

(3) TiN as adhesion layer and barrier layer
Has a laminated structure with Ti, TaN, Ta and the like. Or
Instead of TiN, Ti, TaN, Ta or the like is used.

(4) Heat treatment is performed on the modified SOG film. In this case, dangling bonds in the modified SOG film are reduced. Hygroscopicity is further reduced, and permeation of moisture is further reduced.

(5) The composition of the organic SOG film is represented by the general formula (1)
Is replaced with an inorganic SOG film, and ion implantation is performed on the inorganic SOG film. In this case, moisture and hydroxyl groups contained in the inorganic SOG film can be reduced.

(6) In the above embodiment, boron ions are used as ions to be implanted into the organic SOG film. However, any ions may be used as long as they result in modification of the organic SOG film.

Specifically, ions having a relatively small mass such as argon ion, boron ion and nitrogen ion are suitable, and among them, boron ion is most suitable.
In addition to these, the following ions can be expected to have a sufficient effect.

Inert gas ions (helium ion, neon ion, krypton ion, xenon ion, radon ion). Since the inert gas does not react with the organic SOG film, there is no possibility that an adverse effect is caused by the ion implantation.

Elemental element ions of each group of IIIb, IVb, Vb, VIb, VIIb and compound ions thereof. In particular, oxygen,
Aluminum, sulfur, chlorine, gallium, germanium, arsenic, selenium, bromine, antimony, iodine, indium,
Elemental ions of tin, tellurium, lead and bismuth and their compound ions.

Among these, with respect to metal element ions, the dielectric constant of the organic SOG film after ion implantation can be suppressed low.

Elemental ions of group IVa and Va and their compound ions. In particular, elemental ions of titanium, vanadium, niobium, hafnium, and tantalum, and compound ions thereof. Since the oxides of the IVa and Va group elements have a high dielectric constant, the dielectric constant of the organic SOG film after the ion implantation is also high. However, it is not practical unless an interlayer insulating film having a low dielectric constant is required. no problem.

A plurality of types of ions are used in combination. In this case, a more excellent effect can be obtained by the synergistic action of each ion.

(7) In the above embodiment, ions are implanted into the organic SOG film. However, the ions are not limited to ions, but may be atoms, molecules, or particles (in the present invention, these are collectively referred to as impurities). .

(8) As a sputtering method, other than magnetron sputtering, a method such as diode sputtering, high frequency sputtering, quadrupole sputtering or the like may be used.

(9) As a method of sputter etching,
In addition to using an inert gas, a reactive gas (for example, CCl
₄ , SF ₆ ) for reactive ion beam etching (R
IBE, also called reactive ion milling).

(10) Instead of a single crystal silicon substrate (semiconductor substrate), a conductive substrate or an insulating substrate such as glass is used. That is, in the above embodiment, the example in which the wiring is formed on the single crystal silicon substrate is shown. However, for example, a device in which the wiring is formed on an insulating substrate, such as an LCD, is sufficiently used. The present invention can be applied, and even a wiring formed on such an insulating substrate belongs to the concept of “semiconductor device” in the present invention.

[0123]

According to the present invention, it is possible to provide a semiconductor device having excellent reliability and suitable for miniaturization.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a manufacturing process of a semiconductor device according to a first embodiment of the invention.

FIG. 2 is a schematic sectional view showing a manufacturing process of the semiconductor device according to the first embodiment which embodies the present invention;

FIG. 3 is a schematic sectional view showing a manufacturing process of the semiconductor device according to the first embodiment which embodies the present invention;

FIG. 4 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment, which embodies the present invention;

FIG. 5 is a schematic sectional view showing a manufacturing process of the semiconductor device according to the first embodiment which embodies the present invention;

FIG. 6 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment, which embodies the present invention;

FIG. 7 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment which embodies the present invention;

FIG. 8 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment that embodies the present invention;

FIG. 9 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment, which embodies the present invention;

FIG. 10 is a characteristic diagram for explaining the embodiment of the present invention.

FIG. 11 is a characteristic diagram for explaining the embodiment of the present invention.

FIG. 12 is a characteristic diagram for explaining the embodiment of the present invention.

FIG. 13 is a characteristic diagram for explaining the embodiment of the present invention.

FIG. 14 is a characteristic diagram for explaining the embodiment of the present invention.

FIG. 15 is a schematic sectional view showing a manufacturing process of the semiconductor device according to the second embodiment which embodies the present invention;

FIG. 16 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment which embodies the present invention;

FIG. 17 is a schematic sectional view showing a manufacturing process of the semiconductor device according to the second embodiment which embodies the present invention;

FIG. 18 is a schematic sectional view showing a manufacturing process of the semiconductor device according to the second embodiment which embodies the present invention;

FIG. 19 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment which embodies the present invention;

FIG. 20 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment which embodies the present invention;

FIG. 21 is a schematic sectional view showing a manufacturing process of a semiconductor device according to a third embodiment of the invention.

FIG. 22 is a schematic sectional view showing a manufacturing process of the semiconductor device according to the third embodiment which embodies the present invention;

FIG. 23 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the third embodiment which embodies the present invention;

FIG. 24 is a schematic sectional view showing a manufacturing process of the semiconductor device according to the third embodiment which embodies the present invention;

FIG. 25 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the third embodiment which embodies the present invention;

FIG. 26 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the third embodiment which embodies the present invention;

FIG. 27 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment of the present invention;

FIG. 28 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment of the invention;

FIG. 29 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment which embodies the present invention;

FIG. 30 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment of the invention;

FIG. 31 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment which embodies the present invention;

FIG. 32 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment which embodies the present invention;

FIG. 33 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment of the invention;

FIG. 34 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the fifth embodiment embodying the present invention;

FIG. 35 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the fifth embodiment embodying the present invention;

FIG. 36 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the fifth embodiment which embodies the present invention;

FIG. 37 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the fifth embodiment embodying the present invention;

FIG. 38 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the fifth embodiment which embodies the present invention;

FIG. 39 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the fifth embodiment which embodies the present invention;

[Explanation of symbols]

Reference Signs List 1 silicon substrate 2 silicon oxide film (fourth insulating film) 3 organic SOG film (first insulating film) 4 modified SOG film 5 trench 6 metal wiring (first wiring) 7 organic SOG film (second insulating film) 8) Modified SOG film 8a, 8b Trench 9a, 9b Contact hole 10 Connection hole wiring (second wiring) 11 Modified SOG film 12 Upper layer metal wiring 13 Silicon nitride film mask (first mask pattern) 14 Organic SOG Film (third insulating film) 15 Modified SOG film 16 Resist pattern (second mask pattern) 17a, 17b Trench 17c, 17d Contact hole 18 Wiring (third wiring) 20 Resist pattern (third mask pattern) 21 resist pattern (fourth mask pattern) 22a, 22b contact hole 30 resist pattern (fifth mask pattern) Click patterns) 31a, 31b contact hole (second contact hole) 32 resist film 33 a resist pattern (sixth mask pattern) 34a, 34b contact hole 40 a silicon nitride film (second mask pattern)

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Shinichi Tanimoto 2-5-5 Keihanhondori, Moriguchi City, Osaka Prefecture Inside Sanyo Electric Co., Ltd. (72) Inventor Atsuhiro Nishida 2-5-5 Keihanhondori, Moriguchi City, Osaka Prefecture No. 5 Sanyo Electric Co., Ltd. (72) Inventor Yoshikazu Yamaoka 2-5-5 Sanyo Electric Co., Ltd. (72) Inventor Yasunori Inoue 2 Keihanhondori, Moriguchi City, Osaka Prefecture 5-5-5 Sanyo Electric Co., Ltd. F-term (reference) KK25 KK32 KK33 MM01 MM02 MM12 MM13 NN06 NN07 PP06 PP15 PP27 QQ09 QQ13 QQ14 QQ16 QQ23 QQ28 QQ37 QQ48 QQ60 QQ61 QQ62 QQ63 QQ64 QQ65 QQ66 QQ92 RR04 RR06 RR09 SS12 4 SS07 SS12 SS13 SS14 SS15 SS22 TT02 XX01 XX10 XX12 5F058 AD04 AD05 AD06 AF04 AG01 AG06 BA07 BA10 BA20 BD01 BD10 BD19 BF46 BH20 BJ01 BJ02

Claims (12)

[Claims] A first insulating film into which an impurity is introduced;
Forming a second insulating film on the first insulating film; forming a contact hole communicating with the first wiring in the second insulating film. Forming a second wiring electrically connected to the first wiring at least in the contact hole. A step of forming a first insulating film on the substrate; a step of introducing an impurity into the first insulating film; and a step of burying a first wiring in the first insulating film. Forming a second insulating film on the first insulating film; forming a contact hole in the second insulating film that communicates with the first wiring; Forming a second wiring electrically connected to the first wiring. 3. The method according to claim 1, wherein the first insulating film into which the impurity is introduced has a first property.
Forming a second insulating film on the first insulating film; forming a first mask pattern on the second insulating film; A third insulating film is formed on the second insulating film and the first mask pattern.
Forming an insulating film, forming a second mask pattern having an opening larger than the first mask pattern on the third insulating film, and forming the second mask pattern based on the second mask pattern. Forming a trench that reaches the first mask pattern in the third insulating film; and connecting the first wiring to the second insulating film based on the first mask pattern. Manufacturing a semiconductor device, comprising: forming a contact hole; and forming, in at least the contact hole and the trench, a third wiring electrically connected to the first wiring. Method. 4. A step of forming a first insulating film on a substrate; a step of introducing an impurity into the first insulating film; and a step of burying a first wiring in the first insulating film. Forming a second insulating film on the first insulating film; forming a first mask pattern on the second insulating film; Third on the 1st mask pattern
Forming an insulating film, forming a second mask pattern having an opening larger than the first mask pattern on the third insulating film, and forming the second mask pattern based on the second mask pattern. Forming a trench that reaches the first mask pattern in the third insulating film; and connecting the first wiring to the second insulating film based on the first mask pattern. Manufacturing a semiconductor device, comprising: forming a contact hole; and forming, in at least the contact hole and the trench, a third wiring electrically connected to the first wiring. Method. 5. The method according to claim 1, further comprising a step of introducing an impurity into the second insulating film. 6. The method according to claim 3, further comprising the step of introducing an impurity into the third insulating film. 7. The method according to claim 1, further comprising the step of forming a fourth insulating film under the first insulating film in advance, wherein the step of introducing impurities into the first insulating film includes the steps of: 5. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed under a condition of reaching an interface with the insulating film. 8. The semiconductor device according to claim 1, wherein the first insulating film includes a silicon oxide film containing 1% or more of carbon.
5. The method for manufacturing a semiconductor device according to any one of items 4 to 4. 9. The semiconductor device according to claim 5, wherein the second insulating film includes a silicon oxide film containing 1% or more of carbon.
13. The method for manufacturing a semiconductor device according to item 5. 10. The method according to claim 6, wherein the third insulating film includes a silicon oxide film containing 1% or more of carbon. 11. The method according to claim 1, wherein the first insulating film includes an inorganic SOG film. 12. The semiconductor device according to claim 1, wherein an organic component in the first insulating film is decomposed by introducing an impurity into the first insulating film. Manufacturing method.