JP2002170956A - Thin film transistor and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize both rapidity and stability of a device. SOLUTION: The nitrogen concentration in a range of 10 nm from an interface between a polycrystalline silicon film 2 and an SiO2 gate insulating film 5 is made higher than the nitrogen concentration in other parts of the SiO2 gate insulating film 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method of manufacturing the same, and more particularly, to a polycrystalline silicon thin film transistor (TFT) used as a data driver and a gate driver of an active matrix type liquid crystal display device or a pixel switching element. The present invention relates to a thin film transistor characterized by a gate insulating film structure for achieving both high speed and stability in a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, liquid crystal display devices have been used for OA terminals, projectors, etc. because of their small size, light weight, and low power consumption. In particular, for a high quality liquid crystal display device, an active matrix type liquid crystal display device provided with an active switching element for each pixel is used.

With the recent increase in definition and quality of liquid crystal display devices, voltages applied to gate lines or data lines of address TFTs or pixel switching TFTs of such active matrix type liquid crystal display devices are controlled. A TFT using a polycrystalline silicon thin film capable of achieving high mobility as an active layer is used as a driving driver in a peripheral portion of a pixel.

Here, a conventional TFT will be described with reference to FIG. FIG. 8 is a schematic cross-sectional view of a conventional TFT. A PCVD method (plasma CVD) is formed on a glass substrate 31 via a SiN film and a SiO ₂ film (not shown) serving as a base insulating film.
Then, an amorphous silicon film having a thickness of, for example, 50 nm is deposited by using the above method, and then converted into a polycrystalline silicon film by performing laser annealing using an excimer laser.

Then, the polycrystalline silicon film is etched into a predetermined-shaped island region by dry etching to form a polycrystalline silicon island pattern 32.
Again, the thickness is, for example, 30 nm by the PCVD method.
Then, after depositing an Al film by a sputtering method, a gate electrode 34 is formed by performing dry etching.

[0006] Then, using the gate electrode 34 as a mask, P
After an n-type source / drain region 35 is formed by ion-implanting an n-type impurity such as (phosphorus), an SiO ₂ film 36 and a SiN film 37 are sequentially deposited on the entire surface to form an interlayer insulating film. After forming contact holes for the source / drain regions 35 and the gate electrode 34, Ti, Al, and Ti are sequentially deposited on the entire surface and patterned to form a gate extraction electrode 38 and a source / drain electrode having a Ti / Al / Ti structure. By forming 39, a basic configuration of the TFT is obtained.

However, in such a polycrystalline silicon TFT, a polycrystalline silicon film is formed by crystallizing an amorphous silicon film using a laser beam. Hydrogen contained is liberated and the surface irregularities increase.

[0008]

If the surface unevenness is large, the gate insulating film 3 caused by the step coverage will not be formed.
The variation of the threshold voltage _Vth due to the non-uniformity of the film thickness distribution of No. 3 becomes large. To eliminate such variation of _Vth , the gate insulating film 33 may be made thinner. Leakage current increases and the TFT
However, there is a problem that the off-state current of the device deteriorates.

In addition, when the leakage current increases, dielectric breakdown often occurs, and it is very difficult to achieve both high speed and stability of the device.

Accordingly, an object of the present invention is to achieve both high speed and stability of a device.

[0011]

Here, means for solving the problems in the present invention will be described with reference to FIG.
FIG. 1 is a schematic sectional view of a thin film transistor.
Reference numeral 6, 7 and 8 in FIG, respectively, the gate electrodes, n ^-
Type LDD region and n ⁺ type source / drain regions. See FIG. 1 In order to achieve the above-mentioned object, the present invention provides an insulating substrate 1
Above, at least, in the polycrystalline silicon film 2 and a thin film transistor having a SiO ₂ gate insulating film 5, the polycrystalline silicon film 2 and the SiO ₂ gate insulating film 5 surfactant 1
The nitrogen concentration in the range of 0 nm is higher than the nitrogen concentration in other portions of the SiO ₂ gate insulating film 5, for example, 2 ×
10 ^{20 to} 2 × 10 ²¹ cm ⁻³ , or photoelectron spectroscopy by X-ray irradiation (ESCA: Electron Spect)
roscopy for Chemical Anal
(ysis) method.

As described above, the polycrystalline silicon film 2 and the SiO ₂
Leakage current can be reduced by setting the nitrogen concentration in the range of 10 nm from the interface of the gate insulating film 5 higher than the nitrogen concentration in other portions of the SiO ₂ gate insulating film 5.

The nitrogen concentration in the nitrogen-rich region 3 is preferably, for example, 2 × 10 ²⁰ to 2 × 10 ²¹ cm ^-3, and if it is less than 2 × 10 ²⁰ cm ^-3 ,
The effect of reducing the leak current is low. On the other hand, when the leakage current exceeds 2 × 10 ²¹ cm ⁻³ , the threshold value V _th becomes negative and normal transistor operation cannot be performed. The nitrogen concentration in the nitrogen-rich region 3 is 10% in the quantification by the ESCA method.
It is desirable to make the following.

When the thickness of the SiO ₂ gate insulating film 5 exceeds 40 nm, the uniformity in the film thickness distribution is improved, the coverage of the polycrystalline silicon film 2 with respect to the irregularities is improved, and the nitrogen-rich region 3 is provided. Since the necessity is reduced, it is suitable for a thin film transistor having a thickness of 40 nm or less, that is, a finer thin film transistor, whereby high speed and improved stability can be achieved.

Further, according to the present invention, in a method of manufacturing a thin film transistor, a polycrystalline silicon film 2 is formed on an insulating substrate 1 and then a gas atmosphere of N ₂ O, NO, NH ₃ , or N ₂ is formed. And a step of performing a plasma treatment in the inside.

As described above, the surface of the polycrystalline silicon film 2 is oxidized by plasma treatment in a gas atmosphere of N ₂ O, NO, NH ₃ , or N ₂ , thereby reducing surface irregularities. And the interface state can be reduced, and the nitrogen-rich region 3 can be formed.

In this case, when N ₂ O is used, the SiO ₂ film 4 can be continuously formed by continuously flowing the silane-based gas without stopping the gas flow and the discharge. It is suitable. On the other hand, NH ₃ or N
_{When 2} is used, the nitrogen concentration in the nitrogen-rich region 3 is likely to be high, so that the control of the conditions in the plasma processing step requires precision in order to suppress the fluctuation of _Vth .

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Here, an embodiment of the present invention will be described with reference to FIGS. 2 to 7. First, referring to FIGS. 2 and 3, the embodiment of the present invention will be described. A manufacturing process of a thin film transistor (TFT) will be described. FIGS. 2 (a) see First, the thickness of the TFT substrate, for example, SiO ₂ on the glass substrate 11 of 1.1mm transparent, thickness using a PCVD method, for example, as a 200nm base insulating film After sequentially depositing a film (not shown) and an amorphous silicon film 12 having a thickness of, for example, 50 nm, 45
Anneal at 0 ° C. for 2 hours in a nitrogen gas atmosphere at normal pressure to release hydrogen in the amorphous silicon film 12, and then use a XeCl excimer laser to obtain 400 mJ / c
The amorphous silicon film 12 is converted into a polycrystalline silicon film by polycrystallizing the amorphous silicon film 12 by performing scanning and laser annealing while overlapping the laser light 13 with the power of m ² while overlapping.

Next, as shown in FIG. 2B, the polycrystalline silicon film is subjected to dry etching to form a polycrystalline silicon island pattern 14, and then the polycrystalline silicon island pattern 14 is formed by a PCVD apparatus ( Area of parallel plate electrode: 50cm × 40c
m), N ₂ O gas is introduced and, for example, 40P
A plasma treatment is performed for 30 minutes in the N ₂ O plasma 15 which has been turned into plasma at a temperature of 350 ° C. and a power of 400 W under the pressure of a.

By this plasma treatment, the surface of the polycrystalline silicon island pattern 14 is oxidized to reduce the surface irregularities, reduce the interface state, and reduce
A nitrogen-rich layer 16 mainly composed of SiO ₂ having a thickness of about nm is formed.

Referring to FIG. 2 (c)._TwoStop introduction of O gas and power application
H without_TwoSiH using gas as carrier gas_Four
Gas is introduced and SiH_FourAnd N_TwoPCV made from O
According to Method D, at 350 ° C., the thickness is, for example, 3
0nm SiO _TwoAfter the film 17 is continuously formed,
At 450 ° C for 2 hours in a nitrogen gas atmosphere at normal pressure.
To

Next, as shown in FIG. 2 (d), the thickness is, for example,
After forming a 300 nm Al film, Cl ₂ + BCl ₃
The gate electrode 19 is formed by performing dry etching using + SiCl ₄ gas.

Next, the gate insulating film 18 is formed by selectively removing the SiO ₂ film 17 and the nitrogen rich layer 16 by performing dry etching using CHF ₃ gas.

Next, as shown in FIG. 3E, the P ions 20 are accelerated by, for example, 90 keV.
Energy, 1 × 10 ¹⁴cm^-2Ion implantation at a dose of
By doing so, n is added to the polycrystalline silicon island pattern 14.
^-LDD (Lightly Doped Drain)
n) Form a region 21. In this case, acceleration
Due to energy considerations, only the gate electrode 19 is ion implanted.
It becomes a screen.

Subsequently, as shown in FIG. 3 (f), the P-ion 22 is ion-implanted at an acceleration energy of, for example, 10 keV and at a dose of 2 × 10 ¹⁵ cm ⁻² , thereby forming the polysilicon island pattern 14.
The n ⁺ -type source / drain regions 23 are formed in the exposed portions of the above. Note that, in this case, the gate insulating film 18 also serves as an ion implantation mask due to acceleration energy, and the region immediately below the gate insulating film 18 remains as the n ⁻ -type LDD region 21.

Next, with a XeCl excimer laser,
For example, at a power of 250 mJ / cm ² , an n ^- type LDD
The impurities implanted into the region 21 and the n ⁺ -type source / drain regions 23 are activated.

Next, as shown in FIG. 3 (g), the entire surface is made of SiO ₂ having a thickness of, for example, 30 nm.
After a film 24 and a 370 nm SiN film 25 are sequentially deposited to form an interlayer insulating film, the SiN film 25 is selectively formed by performing dry etching using CF ₄ + O ₂ gas using the SiO ₂ film 24 as an etching stopper layer. Then, by performing wet etching using an etchant composed of HF + NH ₄ F + H ₂ O to remove the exposed SiO ₂ film 24, the n ⁺ -type source / drain region 23 and the gate electrode are removed. 1
9 is formed.

Next, a thickness of, for example, 100 n
m, a 200 nm Al film, and a 100 nm Ti film are sequentially deposited and then patterned to form a gate extraction electrode 26, a source / drain electrode 27 having a Ti / Al / Ti structure, and integrated with them. The basic configuration of the n-channel type TFT can be obtained by forming the wiring of FIG.

Referring to FIG. 4, FIG. 4 shows the SIMS (S
secondary Ion Mass Spectro
a nitrogen concentration death profile measured by the SCOPE method, in which the nitrogen concentration in the gate insulating film 18 in a range of about 10 nm from the interface between the polycrystalline silicon island pattern 14 and the gate insulating film 18 is higher than in other regions, This region corresponds to the nitrogen-rich layer 16 described above.

In this case, in FIG.
8, a nitrogen peak of 3 × 10 ²⁰ cm ⁻³ is observed. The nitrogen peak at about 1 × 10 ²³ cm ⁻³ on the polycrystalline silicon island pattern 14 side is considered to be due to a matrix effect unique to the SIMS method.

FIG. 5 shows a nitrogen concentration death profile of the same TFT by the ESCA method. The peak of the nitrogen concentration in the vicinity of the interface between the polysilicon island pattern 14 and the gate insulating film 18 has an atomic concentration of about 4%. You can see that it has become.

The quantification by the ESCA method is generally performed by using SI
It is understood that although the accuracy is inferior to the MS method, the nitrogen concentration can be measured by the ESCA method when this level of nitrogen is contained.

FIG. 6 shows the channel length of the n-channel TFT according to the embodiment of the present invention, that is, the case where the gate length W is 3 μm, the gate width L is 5 μm, and V _d = 1 V. I
_The drain current I _d obtained from the _d− V _g curve is I _d = 1 ×
It is a plot of a change in threshold voltage V _th at 10 ⁻⁹ A.

As is apparent from the figure, as the nitrogen concentration increases near the interface between the polysilicon island pattern 14 and the gate insulating film 18, V _th shifts to the negative side, and
At x10 ²¹ cm ^-3 , V _th = 0, and at 2 × 10 ²¹ cm ^-3 or more, V _th <0, _preventing normal transistor operation. Therefore, the nitrogen concentration is 2 × 10 ²¹ cm ^−3.
It is desirable to make the following.

FIG. 7 shows a channel length in the n-channel TFT according to the embodiment of the present invention, that is, a gate length W of 3 μm, a gate width L of 5 μm, and a drain voltage V _d of V _d = 5 V. FIG. 4 is a diagram showing a deterioration rate Δμ / μ of mobility μ when a gate voltage _Vg is changed in a state where the gate voltage Vg is changed.

As is apparent from FIG._TwoO plasma processing
When processing is performed, N _TwoO plasma treatment
Degradation of mobility μ is smaller than when no
In particular, V_thThe degradation rate in the vicinity has been significantly improved
It is understood that there is.

From this, it is presumed that the N ₂ O plasma treatment reduces the interface state at the polycrystalline silicon / SiO ₂ interface, and it is understood that the reliability can be improved. You.

Although the embodiments of the present invention have been described above, the present invention is not limited to the configurations and conditions described in the embodiments, and various modifications are possible. For example,
In the above embodiment, the N ₂ O plasma treatment is performed to reduce the interface state and to form the nitrogen-rich layer 16. However, the plasma treatment is not limited to N ₂ O. Plasma treatment using NO, NH ₃ , or N ₂ may be used.

However, when NO, NH ₃ , or N ₂ is used, the step of forming a SiO ₂ film into which SiH ₄ has been introduced cannot be performed continuously. Also,
When NH ₃ or N ₂ is used, the nitrogen-rich layer 16
Since the nitrogen concentration tends to increase in the plasma processing, it is necessary to control the conditions in the plasma processing step with high accuracy in order to suppress the fluctuation of _Vth .

In the above embodiment, the LD
Adopts a D structure, are those not necessarily provided, the carrier movement direction of the width of the gate electrode width of the gate insulating film, i.e., a simple by this be the same as the gate length, n ⁺ -type regions The source / drain region may be constituted only by the above.

In the above embodiment, the plasma treatment and the formation of the SiO ₂ film are performed at 350 ° C., but the temperature range may be any temperature that does not affect the substrate used. In the case where a glass substrate is used, for example, the temperature may be 450 ° C. or less.

Further, in the above embodiment, Si
O ₂ and the formation of the film be performed by using the SiH ₄ is SiH ₄
It is not limited to this, and any silane-based gas may be used.
For example, disilane (Si ₂ H ₆ ) may be used.

In the above embodiment, the plasma processing and the SiO ₂ film forming step are performed continuously in the same chamber, but may be performed in a batch using different reaction apparatuses. Things.

In the above embodiment, the thickness of the polycrystalline silicon film is set to 50 nm.
However, the present invention is not particularly limited to this, but when the film thickness is reduced to about 30 nm, a large increase in gate leakage is not observed, but the variation in characteristics between elements is large. Variation is reduced by applying the plasma treatment, and reliability is improved.

Further, in the above embodiment, Si
Although the thickness of the O ₂ film is set to 30 nm, it is not particularly limited. However, when the thickness of the SiO ₂ film is set to 40 nm or more, the uniformity of the film thickness is improved, the coverage of the polycrystalline silicon film with respect to the irregularities is improved, and the necessity of performing the plasma treatment of the present invention is reduced.
It is particularly effective in the case of nm or less.

Further, in the above-described embodiment, the description has been made of the n-channel type TFT, but the n-channel type TF
The present invention is not limited to T, but is also applicable to p-channel TFTs. In that case, B ions or BF ₂ ions may be used in the source / drain region formation step.

Here, referring again to FIG.
Detailed features will be described. (Supplementary Note 1) On the insulating substrate 1, at least a polycrystalline silicon
Recon film 2 and SiO _TwoA thin film transistor provided with a gate insulating film 5
In the transistor, the polycrystalline silicon film 2 and the S
iO_TwoWithin 10 nm from the interface of the gate insulating film 5
Nitrogen concentration,_TwoOther parts of the gate insulating film 5
Thin film transistor characterized by higher than nitrogen concentration
Ta. (Supplementary Note 2) The above polycrystalline silicon film 2 and SiO_TwoGate
Nitrogen concentration within 10 nm from interface of insulating film 5
Is 2 × 10²⁰~ 2 × 10^{twenty one}cm^-3Is characterized by
The thin film transistor according to claim 1, wherein (Supplementary Note 3) The above polycrystalline silicon film 2 and SiO_TwoGate
Nitrogen concentration within 10 nm from interface of insulating film 5
Quantifies by photoelectron spectroscopy by X-ray irradiation
2. The thin film according to claim 1, wherein the content is 10% or less.
Transistor. (Supplementary Note 4) The SiO_TwoWhen the thickness of the gate insulating film 5 is 4
Any of supplementary notes 1 to 3, wherein the thickness is 0 nm or less
2. The thin film transistor according to claim 1. (Supplementary Note 5) Forming a polycrystalline silicon film 2 on an insulating substrate 1
After that, N_TwoO, NO, NH_ThreeOr N_TwoNo
Equipped with a process of plasma processing in some gas atmosphere
A method for manufacturing a thin film transistor. (Supplementary Note 6) SiO_TwoMembrane
6. The method according to claim 5, further comprising a step of forming a film.
A method for manufacturing a thin film transistor. (Supplementary Note 7) The above SiO_TwoThe film formation process
In the same reaction chamber as the plasma treatment,
After the power is supplied, the
The process is characterized in that it is a process of introducing
7. The method for manufacturing a thin film transistor according to supplementary note 6. (Supplementary Note 8) The above SiO_TwoPlasma chemistry for film formation
It is characterized in that it is performed at a temperature of 450 ° C. or less using vapor phase growth.
The production of the thin film transistor according to Appendix 6 or 7
Construction method.

[0048]

According to the present invention, since the surface of the polycrystalline silicon thin film polycrystallized by laser annealing is plasma-treated in a nitrogen-containing gas, the surface roughness of the polycrystalline silicon thin film can be reduced and the interface state can be reduced. And a nitrogen-rich layer can be formed in the vicinity of the interface, whereby the leakage current can be reduced and the reliability of the device characteristics can be increased. A thin film transistor can be manufactured with good reproducibility.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process partway through an embodiment of the present invention.

FIG. 3 is an explanatory view of a manufacturing process of the embodiment of the present invention after FIG. 2;

FIG. 4 is a nitrogen concentration death profile by a SIMS method according to the embodiment of the present invention.

FIG. 5 is a nitrogen concentration death profile by the ESCA method according to the embodiment of the present invention.

FIG. 6 is an explanatory diagram of nitrogen concentration dependence of V _th of a TFT according to an embodiment of the present invention.

FIG. 7 is an explanatory diagram of N ₂ O processing dependence of V _th reliability of a TFT according to an embodiment of the present invention.

FIG. 8 is a schematic sectional view of a conventional TFT.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 insulating substrate 2 polycrystalline silicon film 3 nitrogen-rich region 4 SiO ₂ film 5 SiO ₂ gate insulating film 6 gate electrode 7 n ⁻ type LDD region 8 n ⁺ type source / drain region 11 glass substrate 12 amorphous silicon film 13 laser light Reference Signs List 14 Polycrystalline silicon island pattern 15 N ₂ O plasma 16 Nitrogen rich layer 17 SiO ₂ film 18 Gate insulating film 19 Gate electrode 20 P ion 21 n ^- type LDD region 22 P ion 23 n ⁺ type source / drain region 24 SiO ₂ Film 25 SiN film 26 gate extraction electrode 27 source / drain electrode 31 glass substrate 32 polycrystalline silicon island pattern 33 gate insulating film 34 gate electrode 35 n-type source / drain region 36 SiO ₂ film 37 SiN film 38 gate extraction electrode 39 source・ Drain electrode

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Yoshiki Ebiko 4-1-1, Kamidadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa F-term within Fujitsu Limited (reference) 5F058 BD04 BD10 BD15 BH16 BJ04 5F110 AA01 AA06 BB02 CC02 DD02 DD13 EE03 EE38 EE44 FF02 FF04 FF05 FF07 FF09 FF30 FF36 GG02 GG13 GG25 GG28 GG29 GG58 HJ01 HJ04 HJ13 HJ23 HL03 HL04 HL12 HM15 NN03 NN04 NN23 NN24 PP03 PP05 PP35 QQ09 QQ11

Claims (5)

[Claims] At least a polycrystalline silicon is provided on an insulating substrate.
Recon film and SiO _TwoThin film transformer with gate insulating film
In the transistor, the polycrystalline silicon film and the SiO_Two
Nitrogen concentration within 10 nm from the interface of the gate insulating film
The degree is SiO_TwoNitrogen concentration in other parts of gate insulating film
A thin film transistor characterized by being higher. 2. A nitrogen concentration within a range of 10 nm from an interface between the polycrystalline silicon film and the SiO ₂ gate insulating film,
2. The thin film transistor according to claim 1, wherein the thickness is 2 × 10 ^{20 to} 2 × 10 ²¹ cm ⁻³ . 3. A nitrogen concentration within a range of 10 nm from an interface between the polycrystalline silicon film and the SiO ₂ gate insulating film,
10 in photoelectron spectroscopy quantification by X-ray irradiation
%. The thin film transistor according to claim 1, wherein 4. A process for forming a polycrystalline silicon film on an insulating substrate and then performing a plasma process in a gas atmosphere of N ₂ O, NO, NH ₃ or N _2. Manufacturing method of a thin film transistor. 5. The method for manufacturing a thin film transistor according to claim 4, further comprising a step of forming an SiO ₂ film continuously with said plasma processing.