JP2000195793A - Method of forming polycrystalline silicon film - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the more effective gettering in a gettering process by moving a nucleus forming precursor substance in the thickness direction of a Si film to absorb it in a gettering layer. SOLUTION: On the surface of a substrate 1 an SiO2 film 2 and a Si film 50a are deposited, and the surface of the Si film 50a is coated with nickel acetate water soln. and heat treated such that Ni diffuses in the Si film 50a and acts as a catalyst (nucleus forming precursor substance) to accelerate the polycrystallization of Si. On the polycrystallized Si film 50a an Si film 51 is deposited, implanted with P and irradiated by a laser to polycrystallize the Si film 51. By the gettering action of P, Ni atoms in the Si film 50a are absorbed in the Si film 51, and then the Si film 51 is removed by the chemical, mechanical polishing using a manganese oxide type slurry.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for producing a polycrystalline silicon film, and more particularly to a method for producing a polycrystalline silicon film in which an amorphous silicon film is polycrystallized using a nucleation precursor. The polycrystalline silicon film is applied to an active region of a thin film transistor (TFT) of an active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art TF using polycrystalline silicon for an active region
T can be applied not only to switching of each pixel of the liquid crystal display device, but also to its peripheral driving circuit. For this reason, the display unit and the driving unit can be arranged on one glass substrate. The TFT of the display portion is required to have a characteristic of a small off-current in order to hold the voltage of the pixel electrode.

In order to reduce the off current, it is necessary to form a high quality polycrystalline silicon film. However, the glass used for the substrate of the liquid crystal display device has a softening point of about 600.
It cannot be heated above this temperature because it is in ° C. A technique for forming high-quality polycrystalline silicon below the softening point of glass has been desired.

A technique is known in which an amorphous silicon film is formed on a glass substrate, and the amorphous silicon film is irradiated with an excimer laser to melt the amorphous silicon and make the amorphous silicon polycrystalline. The characteristics of a TFT using a polycrystalline silicon film formed by this method as an active region are sensitive to the energy of the irradiated excimer laser. Therefore, it is necessary to strictly control the energy of the excimer laser and its in-plane distribution, which is not a method suitable for mass production.

[0005] It is also possible to heat a glass substrate to a temperature slightly lower than its softening point and to polycrystallize amorphous silicon by thermal energy. However, this method requires heat treatment for a long time such as ten and several hours, and is not suitable for mass production. Further, the glass substrate may be deformed by a high temperature close to the softening point.

Japanese Unexamined Patent Publication No. 6-333951 and Japanese Unexamined Patent Publication No. 6-318701 discloses a method for adding silicon (Ni) of about 1 × 10 ¹⁸ cm ⁻³ to amorphous silicon, which is necessary for polycrystallization of silicon. There is disclosed a technology capable of lowering the temperature. Further, Japanese Patent Application Laid-Open No. 8-330602 discloses a technique for suppressing the effect of nickel added to silicon on device characteristics. This technique uses the gettering action of phosphorus added to the source and drain regions of the TFT to reduce the nickel concentration in the channel.

[0007]

According to the additional experiment of the present inventors, it has been found that it is difficult to obtain a TFT having sufficiently small off-state current with the technique described in Japanese Patent Application Laid-Open No. 8-330602. . Further, TFTs used in peripheral driving circuits are required to have higher field-effect mobility.

An object of the present invention is to provide a method for manufacturing a polycrystalline silicon film suitable for manufacturing a TFT having a small off-current and a large field-effect mobility.

[0009]

According to one aspect of the present invention, a step of forming an amorphous silicon film containing a nucleation precursor on a surface of a substrate, and crystallizing the silicon film by applying energy to the silicon film. Forming a gettering layer having a gettering action on the nucleation precursor on the surface of the silicon film; and forming the gettering layer in the silicon film by the gettering layer. A method for producing a silicon film, comprising: a gettering step of absorbing the nucleation precursor and a step of removing the gettering layer that has absorbed the nucleation precursor.

In the gettering step, the nucleation precursor moves in the thickness direction of the silicon film and is absorbed by the gettering layer. For this reason, gettering can be performed more efficiently than in the case of moving in the in-plane direction.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a method for manufacturing a silicon film according to a first embodiment of the present invention will be described.

On the surface of the glass substrate 1, SiH ₄ and N ₂ O
Excited Chemical Vapor Deposition (PE-CVD)
To deposit a SiO ₂ film 2 having a thickness of 300 nm. S
The conditions for forming the iO ₂ film 2 include, for example, a substrate temperature of 300 ° C.
The pressure is 40 Pa and the high frequency applied power is 350 W.

A silicon film 50a having a thickness of 40 nm is formed on the SiO ₂ film 2 by PE-CVD using SiH ₄ and H _2.
Is deposited. The conditions for forming the silicon film 50a are, for example,
Substrate temperature 250 ° C, pressure 100Pa, high frequency applied power 8
0W. Silicon film 50a formed under these conditions
Is in an amorphous state.

On the surface of the silicon film 50a, a concentration of 10 pp
m of nickel acetate aqueous solution is applied by spin coating. Thereafter, heat treatment is performed at a substrate temperature of 550 ° C. for 4 hours. At this time, Ni diffuses into the amorphous silicon film 50a,
This Ni functions as a catalyst (nucleation precursor), and promotes polycrystallization of silicon.

In order to crystallize a portion which is not crystallized and remains amorphous, a XeCl excimer laser is irradiated. The energy density of the laser beam is 400 mJ / c
m ² . Note that when sufficient polycrystallization can be performed only by heat treatment, it is not necessary to perform excimer laser irradiation.

As shown in FIG. 1B, a 40 nm-thick amorphous silicon film 51 is deposited on the polycrystallized silicon film 50a by PE-CVD. Phosphorus (P) is implanted into the silicon film 51 by using an ion doping method. For this implantation, for example, PH ₃ diluted to 10% with hydrogen is used as a doping gas, the acceleration voltage is 3 kV, and the dose is 2 × 10 ^{15 in} terms of phosphorus ions.
cm ^-2 .

As shown in FIG. 1C, the silicon film 51 is polycrystallized by irradiating a XeCl excimer laser.
Thereafter, heat treatment is performed at a temperature of 550 ° C. for 2 hours. Ni atoms in the silicon film 50a are absorbed by the silicon film 51 by the gettering action of phosphorus. The silicon film 5
Gettering may be performed in a state where 1 is amorphous.

Ni in the silicon film after the gettering process
When the concentration was measured by secondary ion mass spectrometry (SIMS), the peak concentration of Ni in the silicon film 51 was 3 × 1.
0 ¹⁹ cm ^-3 , whereas Ni in the silicon film 50a
The concentration was below the detection limit, ie, 1 × 10 ¹⁷ cm ⁻³ .

As shown in FIG. 1D, a silicon film 51 is formed.
Is removed. The removal of the silicon film 51 is performed by chemical mechanical polishing (CMP). The slurry used was a manganese oxide-based slurry, and the polishing liquid was water and abrasive at a weight ratio of 10%.
It is a mixture of 0 to 10. For example, MnO, MnO ₂ , Mn ₃ O ₄ , Mn ₂ O ₃ or the like can be used as the slurry.

When CMP is performed under these conditions, the silicon film 5
1 is removed and the color of the substrate surface changes when the silicon film 50a is exposed. For this reason, the end point of polishing can be clearly known from the appearance. As the polishing liquid, a mixture of water and abrasive grains in a weight ratio of 100 to (2 to 15) may be used.

In the conventional method, Ni atoms in the channel region of the TFT are absorbed in the source / drain region. That is, Ni atoms move in the in-plane direction of the silicon film. In addition, the region where Ni is to be removed and the region where Ni is absorbed are:
Mostly touch with a line.

On the other hand, in the first embodiment, FIG.
In the step (C), the silicon film 5 from which Ni should be removed
Oa and the silicon film 51 for gettering Ni are in contact with each other on a wide surface. The thickness of the silicon film 50a is about several tens nm to several hundreds nm, and the thickness of the N
The i atom moves in its thickness direction. That is, the distance to be moved by gettering is at most several tens nm to several hundred nm.
, Which is shorter than when moving in the in-plane direction. Therefore, Ni can be efficiently gettered.

Next, a method of manufacturing a TFT using the silicon film 50a manufactured in the first embodiment will be described with reference to FIG.

As shown in FIG. 2A, the glass substrate 1
SiO on the surface_TwoA film 2 is formed. SiO_TwoOf membrane 2
An active region 50 made of polycrystalline silicon is formed thereon.
ing. The active region 50 is formed by the method of the first embodiment.
The formed polycrystalline silicon film 50a is patterned and shaped.
Is done. The etching of the silicon film 50a is performed by CF _FourWhen
O_TwoBy reactive ion etching (RIE) using
Can be performed.

The active region 50 is covered with SiO_TwoMembrane 2
On top of SiO_Two120nm thick gate insulating film made of
23 are formed. The gate insulating film 23 is formed by SiH_Four
And N _TwoThis is performed by PE-CVD using O.

A 300 nm thick gate electrode 25 made of an AlSi alloy is formed on a part of the surface of the gate insulating film 23 above the active region 50. In addition, Al
An AlSc alloy may be used instead of the Si alloy. The Si concentration of the gate electrode 25 is, for example, 0.2% by weight.
The deposition of the AlSi alloy film is performed by sputtering using an AlSi alloy target, and the etching of the AlSi alloy film is performed by wet etching using a phosphoric acid-based etchant or RIE using a Cl-based gas.

As shown in FIG. 2B, the gate insulating film 2
3 is patterned to leave the gate insulating film 23a. The gate insulating film 23 is etched by RIE using a mixed gas of CHF ₃ and O ₂ . Gate insulating film 23a
Project about 1 μm on both sides of the gate electrode 25. The active region 50 protrudes on both sides of the gate insulating film 23a.

In the present embodiment, the alignment between the gate electrode 25 and the gate insulating film 23a is performed by using the ordinary photolithography technique. However, the alignment may be performed in a self-aligned manner. For example, the overhanging portion of the gate insulating film 23a can be formed in a self-aligned manner by utilizing the anodic oxidation of the Al gate electrode disclosed in Japanese Patent Application Laid-Open No. 8-332602.

The active region 50 is formed by the ion doping method.
Of the gate insulating film 23a are implanted with phosphorus ions. Phosphorus ions are implanted by using PH ₃ diluted to 10% with H ₂ as a doping gas at an acceleration voltage of 10 kV and a dose of 1 × 10 in terms of phosphorus ions.
Perform under the condition of ¹⁵ cm ^-2 . Under this condition, phosphorus ions are not implanted into the portion covered by the gate insulating film 23a.

As shown in FIG. 2C, a second phosphorus ion implantation is performed by an ion doping method. At this time, the acceleration voltage is 70 kV, and the dose is 2 × 10 ¹⁴ cm ⁻² . Under this condition, phosphorus ions reach below the portions of the gate insulating film 23a that protrude on both sides of the gate electrode 25. Excimer laser annealing is performed to activate the implanted P. The pulse width of the irradiation laser beam is 20
ns, its energy density is 230 mJ / cm ² .

The gate electrode 25 of the gate insulating film 23a
The source low-concentration region 2
6S and the drain low concentration region 26D are formed. A source high concentration region 24S and a drain high concentration region 24D are formed in regions of the active region 50 that protrude on both sides of the gate insulating film 23a. Thus, a TFT having the LDD structure is formed.

The field effect mobility obtained from the current-voltage characteristics of the TFT thus manufactured is about 260 cm ² / Vs
Met. On the other hand, the field effect mobility of the TFT manufactured without performing gettering is about 220 cm ² / Vs
Met. By using a polycrystalline silicon film manufactured by the method according to the first embodiment as an active region, a TFT having a large field-effect mobility can be obtained. Also, the first
TFT using the silicon film according to the embodiment of
The off-state current also decreased.

In the first embodiment, the phosphorus-doped silicon film 51 formed in the step of FIG. 1B functions as a gettering layer. As the gettering layer, a silicon layer doped with boron (B) may be used instead of phosphorus. For example, instead of the phosphorus-doped silicon layer 51 illustrated in FIG. 1B, a 150-nm-thick silicon layer doped with 40 ppm of boron can be used.

The deposition of the boron-doped silicon layer is performed using Si
It can be performed by PE-CVD using H ₄ , H ₂ , and B ₂ H ₆ . The film forming conditions are, for example, a pressure of 100 Pa, a growth temperature of 300 ° C., and a high frequency applied power of 80 W.

FIG. 3 is a sectional view of an active matrix liquid crystal display device to which the TFT shown in FIG. 2C is applied. A 400 nm thick SiO ₂ film 30 is formed on the SiO ₂ film 2 so as to cover the TFT formed on the glass substrate 1. The SiO ₂ film 30 is made of, for example, PE
-Formed by CVD. Contact holes 31 and 32 are formed in the SiO ₂ film 30 at positions corresponding to the drain high concentration region 24D and the source high concentration region 24S, respectively. The contact holes 31 and 32 are formed by, for example, RIE using a mixed gas of CHF ₃ and O _2.
Performed by

A drain bus line 33 is formed on the surface of the SiO ₂ film 30. Drain bus line 33
Are connected to the drain high concentration region 24D via the inside of the contact hole 31. Drain bus line 33
Is a 50 nm thick Ti film and a 200 nm thick AlSi
It has a two-layer structure with an alloy film.

A connection electrode 34 is formed on the surface of the SiO ₂ film 30 at a position corresponding to the contact hole 32 for each high-concentration source region 24S. The connection electrode 34
It is connected to the corresponding source high concentration region 24S.

An SiN film 35 is formed on the SiO ₂ film 30 so as to cover the drain bus lines 33 and the connection electrodes 34. On the surface of the SiN film 35, a pixel electrode 36 made of indium tin oxide (ITO) is formed. The pixel electrode 36 is connected to the connection electrode 34 via a contact hole formed in the SiN film 35. On the SiN film 35, an alignment film 37 is formed so as to cover the pixel electrode 36.

A counter substrate 40 is arranged so as to face the glass substrate 1. On the opposing surface of the opposing substrate 40, I
A common electrode 41 made of TO is formed. A light-shielding film 42 is formed on a predetermined region of the surface of the common electrode 41 where light is to be shielded. A light-shielding film 42 is formed on the surface of the common electrode 41.
An alignment film 43 is formed so as to cover. A liquid crystal material 45 is filled between the two alignment films 37 and 43.

When the TFT according to the first embodiment having the polycrystalline silicon film as the active region 50 is used, an increase in off current can be suppressed. Therefore, the voltage applied to the pixel electrode 36 can be maintained for a long time. Also,
Since a TFT having high field-effect mobility can be obtained, a peripheral driver circuit can be formed over the glass substrate 1.

In the first embodiment, the non-doped amorphous silicon film 5 is formed in the step shown in FIG.
After depositing No. 1, phosphorus ions were implanted, but PE-C
An amorphous silicon film to which phosphorus is added by VD may be deposited. For example, by adding PH ₃ to a growth atmosphere of a silicon film, an amorphous silicon film with a thickness of 200 nm doped with 5 ppm of phosphorus is formed. Subsequently, a gettering process is performed at a temperature of 600 ° C. for 12 hours. According to this method also, Ni can be efficiently gettered.

Next, a method of forming a polycrystalline silicon film according to the second embodiment will be described with reference to FIG. The state shown in FIG. 4A is obtained through the same steps as those of the first embodiment described with reference to FIG.

As shown in FIG. 4B, a silicon film 50 is formed.
A 30 nm thick SiO ₂ film 52 is formed on PE a by PE-CVD. PE-CVD on the SiO ₂ film 52
Thereby, a silicon film 53 having a thickness of 100 nm in an amorphous state is formed. Phosphorus ions are implanted by an ion doping method. The doping condition is, for example, an acceleration voltage of 20
The dose is 1 × 10 ¹⁵ cm ^{−2 in} terms of kV and phosphorus ions. Excimer laser irradiation is performed to polycrystallize the silicon film 53.

In the step shown in FIG.
A gettering process is performed at 0 ° C. for 4 hours. Ni atoms in the silicon substrate 50a are absorbed by the silicon film 53 through the SiO ₂ film 52. Since the Ni atoms move in the thickness direction of the silicon film 50a and are gettered, the Ni atoms can be efficiently gettered as in the case of the first embodiment.

After the gettering process, the silicon film 53 and the SiO ₂ film 52 are removed. The silicon film 53 can be removed by, for example, reactive ion etching (RIE) using a mixed gas of CF ₄ and O ₂ . The etching conditions are, for example, a high-frequency applied power of 1 kW and a pressure of 13 Pa. At this time, the SiO ₂ film 52 functions as an etching stop layer. The SiO ₂ film 52 can be removed by, for example, wet etching using a hydrofluoric acid aqueous solution.

In the second embodiment, since the SiO ₂ film 52 functions as an etching stop layer, the silicon film 50a can be left with good reproducibility.

In the above embodiment, the case where Ni is used as a nucleation precursor when polycrystallizing amorphous silicon is described, but a metal element such as Ge may be used in addition to Ni. In addition, although the case where phosphorus and boron are used as impurities having a gettering effect on a nucleation precursor has been described, other group III or V elements having a gettering effect on a nucleation precursor, for example, G
a, As or the like may be used.

The present invention has been described in connection with the preferred embodiments.
The present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0049]

As described above, according to the present invention,
In the gettering process of Ni atoms in the silicon film,
Ni atoms are moved in the thickness direction of the film. Therefore, gettering can be performed more efficiently than when gettering is performed by moving the film in the in-plane direction of the film.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a substrate for explaining a method of manufacturing a silicon film according to a first embodiment of the present invention.

FIG. 2 shows a TFT using a silicon film according to the first embodiment.
FIG. 4 is a cross-sectional view of a substrate for describing a method for manufacturing the substrate.

FIG. 3 is a cross-sectional view of a liquid crystal display device using the TFT shown in FIG.

FIG. 4 is a cross-sectional view of a substrate for describing a method of manufacturing a silicon film according to a second embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Glass substrate _2, 30, 52 SiO2 film 23 Gate insulating film 24S High-concentration region of source 24D High-concentration region of drain 25 Gate electrode 26S Low-concentration region of source 26D Low-concentration region of drain 31, 32 Contact hole 33 Drain bus line 34 Connection electrode 35 SiN film 36 Pixel electrode 37, 43 Alignment film 40 Counter substrate 41 Common electrode 42 Shielding film 45 Liquid crystal material 50 Active region 50a, 53 Silicon film

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yoshihiro Arimoto 4-1-1 Kamikadanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Sadahiro Kishii 4-chome, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 No. 1 F-term within Fujitsu Limited (reference) PP03 PP10 PP29 PP34 PP38 QQ11 QQ28

Claims (8)

[Claims] A step of forming an amorphous silicon film containing a nucleation precursor on a surface of a substrate; a step of applying energy to the silicon film to crystallize the silicon film; A step of forming a gettering layer exhibiting a gettering action on the nucleation precursor; a gettering step of absorbing the nucleation precursor in the silicon film into the gettering layer; Removing the gettering layer that has absorbed the precursor. 2. The method according to claim 1, wherein the nucleation precursor is Ni. 3. The method according to claim 2, wherein the gettering layer is formed of silicon containing phosphorus or boron. 4. After the step of forming the silicon film in the amorphous state and before the step of forming the gettering layer, the silicon film and the gettering layer are made of a material having different etching resistance. The method for producing a silicon film according to claim 1, further comprising a step of forming an etching stop layer. 5. The method according to claim 4, further comprising, after the step of removing the gettering layer, a step of removing the etching stop layer. 6. The method according to claim 4, wherein the etching stop layer is formed of SiO ₂ . 7. The method according to claim 1, wherein in the step of removing the gettering layer, the gettering layer is removed by chemical mechanical polishing using a manganese oxide-based slurry. 8. The method of manufacturing a silicon film according to claim 7, wherein in the step of removing the gettering layer, chemical mechanical polishing is performed with a weight ratio of water to abrasive grains being 100: (2 to 15).