JP3318551B2 - Thin film transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a thin film transistor (hereinafter referred to as a TFT) formed on an insulating substrate and a method of manufacturing the thin film transistor. The present invention relates to a technique for obtaining a TFT exhibiting characteristics with a small current.

[0002]

2. Description of the Related Art Thin film transistors, which are active elements using a semiconductor thin film layer formed on an insulating substrate, are being applied to various places such as a large area transmission type liquid crystal display and a contact type image sensor. In particular, devices with a focus on polycrystalline silicon have attracted high interest. The requirements for TFTs as active elements are: High transconductance B. These include issues such as increasing the withstand voltage between the source and drain.

The term “transconductance” as used herein is a concept corresponding to the amplification factor of a transistor or a vacuum tube, where _ID is a drain current, V _GS is a gate control voltage,
The V _DS as the source-drain voltage, V _DS = is defined under certain conditions (dI _D / dV _GS).

[0004] Further, the purpose of increasing the withstand voltage between the source and the drain is to realize a configuration in which a leak current does not flow between the source and the drain with respect to a voltage applied between the source and the drain. Specifically, in order to prevent a leak current (also referred to as an off-state current) from flowing between the source and the drain when the TFT is in an OFF state, that is, when a current cannot flow between the source and the drain, That is, the TFT must have a withstand voltage characteristic with respect to the voltage applied to the gate electrode, and therefore, it is necessary to increase the withstand voltage between the source and the drain.

In order to satisfy the above requirements,
Various ideas such as an LDD structure (lightly doped drain structure) and a gate offset structure have been proposed. However, A. At present, a structure that satisfies the requirement indicated by B cannot be completely realized by a simple self-alignment process.

FIG. 1E shows a structure of a TFT which has been conventionally proposed to realize a high breakdown voltage and a low leakage current characteristic. This TFT is called an offset gate structure, and has a source region 17 as shown in FIG.
In addition, a gate offset region 20 is provided between the drain region 19 and the channel forming region 18, and the region is provided near the boundary between the source region 17 and the drain region 19 and the channel forming region 18 (particularly, the boundary between the drain region and the channel forming region 18). (In the vicinity), to reduce the electric field concentration, to increase the breakdown voltage, and to realize low leakage current characteristics.

In the following description, a region where a channel is formed is referred to as a channel formation region, but not all of the channel formation region is necessarily a channel. Generally, a channel having a thickness of several hundreds of mm is formed near the surface facing the gate electrode via the gate insulating film (in FIG. 1, near the interface between the channel forming region 18 and the gate insulating film 14). It is believed that.

Although the gate offset region 20 does not positively have one conductivity type like the channel forming region,
Since it is not directly affected by the electric field from the gate electrode 15,
It functions as a kind of buffer region that does not function as a channel and does not function as a source / drain region. Although not shown here, in the LDD structure (lightly doped drain structure), a region in which an impurity imparting a conductivity type is lightly doped between the channel formation region and the drain region also functions as a buffer region. The purpose of the present invention is to reduce the electric field concentration near the boundary with the drain region and realize high withstand voltage and low leakage characteristics.

The structure of the offset gate type TFT will be described below with reference to FIG. T shown in FIG.
The FT includes a glass substrate 11, a base silicon oxide film 12, a source region 17, a channel formation region 18, a drain region 19,
A silicon oxide film 14, which is a gate insulating film, a gate electrode 15,
Interlayer insulating film 16, source electrode 21, drain electrode 23,
It consists of an offset gate region 20.

In the structure of the TFT shown in FIG. 1E, the concentration of the electric field at the junction (particularly at the boundary between the channel forming region 18 and the drain region 19) caused when an electric field is applied between the source and the drain is reduced. Therefore, an offset gate region 20 is provided, and by providing the offset gate region 20, a reduction in leakage current can be realized.

However, while the offset region 20 contributes sufficiently to increase the breakdown voltage between the source and the drain, the offset gate region 20 itself is a non-doped semiconductor and has a high resistance. Therefore, in the structure shown in FIG. 1, the offset gate region 20 functions as a parasitic resistance connected in series to the channel forming region 18, and the on-state current (when the TFT becomes O
The current flowing between the source and the drain at the time of N, that is, the drain current when the TFT is in the ON state, is reduced.

That is, in the structure shown in FIG. 1E, although the leakage current can be reduced, there is a dilemma that the on-current is reduced. As a result, problems such as a decrease in the ON / OFF ratio and a decrease in the field-effect mobility due to a decrease in the mutual conductance newly occur, and a TFT having satisfactory characteristics cannot be obtained.

On the other hand, when the LDD structure is employed, the degree of reduction of the field effect mobility is smaller than that of the offset gate structure, but the electric field at the end of the drain region is insufficiently relaxed, so that the leakage current is not sufficiently reduced. As in the case of the offset gate structure, no sufficient improvement in characteristics could be expected.

FIGS. 2A to 2E show a procedure for manufacturing a TFT having a conventional offset gate structure. All thin film production methods use a gas phase method. In the following description, items (A) to (E) roughly correspond to reference numerals (A) to (E) indicating steps in the drawings. (A) A base silicon oxide film 12 is formed on a glass substrate 11, an amorphous silicon film is formed thereon, and the amorphous silicon is polycrystallized by thermal solid phase growth or laser annealing (hereinafter referred to as 13). ). (B) The polycrystalline silicon 13 is formed into an island shape by a photolithography process and dry etching to form an active layer island. A silicon oxide film 14 serving as a gate insulating film is formed thereon. (C) Amorphous silicon doped with impurities is formed on the silicon oxide film 14, crystallization and low resistance are performed by heat and activation by excimer laser, and the gate electrode 15 is formed by photolithography and dry etching. Form. (D) Above the silicon oxide film 1 for forming an offset region
6 is formed. (E) The silicon oxide film 16 for forming the offset region is etched to the interface with the gate electrode 15 by anisotropic etching to form a wall of the silicon oxide film at the end of the gate electrode 15 (side surface of the gate electrode). The source region 17 and the drain region 19 are formed in a self-aligned manner by through doping using an output ion doping process.

In this step, since there is a wall of the doping stopper at the end of the gate electrode 15 (formed by the silicon oxide film 15 on the side surface of the gate electrode 15), doping is not performed in a lower region of that portion. As the channel region 18, the source region 17, and the drain region 1.
9, a high resistance region is formed, and an offset gate region 20 in which a gate electric field is not applied is provided.

However, in the step (E), when the silicon oxide film 14 for forming the offset gate region is processed by etching, in-plane non-uniformity of the etching becomes a problem. When the thickness of the silicon oxide film 16 on the side surface of the electrode 15 is not constant in the substrate surface and a large number of TFTs are formed on the substrate surface, it is difficult to obtain a uniform offset length in the substrate surface.

Further, the lower crystalline silicon layer 13 must be through-doped with ions of an element imparting one conductivity type through the silicon oxide film 14, but this is higher than the case where the semiconductor layer is directly doped. Since an accelerating voltage is required, the doping efficiency decreases, and the crystalline silicon layer 13
Damage to the crystalline silicon layer 13 such as amorphization of the amorphous silicon becomes apparent, which causes a decrease in reliability.

As described above, the conventional offset gate structure TFT can increase the breakdown voltage between the source and the drain and reduce the leakage current (off current). There are problems such as a decrease in transconductance, a decrease in field effect mobility, and a self-aligned TF
As compared with T, the number of process steps increased, and variation in characteristics and reduction in yield increased, which was not always preferable.

[0019]

SUMMARY OF THE INVENTION In the present invention, a conventional offset gate structure type TFT and LDD structure type TF are disclosed.
(A) Leakage current (OFF current) without reducing ON current
Decrease. (b) The manufacturing process is not complicated, and the yield is not reduced. It is an object of the present invention to provide a structure of a TFT having such characteristics and a method for manufacturing the same.

[0020]

[First invention] A first invention of the present invention relates to a thin film transistor having a semiconductor layer constituting a source region, a drain region and a channel formation region provided on an insulating substrate. The semiconductor device is characterized in that the thickness of the semiconductor layer in the source / drain region is made smaller than the thickness of the semiconductor layer in the channel formation region.

By adopting the above structure, the difference in film thickness between the channel forming region and the source / drain region can be used as a region for alleviating electric field concentration, similar to the case where the above-described gate offset structure is employed. The effect can be obtained. Further, since the regulation resistance of the gate offset region itself, which is a problem when the gate offset structure is adopted, can be almost ignored, the reduction of the on-current can be minimized.

[Second invention] The present invention relates to a method of manufacturing a thin film transistor for realizing the first invention, wherein a semiconductor layer comprising a source region, a drain region and a channel forming region on an insulating substrate is provided. Forming a gate insulating film on the semiconductor layer, forming a gate electrode layer on the insulating layer, and forming a gate on the gate electrode layer. A step of forming a mask for forming an electrode, and using the mask, performing etching with anisotropy in a direction perpendicular to the substrate, and etching the layer to be the gate electrode and the insulating layer. Etching the semiconductor layer to a predetermined thickness, and doping an impurity imparting one conductivity type using a region left unetched in the step as a mask. And by a step of forming a source region and a drain region, the, compared to the thickness of the semiconductor layer constituting the channel forming region below the gate electrode,
According to another aspect of the present invention, the semiconductor layer forming the source region and the drain region is formed to have a small thickness.

According to the structure of the present invention, in the semiconductor layer in which the source region, the channel forming region and the drain region are formed, the source / drain region and the channel portion of the channel forming region (the portion which actually becomes a channel) A thin film layer region corresponding to the difference between the thickness of the source / drain region and the thickness of the channel formation region is formed between them.
High breakdown voltage between drains can be realized.

The above-described structure of the present invention provides a TFT in a self-aligned manner.
Is characterized in that As a particularly troublesome step in the present invention, there is a step of selectively etching in a vertical direction by controlling a semiconductor layer in which a source region, a channel formation region, and a drain region are formed to a predetermined thickness. However, since the control of the etching rate in the vertical direction can be performed with very good controllability, it does not matter much. In this vertical etching step, a reactive ion etching method is generally used, but other anisotropic etching means may be used.

Since the exposed source / drain regions can be directly doped with impurities, the problem of damaging the device can be reduced in the step of doping the impurities imparting one conductivity type. In particular, when a doping method using laser light is used in an atmosphere containing an impurity element to be doped, an activation step by thermal annealing after doping, which may cause a defect, is not necessary, which makes the manufacturing process extremely difficult. Is advantageous. However, it is also possible to use an ion doping method which has been widely used in the past, with some care for damage. At this time, since ions are directly implanted into the semiconductor layer, the implantation energy can be weakened, and damage due to ion energy can be reduced.

According to the present invention, the above-described etching step and the doping step of an impurity imparting one conductivity type do not cause electric field concentration at the channel end formed above the source / drain region and the channel formation region in a self-aligned manner. Since the thin film layer region to be formed can be formed, it is very advantageous in a manufacturing process.

[0027]

In the structure of the present invention, the thin film layer region below the channel exists between the channel as the current path and the drain region as the carrier outlet, so that the drain region and the channel forming region are separated from each other. The electric field between them (called the drain electric field) is concentrated below the channel, and does not show the phenomenon that the previous drain electric field contributes to the channel formation. Therefore, it exhibits characteristics of low leakage current and high withstand voltage, and it is possible to obtain a characteristic improvement effect equal to or higher than that of a TFT having an offset gate structure.

At the same time, the lower portion of the channel functions as a buffer region for alleviating the electric field concentration, so that the resistance at that portion can be almost ignored, and the decrease in the on-current can be suppressed. Therefore, it is possible to prevent a decrease in the on-current while reducing the leak current.
That is, the mutual conductance can be improved.

[0029]

EXAMPLE In this example, a method for manufacturing an N-channel insulated gate field effect transistor (hereinafter referred to as NTFT) on a glass substrate using the structure of the present invention and its characteristics will be described.

In this embodiment, one NTFT (N
Although only a channel type TFT is provided, it goes without saying that a large number of NTFTs can be simultaneously manufactured by a similar manufacturing method. Alternatively, only a P-channel insulated gate field effect transistor (PTFT) may be provided.
A TFT circuit having a structure can be provided.

The manufacturing process of this embodiment will be described with reference to FIG. First, in FIG. 2A, a silicon oxide film 32 is formed as a base protective film on a glass substrate 31 to a thickness of 300 nm by sputtering in a 100% oxygen atmosphere. Of course, a light-transmitting insulating substrate other than a glass substrate may be used as the substrate. Further, a silicon nitride film may be used instead of silicon oxide as the base protective film.

The sputtering conditions are as follows: magnetron type RF sputtering is performed in an atmosphere of 100% oxygen.
RF output 500 for 6 inch synthetic quartz target
W was formed at a substrate temperature of 200 ° C. and a film forming pressure of 0.6 Pa.

Next, on the silicon oxide film 32, an amorphous silicon (a-Si: H) film 3 serving as a semiconductor layer constituting a source / drain region and a channel forming region of the NTFT is formed.
3 is formed to a thickness of 100 to 200 nm. As a film forming method, a sputtering method was used, but a plasma CVD method,
A well-known method of forming an amorphous silicon film, such as a light CVD method or a thermal CVD method, can be used.

The sputtering conditions used in this embodiment were as follows: a pressure of 0.5 Pa, a substrate temperature of 350 ° C., and a 6-inch high-purity, high-resistance silicon target (cathode) in a mixed atmosphere of argon and hydrogen as a sputtering gas. ) Was applied with a high frequency power of 13.56 MHz, and a film of hydrogenated amorphous silicon was formed by a sputtering reaction.

The sputtering apparatus used for film formation has a multi-chamber structure, and a turbo-molecular pump and a rotary pump are connected in series independently of each other in both the transfer chamber and the film formation chamber. At first, active elements in the atmosphere are exhausted to minimize mixing in the film during film formation.

After the formation of the hydrogenated amorphous silicon film 33, the film is formed at 400 ° C. to 500 ° C. in an inert gas atmosphere.
Heat treatment was performed at a temperature of ° C. for 1 to 3 hours to release hydrogen from the film. This heat treatment is for preventing a large amount of hydrogen in the film from being released in a short time during crystallization by laser light, which is a post-process, so as to prevent the film surface from having irregularities. It is better to release hydrogen as much as possible by the heat treatment. However, when heat treatment is performed at a high temperature for a long time, crystal nuclei are generated and polycrystallization proceeds due to solid phase growth, so that laser light (in general, excimer laser light having a wavelength in the ultraviolet region is used). Since the absorption coefficient is smaller than that of amorphous silicon, favorable crystal formation by laser light irradiation cannot be performed. Therefore, heat treatment at high temperature and short time and low temperature and long time are effective.

For the crystallization, solid phase growth by heat may be used, or a method of forming polycrystalline silicon directly on a substrate by thermal CVD or the like may be used. It is also possible to use hydrogenated amorphous silicon directly. Needless to say, the type of semiconductor may be selected according to the purpose.

In FIG. 2B, the amorphous silicon thin film 33 from which the hydrogen has been released is used as a positive resist and a first resist.
Is formed as a pattern (island pattern) having the same shape as the first chromium mask pattern by a photolithography process using the chrome mask.

In order to form the island pattern, amorphous silicon was etched by a balanced plate type reactive ion etching (hereinafter referred to as RIE) method which is anisotropic dry etching. The etching by the RIE method is a widely used method such as LSI manufacturing among well-known etching methods. Usually, electrodes are arranged in parallel in a vacuum vessel, gas is introduced, and one electrode is By applying high-frequency power to generate plasma between the electrodes, plasma ions are vertically incident on a substrate provided on the electrodes and anisotropic etching is performed in the vertical direction. In this step, wet etching using an etching solution containing hydrofluoric acid and nitric acid as main components can be used.

The etching by the RIE method in this embodiment was performed as follows. First, place the substrate on the electrode,
After a high vacuum was applied with a diffusion pump, carbon tetrafluoride (CF ₄ ) as an etching gas was introduced to maintain the pressure at 10 Pa.
Etching was performed by applying a high frequency power of 13.56 MHz to the electrodes at an output of 100 W. Although carbon tetrafluoride is used in this embodiment, etching can be similarly performed using sulfur hexafluoride, nitrogen trifluoride, or a mixed gas thereof.

After the island of the semiconductor layer was formed by etching, the resist component was removed with a stripping solution, and the natural oxide film was further removed with 1% (volume ratio) hydrofluoric acid.

Next, a silicon oxide film 34 serving as a gate insulating film was formed to a thickness of 100 to 150 nm by sputtering. The film forming process is as follows. The substrate was placed in a chamber of a sputtering apparatus, a high vacuum was generated by a turbo molecular pump, only oxygen was introduced as a sputtering gas into the chamber, and a pressure of 0.6 Pa and a substrate temperature of 200 ° C. were applied to a 6-inch synthetic quartz target at 13.56 MHz high frequency. 5 power
00W is applied, and the silicon oxide film 3 is formed by a sputtering reaction.
4 was formed. In this embodiment, the silicon oxide film is formed by sputtering.
In addition to a silicon oxide film, a silicon nitride film can be used instead of a silicon oxide film, a photo-CVD method, a liquid layer deposition method, a thermal oxidation method, and the like.

In FIG. 2C, an amorphous silicon film serving as a gate electrode 35 is formed on the silicon oxide film 34 serving as the gate oxide film by sputtering to a thickness of 100 to 150 nm. The manufacturing process is the same as the amorphous silicon film 3 described above.
The same conditions as in No. 3. Since this amorphous silicon layer has a high resistance, it is necessary to reduce the resistance by laser doping described later in order to use it as a gate electrode. However, the resistance may be reduced by laser light or heat treatment after ion doping.

In addition, a film formed by sputtering using silicon doped with impurities as a target does not require a doping step, and the resistance can be reduced by performing only an activation step by laser or heat treatment. Naturally, an impurity-doped amorphous silicon film can be formed by a known film forming method such as plasma CVD or thermal CVD, and the resistance can be reduced by the above-described process, so that the film can be used as a gate electrode. Further, a thin metal film of aluminum, chromium, molybdenum, tantalum, or the like can be formed by sputtering or vapor deposition and used as a gate electrode.

A gate region is formed on the amorphous silicon film serving as the gate electrode 35 by photolithography and etching using a second mask (for forming a gate). Here, the basic structure of the channel, the source, and the drain is completed in a self-aligned manner. The etching step using the photolithography and the RIE method used the same conditions as the formation of the semiconductor island to be the channel formation region.

Next, the shape shown in FIG. 2D is obtained by using an etching process by the RIE method. In this step, which is a feature of the present invention, the etching is not completed only with the amorphous silicon layer serving as the gate electrode 35.
The silicon oxide film serving as the gate insulating film 34 and the upper portion of the semiconductor layer 33 in the source and drain regions are continuously etched. In this step, the basic structure of the present invention is completed.

In order to obtain the shape shown in FIG. 3D, it is necessary to partially etch the upper portion of the crystallized silicon semiconductor layer 33, but this requires experimentally obtaining conditions according to the process. This can be easily realized.

In this step, the silicon oxide film 34
Since only the etching is not performed selectively, it is not necessary to end the etching accurately at the interface between the crystalline silicon film 33 and the silicon oxide film 34, and the state shown in FIG. 2 (E) is useful in the manufacturing process. further,
Since the silicon oxide film on the source / drain regions is completely removed, it is not necessary to perform high-energy ion doping through the conventional silicon oxide film, so that ion energy is less damaged and the yield is improved. Can be fulfilled. In particular, in the case of the present embodiment, the exposed source / drain regions can be directly doped with an impurity imparting a conductivity type by a laser doping method. A thermal annealing step is not required, and the yield can be increased.

Further, in this step, since isotropic etching such as wet etching is not used in this etching step, there is no over-etching of the gate oxide film, the leak current increases in the gate direction, and the gate length decreases due to the decrease in channel length. It is possible to suppress a decrease in the dielectric strength of the oxide film and an adverse effect on the circuit design due to a change in TFT characteristics.
A TFT with high characteristics and high yield can be obtained.

By the above etching step, FIG.
Then, laser doping with an excimer laser was performed to reduce the resistance of the source region 36, the drain region 37, and the gate electrode 35.

The laser doping process will be described below.
In this step, a device was used which was provided with a substrate holder which could be heated by a sheath heater in a vacuum chamber provided with a turbo molecular pump, and which could irradiate laser light from a quartz window. Specifically, first, a sample is placed on a substrate holder, and after a high vacuum is generated by a turbo molecular pump, the substrate temperature is maintained at 400 to 500 ° C., and a mixed gas of phosphine and hydrogen is used as a doping gas for forming an N channel. It is introduced into the chamber and the pressure is kept at 100 Pa. In this state, the substrate is irradiated with excimer laser light through a quartz window at the top of the chamber to decompose the phosphine molecules adsorbed on the substrate, and diffuse the film into a low-resistance layer. Here, the gate electrode layer is polycrystalline at the same time as the impurity is doped, so that a gate electrode of low-resistance polycrystalline silicon is formed.

In the doping by the laser, since the laser light itself does not diffuse, the doping action has a very strong anisotropy. Therefore, as long as the laser beam is irradiated perpendicularly to the substrate, the exposed side surface 40 of the channel forming region between the source / drain region and the channel region.
Is not doped with impurities.

In this embodiment, phosphine was used as a dopant gas to form an NTFT.
If boron fluoride is used, a PTFT can be manufactured. Further, an ion doping method can be used as a doping method.

In FIG. 2E, after completion of the doping step, a silicon oxide film 39 is formed as an interlayer insulating film to a thickness of 400 to 600 nm.
Film formation was performed by sputtering. The fabrication conditions are the same as the fabrication conditions for the gate oxide film 34. In this step, a silicon oxide film formed by sputtering was used.
D, thermal CVD, optical CVD, liquid layer deposition, or other well-known film forming methods may be used, and a silicon nitride film may be used instead of the silicon oxide film.

Next, contact holes were formed by photolithography and etching. At this time, the etching is H
Wet etching was performed using buffered hydrofluoric acid with F: NH ₄ F = 1: 10 (volume ratio).

After forming the contact hole, the extraction electrode 4
The aluminum which becomes 1, 42 is 500 ~ with the electron beam evaporation machine.
A 1000 nm film was formed. Next, an electrode pattern is formed by a photolithography process, wet etching is performed with a commercially available aluminum etchant solution, and the resist is removed to form an NTFT.
Was completed.

Although aluminum is used for the extraction electrodes 41 and 42 in this step, a metal such as chromium, molybdenum, and tantalum and silicide which is an alloy with silicon can be used. Further, a film may be formed by sputtering and plating.

After the TFT is completed, the TFT is placed in a hydrogen atmosphere at atmospheric pressure.
The FT substrate was charged, the temperature was raised to 350 ° C., and hydrogen heat treatment was performed for 30 minutes to terminate the channel interface and defects in the active layer with hydrogen atoms, thereby stabilizing the TFT characteristics.

FIG. 3 shows a TFT (Thin drain) having a structure in which the source and drain regions manufactured according to the present embodiment are thinned.
7 shows a comparison of drain current-gate voltage characteristics between a TFT (Normal type) and a TFT (Normal type) having no such structure. The thickness of the channel forming region of the TFT of this embodiment is 150 nm, and the thickness of the source / drain region is 50 nm. The normal type TFT of the comparative example has a channel forming region and a source / drain region both having a thickness of 150 nm.

As can be seen from FIG. 4, T
FT has a small off-state current. On the other hand, it can be seen that the off-state current of the normal type TFT having the conventional structure is about two orders of magnitude larger than that of the TFT of this embodiment. On the other hand, with respect to the ON current, no difference was observed between the TFT of the present embodiment and the conventional TFT. Therefore, a decrease in the mutual conductance due to the structure of the present embodiment was not observed. It is concluded that the transconductance increases due to the decrease. The field-effect mobility of the TFT of this embodiment was almost the same as that of the conventional TFT.

Further, the source of the TFT of this embodiment is
As for the drain-to-drain breakdown voltage, an improvement in the breakdown voltage characteristic with respect to the drain electric field of about 30% was observed as compared with the conventional TFT.

In this embodiment, an amorphous silicon semiconductor crystallized by a laser beam is used. However, in the present invention, the type of semiconductor is not limited, and the crystal state may be changed as required. Others can be used.

[0063]

As described above, according to the present invention, T
By forming the source and drain regions of the FT thinner than the thickness of the channel forming region, the electric field at the interface between the source / drain region and the channel portion is utilized by utilizing the reduced thickness. The concentration phenomenon can be reduced, and a thin film transistor having low leakage, high mutual conductance, and high withstand voltage can be obtained.

[Brief description of the drawings]

FIG. 1 shows a manufacturing process of a conventional gate offset type TFT.

FIG. 2 shows a manufacturing process of a TFT according to an embodiment of the present invention.

FIG. 3 shows a comparison of characteristics between a TFT manufactured in an example of the present invention and a conventional TFT.

[Explanation of symbols]

Reference Signs List 11 glass substrate 12 base silicon oxide film 13 semiconductor layer serving as source / drain region and channel formation region 14 silicon oxide film serving as gate insulating film 15 semiconductor layer serving as gate electrode 16 silicon oxide film serving as interlayer insulating film 17 source region 18 Channel formation region 19 Drain region 20 Offset gate region 21 Aluminum layer as extraction electrode 23 Aluminum layer as extraction electrode 31 Glass substrate 32 Silicon oxide film as base oxide film 33 Semiconductor layer as source / drain region and channel formation region 34 Silicon oxide film serving as a gate insulating film 35 Semiconductor layer serving as a gate electrode 43 Resist serving as a mask 40 Side surface of a channel forming region exposed 36 Source region 38 Channel forming region 37 Drain region 41 Aluminum layer serving as a lead electrode 42 Aluminum serving as a lead electrode A silicon oxide film serving as a layer 39 interlayer insulating film

Claims (4)

(57) [Claims] A semiconductor layer having a source region, a drain region, and a channel forming region provided on a projection between the source region and the drain region on an insulating surface;
A gate electrode provided adjacent to the channel formation region with a gate insulating layer interposed therebetween; and a layer serving as the gate electrode and an insulating layer serving as the gate insulating film.
An edge layer and a semiconductor serving as the source and drain regions.
The surface portion of the body layer is formed by continuous etching, and the interface between the drain region and the channel formation region and
And the interface between the source region and the channel forming region.
The thin film transistor according to claim 1, wherein a side surface of the convex portion forming a plane has a side surface perpendicular to the insulating surface. 2. The thin film transistor according to claim 1, wherein the insulating surface is a light-transmitting insulating surface. 3. The thin film transistor according to claim 1 , wherein a side surface of the projection is perpendicular to the insulating surface. 4. A have your <br/> to any one of claims 1 to 3, wherein the gate electrode, silicon, aluminum, chromium,
A thin film transistor containing any of molybdenum and tantalum.