JP2002162945A - Electrooptical panel, its driving circuit, data line driving circuit, scanning line driving circuit and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driving circuit or the like which prevents active intervals of output signals from being overlapped by using a simple constitution. SOLUTION: A data line driving circuit 150A is provided with an X shift register 151 and an arithmetic section 152 having computing unit circuits Ub1 to Ubn. The circuits Ub1 to Ubn are provided with NAND circuits 504-1 to 504-n and NOR circuits 505-01 to 505-n. Falling edges of sampling signals SR1 and rising edges of sampling signals SR2 are determined by the rising edges of shift pulses C2. Thus, sampling signals SR1 to SRn are made active in an exclusive OR manner.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is to drive an electro-optical panel having a plurality of scanning lines and a plurality of data lines, and pixel electrodes and switching elements arranged in a matrix corresponding to their intersections. And a data line driving circuit and a scanning line driving circuit using the driving circuit, an electro-optical panel, and an electronic device.

[0002]

2. Description of the Related Art In a conventional electro-optical device, for example, a liquid crystal device, a plurality of data lines and a plurality of scanning lines are formed in an image display area, and pixel electrodes arranged in a matrix corresponding to their intersections. Each with a thin film transistor (Thin Fil
m Transistor: hereinafter referred to as TFT). The driving circuit of the liquid crystal device includes a data line driving circuit for supplying a data line signal, a scanning line signal, and the like to the data line and the scanning line at a predetermined timing, a scanning line driving circuit, and the like.

[0003] These drive circuits generate a selection signal by the following method, and generate a data line signal and a scanning line signal based on the selection signal. First, the driving circuit sequentially transfers the start pulse according to the clock signal and the inverted clock signal obtained by inverting the clock signal to generate a plurality of shift pulses whose phases are shifted by a half cycle of the clock signal. Each selection signal is generated by calculating the logical product of the shift pulse and the next shift pulse.

If the drive circuit operates ideally, each select signal is exclusively active. However, in an actual drive circuit, adjacent select signals are caused by the time delay of the logic circuit and the characteristics of the active elements. Active periods may overlap.

Therefore, a technique for eliminating the overlap of the active periods using an inhibit signal is known. FIG.
FIG. 13 is a block diagram showing a configuration of a conventional data line driving circuit and its peripheral circuits, and FIG. 13 is a timing chart thereof.

[0006] As shown in the figure, the data line driving circuit includes shift units U0, U1, U2, ..., Un. , Un sequentially transfer the start pulse DX based on the X clock signal XCK and the inverted X clock signal XCKB, and output the shift pulses C0, C1, C2,. AND circuit G1,
G2,..., Gn are corresponding shift units U1, U
, Un, and the logical product of the input and output signals of Un are calculated, and the signals Sa1, Sa2,.

On the other hand, the inhibit signal INHB is an L level (active) signal for a predetermined period centered on the timing at which the logic levels of the X clock signal XCK and the inverted X clock signal XCKB transition as shown in the figure.

Here, AND circuits G1, G2,... Calculate the logical product of the inhibit signal INHB and the signals Sa1, Sa2,. Therefore, the selection signals SR1, SR2,.
Is at the L level during the period when the inhibit signal INHB is at the L level as shown in the figure. This makes it possible to provide an inactive period between adjacent selection signals.

The selection signal SR generated as described above
Are supplied to the control input terminals of the switches SW constituting the sampling circuit. In this example, each switch SW is configured by an N-channel transistor. Therefore, when the gate voltage becomes H level, the image signal VID is sampled and supplied to each data line as a data line signal. Since each data line has a wiring capacitance, the voltage of the image signal VID is written to the wiring capacitance in the sampling process.

[0010]

The inhibit signal INHB is supplied to the AND circuit G via the signal supply line LX.
, G2,..., The input capacitance of those circuits accompanies the signal supply line LX. For this reason, it is necessary to use a circuit capable of supplying a large current at a high response speed as the inhibit signal drive circuit, which causes a problem that the circuit configuration becomes large-scale and a large current consumption is required.

When the pulse width of the inhibit signal INHB is wide, the writing time for writing the image signal VID to the data line is shortened.
Cannot be written sufficiently. Therefore, it is desirable to narrow the pulse width of the inhibit signal INHB. In particular, in order to display a high-definition image, it is necessary to increase the number of data lines.
Since the active period of 1, Sa2,... Becomes shorter,
It is necessary to further narrow the pulse width. on the other hand,
Reducing the pulse width of the inhibit signal INHB means an increase in high frequency components. However, the drive capability of the inhibit signal drive circuit has a certain limit,
There is a problem that it is difficult to narrow the pulse width.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a drive circuit or the like which has a simple configuration and prevents active periods of output signals from overlapping.

[0013]

In order to achieve the above object, a driving circuit according to the present invention provides a plurality of scanning lines, a plurality of data lines, and an intersection between the scanning lines and the data lines. Used for an electro-optical panel having pixel electrodes and switching elements arranged in a matrix, comprising a shift register section and a logical operation section, wherein the shift register section starts pulses based on a clock signal. A plurality of shift unit circuits for sequentially shifting and sequentially outputting output signals, wherein the logical operation unit includes a plurality of operation unit circuits provided corresponding to each shift unit circuit, The unit circuit generates a first signal specifying a first period during which both the input signal and the output signal of the corresponding shift unit circuit are active, and the first signal and the shift unit circuit Generating and outputting an output signal that is active in a third period excluding the active period of the second signal from the active period of the first signal, based on the second signal output from the shift unit circuit of the next stage. It is characterized by.

According to the present invention, even if the active periods of the first signals generated by the adjacent operation unit circuits overlap, the active periods are corrected by the second signal so as to be shortened. Therefore, each output signal can be exclusively activated.

Here, the operation unit circuit calculates a NAND of an input signal and an output signal of a corresponding shift unit circuit and outputs the result as the first signal, a NAND circuit, and the first signal and the second signal. A NOR circuit for calculating an inverted logical sum of the two signals and outputting the result as the output signal. The present invention corresponds to the case where the start pulse is given by positive logic (active H).

On the other hand, when the start panel is provided with negative logic (active L), the operation unit circuit calculates the inverted logical sum of the input signal and the output signal of the corresponding shift unit circuit to perform the first operation. A NOR circuit that outputs a signal,
It is preferable that a NAND circuit that calculates an inverted OR of the first signal and the second signal and outputs the result as the output signal is provided.

Next, a data line driving circuit according to the present invention includes the above-described driving circuit, and samples an input image signal based on each output signal output from the driving circuit and supplies the sampled image signal to each data line. It is characterized by the following. As described above, the output signals of the drive circuit are exclusively active and are not active at the same time. Therefore, when this data line drive circuit is used, it is not necessary to simultaneously select adjacent data lines. When adjacent data lines are selected at the same time, the input image signal to be supplied to one data line is also supplied to the other data line, so that crosstalk in the data line direction occurs, and the quality of the displayed image is reduced. Will deteriorate. However, in this data line driving circuit, since a plurality of data lines are not selected at the same time, the occurrence of crosstalk can be prevented and a high-quality image can be displayed.

Next, a scanning line drive circuit according to the present invention includes the above-described drive circuit, and drives each of the scan lines based on each selection signal output from the drive circuit. . When adjacent scanning lines are selected at the same time, input image signals are simultaneously written to pixels corresponding to these scanning lines, so that crosstalk occurs in the scanning line direction and the quality of a displayed image is degraded. However, in this scanning line driving circuit, since a plurality of scanning lines are not selected at the same time, generation of crosstalk can be prevented and a high-quality image can be displayed.

Next, in the electro-optical panel according to the present invention, a plurality of scanning lines, a plurality of data lines, and a matrix are arranged corresponding to intersections of the scanning lines and the data lines. A pixel region having a pixel electrode and a switching element, the above-described data line driving circuit, and a scanning line driving circuit for driving the scanning line are provided. Since the electro-optical panel does not select a plurality of data lines at the same time, high-quality images can be displayed by preventing the occurrence of crosstalk.

Further, in the electro-optical panel according to the present invention, a plurality of scanning lines, a plurality of data lines, and pixels arranged in a matrix corresponding to intersections of the scanning lines and the data lines. A pixel region having an electrode and a switching element, a data line driving circuit for driving the data line, and the above-described scanning line driving circuit are provided. Since the electro-optical panel does not select a plurality of scanning lines at the same time, high-quality images can be displayed while preventing the occurrence of crosstalk.

Next, an electronic apparatus according to the present invention includes the above-described electro-optical panel. For example, a viewfinder, a mobile phone, a notebook computer, a video projector, and the like used for a video camera are provided. Applicable.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. <1. Liquid Crystal Device><1-1: Overall Configuration of Liquid Crystal Device> First, a liquid crystal device will be described as an example of an electro-optical device. FIG. 1 is a block diagram illustrating an electrical configuration of the liquid crystal device. As shown in this figure, the liquid crystal device has a liquid crystal display panel 100.
, A timing generator 200, and an image signal processing circuit 300. Among them, the timing generator 200 outputs a timing signal (described later as necessary) used in each unit. Also, a phase expansion circuit 302 inside the image signal processing circuit 300
Receives one system of image signal VID, expands it into an N-phase (N = 6 in the figure) image signal, and outputs it in parallel. The image signal is converted into N parallel image signals. To a serial-parallel conversion circuit. Here, the image signal is N
The reason for developing the phase is to increase the application time of the image signal to the source electrode of the TFT functioning as a switching element by the sampling circuit described later, and to sufficiently secure the writing time for the wiring capacitance of the data line. .

On the other hand, the amplifying / inverting circuit 304 inverts the phase-deployed image signal that needs to be inverted, and thereafter amplifies it appropriately to produce image signals VID1 to VID.
The reference numeral 6 designates a liquid crystal display panel 100 which is supplied in parallel. In addition, regarding whether or not to invert, generally,
Determined according to whether the data signal application method is scan line polarity inversion, data signal line unit polarity inversion, pixel unit polarity inversion, or screen unit polarity inversion, The inversion cycle is set to one horizontal scanning period or one vertical scanning period.

The image signals VID1 to VID
The supply timing of ID6 to the liquid crystal display panel 100 is as follows.
In the liquid crystal device shown in FIG. 1, the timings are simultaneous, but they may be shifted sequentially in synchronization with a dot clock. In this case, an N-phase image signal may be sequentially sampled by a sampling circuit described later.

<1-2: Structure of Liquid Crystal Display Panel>
The schematic configuration of the liquid crystal display panel 100 will be described with reference to FIGS. Here, FIG. 2 is a perspective view for explaining the structure of the liquid crystal display panel 100, and FIG.
FIG. 2 is a partial cross-sectional view for explaining the structure of the liquid crystal display panel 100. As shown in these figures, the liquid crystal display panel 100 includes an element substrate 101 such as glass or semiconductor on which a pixel electrode 118 or the like is formed, and a transparent counter substrate 102 such as glass on which a common electrode 108 or the like is formed. Are bonded to each other so that the electrode forming surfaces face each other with a certain gap maintained by the sealing material 105 mixed with the spacer S, and the liquid crystal 106 is sealed in the gap.

A scanning line driving circuit 13 to be described later is provided on the surface facing the element substrate 101 and outside the sealing material 105.
0, sampling circuit 140, and data line driving circuit 1
A drive circuit group 120 of 50 A or the like is formed. Also,
External connection electrodes (not shown) are formed therein, and the timing generator 200 and the image signal processing circuit 3
Various signals from 00 are input. Note that the common electrode 108 of the counter substrate 102 is
The conductive material provided in at least one of the four corners of the bonding portion with the first conductive member 1 electrically connects the wiring extending from the external connection electrode of the element substrate 101.

In addition, the opposing substrate 102 is provided with, for example, color filters arranged in stripes, mosaics, triangles, etc., depending on the use of the liquid crystal display panel 100, and secondly, For example, a black matrix such as a resin black in which a metal material such as chromium or nickel or carbon or titanium is dispersed in a photoresist is provided. Third, a backlight for irradiating the liquid crystal display panel 100 with light is provided. . In particular, in the case of color light modulation, a black matrix is provided on the counter substrate 102 without forming a color filter. In addition, the opposing surfaces of the element substrate 101 and the opposing substrate 102 are each provided with an alignment film or the like that has been rubbed in a predetermined direction. 103 and 104 are provided, respectively. However, when a polymer-dispersed liquid crystal in which fine particles are dispersed in a polymer is used as the liquid crystal 108, the above-described alignment film, polarizing plate, and the like become unnecessary, and the light use efficiency is increased. This is advantageous in terms of low power consumption and the like.

Returning to FIG. 1, the electrical configuration of the liquid crystal display panel 100 will be described. On the element substrate 101 of the liquid crystal display panel 100, an image display area AA is formed. In this figure, a plurality (m) of scanning lines 112 are arranged in parallel along the X direction in the figure, and a plurality (6n) of scanning lines 112 are formed in parallel along the Y direction orthogonal to this. A data line 114 is formed. At each intersection of the scanning line 112 and the data line 114, the gate electrode of the TFT 116 is connected to the scanning line 112, while the source electrode of the TFT 116 is connected to the data line 114 and the TFT 116
Are connected to the pixel electrode 118. Each pixel is composed of a pixel electrode 118, a common electrode 108 formed on the counter substrate 102, and the liquid crystal 106 sandwiched between these electrodes.
They are arranged in a matrix corresponding to each intersection between the data line 114 and the data line 114. In addition, a storage capacitor (not shown) is provided for each pixel, and is electrically parallel to the liquid crystal layer sandwiched between the pixel electrode 118 and the common electrode 108.

Next, the driving circuit group 120 includes the scanning line driving circuit 130, the sampling circuit 140, and the data line driving circuit 150A.
It is formed on top. These circuits use the T
The TFT is formed using a manufacturing process common to the FT (for example, a high-temperature polysilicon process). This is advantageous in terms of integration and manufacturing cost.
Note that, in this example, the data line driving circuit 150A and the sampling circuit 140 are described separately, but it is a matter of course that both may be regarded as a data line driving circuit that drives the data line 114 integrally.

Now, the scanning line driving circuit 130 has a shift register,
The clock signal YCK and its inverted Y clock signal YCK
The scanning line signal Y based on the B, Y transfer start pulse DY, etc.
, Ym (selection signal) are sequentially output to each scanning line 112, and the scanning line signals Y1, Y2,..., At the timing of shifting the pulse DY according to the clock signal in the shift register. Ym is output.

On the other hand, the sampling circuit 140 groups the six data lines 114, and samples the image signals VID1 to VID6 with respect to the data lines 114 belonging to these groups according to the sampling signals SR1 to SRn. It is supplied. Sampling circuit 14
0, a switch 141 composed of a TFT is connected to each data line 1.
14, and a source electrode of each switch 141 is connected to a signal line to which one of the image signals VID1 to VID6 is supplied.
One drain electrode is connected to one data line 114. Further, the gate electrode of each switch 141 connected to the data line 114 belonging to each group is connected to one of signal lines to which the sampling signals SR1 to SRn are supplied corresponding to the group. As described above, the image signal V
Since ID1 to VID6 are supplied at the same time, they are simultaneously sampled by the sampling signal S1.

The data line driving circuit 150A is connected to the X clock signal XCK from the timing generator 200.
And sampling signals SR1 to SRn based on the inverted X clock signal XCKB, the X transfer start pulse DX, and the like.
(Selection signals) are sequentially output.

<1-3: Data Line Driving Circuit> Next, the data line driving circuit 150A will be described. FIG. 4 is a block diagram showing the overall configuration of the data line drive circuit. As shown in FIG. 4, the data line driving circuit 150A includes an X shift register 151 and a logical operation unit 152.

First, the X shift register 151 is configured by cascade-connecting the shift register unit circuits Ua0 to Uan. Each of the shift register unit circuits Ua0 to Uan includes clocked inverters 501-0 to 501-n and 502-0 to 50-n.
2-n and inverters 503-0 to 503-n.

Clocked inverters 501-1 to 501-n
And 502-1 to 502-n invert each of the input signals when the control terminal voltage is at the H level and output them, and when the control terminal voltage is at the L level, put the output terminal in a high impedance state. Each control terminal is supplied with an X clock signal XCK and an inverted X clock signal XCKB which are active only for a predetermined period.

For example, in the shift register unit circuit Ua0, when the X clock signal XCK is at the H level, the clocked inverter 501-0 inverts the input signal and outputs the inverted signal.
At this time, since the inverted X clock signal XCKB is at the L level, the output terminal of the clocked inverter 502 is in a high impedance state. Therefore, in this case, the input signal is output via clocked inverter 501-0 and inverter 503-0. On the other hand, inversion X
When clock signal XCKB is at H level, clocked inverter 502-0 inverts the input signal and outputs the inverted signal. At this time, since the X clock signal XCK is at the L level, the output terminal of the clocked inverter 501-0 is in a high impedance state. In this case, a clocked inverter 502-0 and an inverter 503-0 constitute a latch circuit.

As a result, each shift register unit circuit U
a0 to Uan sequentially shift the X transfer start pulse DX in synchronization with the X clock signal XCK and the inverted X clock signal XCKB to generate shift pulses C0 to Cn. By this shift operation, the active period (H level) of a certain shift pulse Cj and the next shift pulse Cj + 1 is X.
The clock signal XCK overlaps by 周期 cycle.

Next, the logical operation unit 152 includes operation unit circuits Ub1 to Ubn. Each operation unit circuit Ub1 to Ubn
Are provided corresponding to the shift register unit circuits Ua1 to Uan, respectively. Further, each operation unit circuit Ub1 to Ubn is
NAND circuits 504-1 to 504-n and NOR circuit 505-1
To 505-n-1. However, the operation unit circuit U
Ubn is provided with an inverter 505-n instead of the NOR circuit.

The NAND circuits 504-1 to 504-n invert the logical product of the input signals and the output signals of the corresponding shift register unit circuits Ua1 to Uan and output the inverted signals as signals S1 to Sn. For example, since the operation unit circuit Ub1 corresponds to the shift register unit circuit Ua1, the NAND circuit 504-1 of the operation unit circuit Ub1 inverts the logical product of the shift pulses C1 and C2 to generate the signal S1. Here, since the shift pulses CO to Cn are active at the H level as shown in FIG. 5, the NAND circuits 504-1 to 504-n output the input signals and the output signals of the corresponding shift register unit circuits Ua1 to Uan. There is a function to specify a period during which both are active.

Next, the NOR circuits 505-1 to 505-n-1 supply the output signals of the NAND circuits 504-1 to 504-n and the output signals of the shift register unit circuit at the next stage of the corresponding shift register unit circuit. And are supplied. Noah circuit 505-1
505-n-1 calculate the inversion of these logical sums and output them as sampling signals SR1 to SRn. For example,
The NAND circuit 504-1 of the operation unit circuit Ub1 inverts the logical sum of the signal S1 and the shift pulse C2 to generate the sampling signal SR1. Here, the signals S1 to Sn are active at the L level as shown in FIG. 5, while the shift pulses CO to Cn are active at the H level. NOR circuits 505-1 to 505-n-1 are connected to NAND circuits 505-1 to 50-50.
There is a function of generating a signal that becomes active in a period excluding a period in which the output signal of the next-stage shift register unit circuit is active from a period in which the 5-n-1 output signal is active.

<1-4: Operation of Data Line Driving Circuit> Next, the operation of the data line driving circuit 150A will be described with reference to FIG. FIG. 5 shows a data line driving circuit 150A.
6 is a timing chart showing the operation of FIG.

First, at time T1, when the X clock signal XCK goes high, the clocked inverter 501-0 of the 0th shift register unit circuit Ua0 becomes active. At this time, the X transfer start pulse DX is output as the shift pulse CO via the clocked inverter 501-0 and the inverter 503-0. Therefore, from time T1, shift pulse CO goes high.

Next, at time T2, when the inverted X clock signal XCK goes to H level, the clocked inverter 501 in the first shift register unit circuit Ua1.
-1 becomes active. At this time, the clocked inverter 501-0 at the preceding stage becomes inactive, but the clocked inverter 502-0 becomes active and the inverter 5-0
Together with 03-0, a latch circuit is formed. Therefore, even at time T2, shift pulse C0 maintains the H level, while shift pulse C1 transitions from the L level to the H level.

At time T3, the clocked inverter 501-0 of the shift register unit circuit Ua0 becomes active again, so that the X transfer start pulse DX is transmitted via the clocked inverter 501-0 and the inverter 503-0. It is output as a shift pulse CO. Therefore, shift pulse CO changes from H level to L level from time T3. In the shift register unit circuit Ua1, the clocked inverter 501-1 becomes inactive while the clocked inverter 502-1 becomes active, and the shift pulse C1 is maintained at the H level.

Thereafter, by repeating this shift operation sequentially, each shift register unit circuit Ua0 to Uan
The transfer start pulse DX is sequentially transferred according to the X clock signal XCK and the inverted X clock signal XCKB.

Next, the NAND circuits 504-1 to 504-n are
Signals S1 to Sn are generated by inverting the logical product of the input signals and output signals of the corresponding shift unit circuits Ua1 to Uan. By the way, the NAND circuits 504-1 to 504-n are Pc
Although it is composed of an h-type TFT and an Nch-type TFT,
Since the ON current and the threshold voltage of the TFT vary, the slew rate differs and the delay time differs between the rising edge and the falling edge. Due to this, the actual pulse width of the signals S1 to Sn is wider than the ideal pulse width.

Specifically, as shown in the figure, the active periods of the signals S1 and S2 overlap by a time ΔT. The active periods of other adjacent signals also overlap. Note that td shown in the figure is the NAND circuits 504-1 to 504-n and the NOR circuits 505-0 to 505-n
-1 is each propagation delay time.

The rising edges Esu1, Esu2,... Of the signals S1, S2,.
Are determined by the falling edges Ecd0, Ecd1,..., While the falling edges Esd1, Esd of the signals S1, S2,.
Are determined by the rising edges Ecu1, Ecu2,... Of the shift pulses C1, C2,.

For example, the rising edge Esu1 of the signal S1 is determined by the shift pulse C0, while the falling edge Esd2 of the signal S2 is determined by the rising edge Ecu2 of the shift pulse C2. That is, the signal Sj which is temporally adjacent
Falling edge Esdj of signal Sj + 1 and rising edge Ecuj + of signal Sj + 1
2 are generated due to different signals.

The NOR circuits 505-1 to 505-n-1 output the signal S
Output signals of the shift unit circuits at the next stage of the shift unit circuits corresponding to 1 to Sn-1 are set as input signals. For example, the NOR circuit 505-1 uses the signal S1 and the shift pulse C2 as input signals. Here, the falling edge Erd1 of the sampling signal SR1, which is the output signal of the NOR circuit 505-1, is determined by the rising edge Ecu2 of the shift pulse C2. On the other hand, the rising edge Eru2 of the sampling signal SR2 is determined by the falling edge Esd2 of the signal S2. As described above, the falling edge Esd2 of the signal S2 is the shift pulse C
2 is determined by the rising edge Ecu2 of the sampling signal SR2.
2 rising edge Ecu2.

That is, the NOR circuits 505-1 to 505-n-1
Accordingly, the falling edge Erdj of the sampling signal SRj and the rising edge Erj + 1 of the sampling signal SRj + 1 that are temporally adjacent can be determined based on the rising edge Ecuj + 1 of the same shift pulse Cj + 1. . In addition, the falling edge Erdj of the sampling signal SRj is obtained by passing the rising edge Ecuj + 1 through the NOR circuit 505-j, whereas the rising edge Erjj + 1 of the sampling signal SRj + 1 is obtained by the rising edge Ecuj + 1. Is obtained by passing through the NAND circuit 504-j and the NOR circuit 505-j. Therefore, the rising edge Erj + 1 of the sampling signal SRj + 1 is always delayed with respect to the falling edge Erdj of the sampling signal SRj.

Therefore, the falling edge of a certain sampling signal can always be generated before the rising edge of the next sampling signal. Thus, each of the sampling signals SR1 to SRn can be exclusively activated.

<1-5: Scan Line Drive Circuit> Next, the scan line drive circuit 130 will be described. FIG. 6 is a block diagram illustrating a configuration of the scanning line driving circuit 130. As shown in this figure, the basic configuration of the scanning line driving circuit 130 is similar to that of the data line driving circuit 150A.
Includes a Y shift register 131 and a logical operation unit 132.

The Y shift register 131 has a Y clock signal YCK and an inverted Y clock signal YCK instead of the X clock signal XCK and the inverted X clock signal XCKB.
This is the same as the X shift register 150A described above, except that B is supplied and m + 1 shift register unit circuits Ua0 to Uam are provided. The logical operation unit 13
2 includes m operation unit circuits Ub1 to Ubm each including a NAND circuit and a NOR circuit.

Therefore, the scanning line driving circuit 130 outputs the scanning line signal Y similarly to the X shift register 150A described above.
1 to Y2 can be exclusively activated.

<1-6: Overall Operation of Liquid Crystal Display Panel> Next, the operation of the above liquid crystal display panel will be described.
First, in the scanning line driving circuit 130, a Y transfer start pulse DY is supplied at the beginning of a vertical scanning period. This Y transfer start pulse DY is supplied to the scanning line driving circuit 130 by the Y
Clock signal YCK and its inverted Y clock signal YC
The data is sequentially shifted by KB and output to each scanning line 112. Active periods of the scanning line signals Y1 to Ym do not overlap. As a result, the plurality of scanning lines 112 are exclusively selected one by one.

On the other hand, when the X transfer start pulse DX is supplied to the data line drive circuit 150A, the X transfer start pulse DX is applied to the data line drive circuit 150A as described above.
At A, the signals are sequentially shifted every half cycle of the X clock signal XCK and its inverted X clock signal XCKB and output as sampling signals SR1 to SRn. At the boundary timing when the active period shifts from one sampling signal Sj to the next sampling signal Sj + 1,
Since the falling edge Erjj of the sampling signal Sj and the rising edge Eruj + 1 of the sampling signal SRj + 1 are determined based on the rising edge Ecuj + 1 of the same shift pulse Cj + 1, each sampling signal SR1 to SRn is exclusive. Become active.

Here, when the sampling signal SR1 is output, the image signals VID1 to VID6 are sampled on the six data lines 114 belonging to this group, respectively, and these image signals VID1 to VID6 are selected at the present time. The six pixels that intersect with the scanning line
16 respectively. Thereafter, when the sampling signal SR2 is output, this time,
The image signal VID1 is applied to the next six data lines 114, respectively.
To VID6 are sampled, and these image signals VI
D1 to VID6 are written into the six pixels intersecting the scanning line selected at that time by the TFT 116, respectively.

Similarly, the sampling signal SR
, SRn are sequentially output, the image signals VID1 to VID6 are output to the six data lines 114 corresponding to the respective sampling signals, and these image signals VID1 to VID6 are selected at that time. Then, the data is written to each of the six pixels intersecting the scanning line. Thereafter, the next scanning line is selected, sampling signals SR1 to SRn are sequentially output again, and the same writing is repeatedly performed.

As described above, each sampling signal SR1
Since the active periods of .about.SRn do not overlap, the quality of the displayed image can be greatly improved by preventing crosstalk. In addition, in such a driving system,
The number of stages of the data line drive circuit 150A for controlling the drive of the switch 141 in the sampling circuit 140 is reduced to 1/6 as compared with the method of driving each data line 114 in a dot-sequential manner. Furthermore, the frequency of the Y clock signal YCK and its inverted Y clock signal YCKB to be supplied to the data line driving circuit 150A can be reduced to 1/6 compared with the method of driving each data line 114 in a dot-sequential manner. In addition, lower power consumption can be achieved.

<2. Application Example><2-1: Another Configuration Example of Data Line Driving Circuit> In the above-described embodiment, the X transfer start pulse DX becomes active at the H level, and the sampling signals SR1 to SRn become active at the H level. Although the logical-form data line drive circuit 150A has been described as an example, on the contrary,
The X transfer start pulse DX becomes active at L level,
Of course, the data line drive circuit 150B of the negative logic type in which the sampling signals SR1 to SRn are active at the L level may be used.

FIG. 7 is a block diagram showing a configuration of the data line drive circuit 150B. As shown in this figure, the data line driving circuit 150B is configured similarly to the data line driving circuit 150A shown in FIG. 4 except that a logical operation unit 152 'is used instead of the logical operation unit 152. More specifically, in each of the operation unit circuits Ub1 to Ubn, NOR circuits 504-1 to 504-1 are used instead of the NAND circuits 504-1 to 504-n.
4 is the same as the data line driving circuit 150A shown in FIG. 4 except that the NAND circuits 505-1 to 505-n-1 are used instead of the NOR circuits 505-1 to 505-n-1. It is.

FIG. 8 is a timing chart showing the operation of data line drive circuit 150B. Each signal S1, S2,
Are rising pulses Esu1, Esu2,.
, While falling edges Ecd1, Ecd2,... Of the signals S1, S2,.
Are determined by rising edges Ecu0, Ecu1,... Of shift pulses C0, C1,.

For example, while the falling edge Esd1 of the signal S1 is determined by the rising edge Ecu0 of the shift pulse C0,
The rising edge Esu2 of the signal S2 is determined by the falling edge Ecd2 of the shift pulse C2. That is, the rising edge Esuj of the temporally adjacent signal Sj and the signal Sj +
One falling edge Ecdj + 2 is generated due to a different signal.

The NAND circuits 505-1 to 505-n-1 use the output signal of the shift unit circuit at the next stage of the shift unit circuit corresponding to the signals S1 to Sn-1 as an input signal. For example, the NAND circuit 505-1 uses the signal S1 and the shift pulse C2 as input signals. Here, the sampling signal SR1, which is the output signal of the NAND circuit 505-1, has a rising edge Eru1.
Is determined by the falling edge Ecd2 of the shift pulse C2. On the other hand, the falling edge Erd of the sampling signal SR2
2 is determined by the rising edge Esu2 of the signal S2. As described above, since the rising edge Esu2 of the signal S2 is determined by the falling edge Ecd2 of the shift pulse C2, the falling edge Erd2 of the sampling signal SR2 is determined by the falling edge Ecd2 of the shift pulse C2.

That is, the NAND circuits 505-1 to 505-n
-1, the sampling signal SRj which is temporally adjacent
And the falling edge Erjj + 1 of the sampling signal SRj + 1 can be determined based on the falling edge Ecuj + 1 of the same shift pulse Cj + 1. Thus, each of the sampling signals SR1 to SRn can be exclusively activated.

It is needless to say that the scanning line driving circuit 130 may be configured in a negative logic form, similarly to the data line driving circuit 150B shown in FIG. In this case, the Y transfer start pulse becomes active at L level, and each scanning line signal becomes active at L level.

<2-2: Structure of Element Substrate> In each of the above-described embodiments, the element substrate 151 of the liquid crystal panel is formed of a transparent insulating substrate such as glass, and a silicon thin film is formed on the substrate. In addition, the switching elements (TFTs 50) of the pixels, the elements of the data line driving circuit 100, and the elements of the scanning line driving circuit 200 are described as being constituted by the TFTs having a source, a drain, and a channel formed on the thin film. The present invention is not limited to this.

For example, the element substrate 151 is formed of a semiconductor substrate, and a switching element of a pixel and elements of various circuits are formed by an insulated gate field effect transistor having a source, a drain, and a channel formed on the surface of the semiconductor substrate. You may comprise. When the element substrate 151 is formed of a semiconductor substrate as described above, it cannot be used as a transmissive display panel. Therefore, the pixel electrode 9a is formed of aluminum or the like and used as a reflective type. Alternatively, the element substrate 151 may simply be a transparent substrate and the pixel electrode 9a may be of a reflection type.

It should be noted that instead of forming a part or all of the peripheral circuits such as the data line driving circuit 150 and the scanning line driving circuit 130 on the element substrate 151, for example, TAB (Tape A)
The driving IC chip mounted on the film using the utomated bonding technique may be electrically and mechanically connected via an anisotropic conductive film provided at a predetermined position on the element substrate 151. The IC chip itself is mounted on the element substrate 1 using COG (Chip OnGrass) technology.
It may be configured to be electrically and mechanically connected to a predetermined position 51 via an anisotropic conductive film.

<2-3: Electronic Apparatus> Next, a case where the above-described liquid crystal device is applied to various electronic apparatuses will be described. <2-3-1: Projector> First, a projector using this liquid crystal device as a light valve will be described. FIG. 9 is a plan view showing a configuration example of the projector.

As shown in FIG.
Inside 100, a lamp unit 1102 composed of a white light source such as a halogen lamp is provided. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and is used as a light valve corresponding to each primary color. Liquid crystal panels 1110R, 1110B and 1110
G is incident.

The configuration of the liquid crystal panels 1110R, 1110B, and 1110G is the same as that of the above-described liquid crystal panel 100, and is driven by R, G, and B primary color signals supplied from an image signal processing circuit (not shown). It is. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, the R and B lights are refracted at 90 degrees, while the G light travels straight. Therefore, as a result of combining the images of each color,
A color image is projected on a screen or the like via the projection lens 1114.

Here, each liquid crystal panel 1110R, 111
Focusing on the display images by 0B and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally inverted with respect to the display image by the liquid crystal panels 1110R and 1110B.

The liquid crystal panels 1110R, 1110B
And 1110G have a dichroic mirror 1108
Accordingly, light corresponding to each of the primary colors R, G, and B is incident, so that it is not necessary to provide a color filter.

<2-3-2: Mobile Computer>
Next, an example in which the liquid crystal panel is applied to a mobile personal computer will be described. FIG. 10 is a perspective view showing the configuration of the personal computer.
In the figure, a computer 1200 includes a keyboard 12
02 with the liquid crystal display unit 12
06. This liquid crystal display unit 12
Reference numeral 06 is configured by adding a backlight to the back surface of the liquid crystal display panel 100 described above.

<2-3-3: Mobile Phone> An example in which the liquid crystal display panel 100 is applied to a mobile phone will be described. FIG. 11 is a perspective view showing the configuration of the mobile phone. In the figure, a mobile phone 1300 includes a plurality of operation buttons 1302 and a reflective liquid crystal panel 1005. In the reflection type liquid crystal panel 1005, a front light is provided on the front surface as needed.

Note that, in addition to the electronic devices described with reference to FIGS. 9 to 11, a liquid crystal television, a viewfinder type,
Examples include a monitor-directed video tape recorder, a car navigation device, a pager, an electronic organizer, a calculator, a word processor, a workstation, a videophone, a POS terminal, and a device equipped with a touch panel. It goes without saying that the present invention can be applied to these various electronic devices.

[0079]

As described above, according to the driving circuit of the present invention, the active period of each output signal can be exclusively activated with a simple configuration. Further, by applying this driving circuit to a data line driving circuit or a scanning line driving circuit, it is possible to prevent crosstalk and display a high quality image.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a liquid crystal device according to the present invention.

FIG. 2 is a perspective view illustrating the structure of a liquid crystal display panel.

FIG. 3 is a partial cross-sectional view illustrating a structure of a liquid crystal display panel.

FIG. 4 is a circuit diagram showing a detailed configuration of a data line driving circuit 150A of the device.

FIG. 5 is a timing chart of the data line driving circuit 150A.

FIG. 6 is a block diagram illustrating a configuration of a scanning line driving circuit 130.

FIG. 7 is a data line driving circuit 150B corresponding to negative logic.
FIG.

FIG. 8 is a timing chart of the data line driving circuit 150B.

FIG. 9 is a cross-sectional view of a video projector as an example of an electronic apparatus to which the liquid crystal device is applied.

FIG. 10 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which the liquid crystal device is applied.

FIG. 11 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the liquid crystal device is applied.

FIG. 12 is a circuit diagram showing a configuration of a conventional shift register.

FIG. 13 is a timing chart showing the operation of a conventional shift register.

[Explanation of symbols]

112 scanning line 114 data line 118 pixel electrode 116 TFT (switching element) SR1 to SRn sampling signal (selection signal) VID input image signal 150A, 150B data line drive circuit 151 ... X shift register (shift register section) 152... Logical operation section 130... Scanning line drive circuit Ua0 to Uan... Shift register unit circuit (shift unit circuit) Ub1 to Ubn.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 623 G09G 3/20 623H 623R F-term (Reference) 2H093 NA16 NC16 NC22 NC34 ND08 ND15 ND39 NE06 NG02 5C006 BB16 BC03 BC12 BC20 BF03 BF11 BF25 BF26 BF27 EB05 EC08 EC11 FA21 FA36 FA41 FA47 5C080 AA10 BB05 DD10 DD22 DD26 FF11 JJ02 JJ04 JJ06 KK07

Claims (8)

[Claims] 1. An electro-optical panel having a plurality of scanning lines, a plurality of data lines, and pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines. A drive circuit for an electro-optical panel including a shift register unit and a logical operation unit, wherein the shift register unit sequentially shifts a start pulse based on a clock signal and outputs a plurality of shift signals each for outputting an output signal. The logic operation unit includes a plurality of operation unit circuits provided respectively corresponding to the shift unit circuits, and one operation unit circuit includes an input signal and an output of the corresponding shift unit circuit. A first signal for specifying a first period in which both the signal and the signal are active is generated, and the first signal and a second signal output from the next shift unit circuit of the shift unit circuit are output. Based on the item, the driving circuit for an electro-optical panel and generates an output signal which becomes active in a third period except the active period of the second signal from the active period of the first signal. 2. The NAND circuit according to claim 1, wherein the operation unit circuit performs an AND operation of an input signal and an output signal of a corresponding shift unit circuit and outputs the result as the first signal; 2. The driving circuit for an electro-optical panel according to claim 1, further comprising a NOR circuit that calculates an inverted OR of the signal and the output and outputs the result as the output signal. 3. The NOR circuit according to claim 1, wherein the operation unit circuit calculates an inverted OR of an input signal and an output signal of a corresponding shift unit circuit and outputs the result as the first signal; 2. The drive circuit for an electro-optical panel according to claim 1, further comprising: a NAND circuit that calculates an inverted logical sum of the output signal and a signal and outputs the result as the output signal. 4. A driving circuit according to claim 1, wherein an input image signal is sampled based on each selection signal output from the driving circuit, and the sampling is performed to each data line. A data line driving circuit characterized by supplying the data. 5. The driving circuit according to claim 1, wherein each of the scanning lines is driven based on a selection signal output from the driving circuit. Scan line driver circuit. 6. A pixel region having a plurality of scanning lines, a plurality of data lines, and pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines. An electro-optical panel, comprising: the data line driving circuit according to item 4; and a scanning line driving circuit for driving the scanning line. 7. A pixel region having a plurality of scanning lines, a plurality of data lines, and pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines, An electro-optical panel comprising: a data line driving circuit for driving a data line; and the scanning line driving circuit according to claim 5. 8. An electronic apparatus comprising the electro-optical panel according to claim 6.