JP2001324951A - Shift register, control method therefor, data line driving circuit, scanning line driving circuit, electro-optical panel, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an X-shift register which surely operates even if a clock signal has a low driving ability. SOLUTION: The X-shift register 110A is configured of a shift register 111 cascading each of the shift register unit circuits Ua1-Uan+2, and a clock control circuit 112 cascading each of the control unit circuits Ub2-Ubn+2. Each of the control unit circuit Ub2-Ubn+1 supplies an X-clock signal XCK and an inverse X-clock signal XCKB to the shift register unit circuits Ual-Uan+2 only for the period when either the signal voltages of the connection points A2-An+2 of the corresponding shift register unit circuits Ub2-Ubn+2 or those of the connection voltages A1-An+1 of the preceding stage become active.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is to drive an electro-optical panel having a plurality of scanning lines and a plurality of data lines, and pixel electrodes and switching elements arranged in a matrix corresponding to their intersections. Register, a control method thereof, a data line driving circuit and a scanning line driving circuit using the shift register, an electro-optical panel, and an electronic apparatus.

[0002]

2. Description of the Related Art A driving circuit of a conventional electro-optical device, for example, a liquid crystal device, supplies a data line signal or a scanning signal to a data line or a scanning line wired in an image display area at a predetermined timing. It is composed of a data line driving circuit, a scanning line driving circuit, and the like.

The basic structure of a data line driving circuit differs depending on whether an input image signal is an analog signal or a digital signal. However, in any case, the data line driving circuit includes a shift register that sequentially shifts a transfer signal supplied at the beginning of a horizontal scanning period in accordance with a clock signal.

As this shift register, Japanese Patent Laid-Open No.
The circuit shown in FIG. 20 is disclosed in 199284. In this shift register, basic units are connected in multiple stages, and each basic unit is driven by a clock signal HCK and an inverted clock signal HCKX obtained by inverting the clock signal HCK. Here, the basic unit Un of the n-th stage includes inverters INV1, INV2, INV3, a NOR circuit NOR, and switches SWa, SWb which are turned on when the control voltage is at the L level and turned off when the control voltage is at the H level. . The inverters INV1 and INV2 invert and output each input signal when the control voltage is at the H level, and bring the output terminals into a high impedance state when the control voltage is at the L level.

In such a circuit, the inverter INV
It is not necessary to always operate INV2 and INV2 need only operate during the period when the signal Dn is active or during the period when the signal Dn + 1 is active. For this reason, the NOR circuit NOR calculates the inverted OR of the signal Dn and the signal Dn + 1,
The switches SWa and SWb are controlled based on the calculation result. As a result, the clock signal HCK and the inverted clock signal HCKX are output from the inverters INV1 and INV2 only during a predetermined period.
Supplied to

Therefore, the period during which the clock signal HCK and the inverted clock signal HCKX are supplied to each basic unit constituting the shift register can be limited. As a result, power consumption of the shift register can be reduced.

[0007]

FIG. 21 is a timing chart of a conventional shift register. In this shift register, when the signal Dn rises from the low level to the high level, the signal Dn becomes the inverter INV1 and the inverter INV1.
The signal is transmitted via INV3 and output as a signal Dn + 1. That is, the rising edge E1 of the signal Dn + 1 is
The delay due to the inverter INV1 and the response characteristics of the transistors forming the inverter INV3 are affected. For this reason,
As shown in the figure, the rising edge E1 is later than the original rising time t1, and the rising time is longer.

On the other hand, the falling edge E2 of the signal Dn + 1
Is affected by the delay caused by the inverter INV1 and the response characteristics of the transistors constituting the inverter INV2. Therefore, as shown in the figure, the rising edge E1 is later than the original rising time t1, and the falling time is longer. Similarly, the rising edge and the falling edge of the signal Dn + 2 are delayed, and their slopes become gentler.

Since the output signal of the NOR circuit NOR of the basic unit Un + 1 is generated based on the signals Dn + 1 and Dn + 2, its signal waveform is as shown in FIG.
Delays from the edges of HCK and the inverted clock signal HCKX. Therefore, the clock signal CKA and the inverted clock signal CKB supplied to the inverters INV1 and INV2 are gated by the NOR circuit NOR, and a part thereof is missing as shown in the figure.

That is, the conventional shift register has a problem that the operation margin is reduced and a malfunction is likely to occur.

In the shift register shown in FIG. 20, the wiring capacity for supplying the clock signal HCK and the inverted clock signal HCKX is determined by the switches SWa, S of each basic unit.
When Wb is turned on, the wiring capacitance CL from the output terminals of the switches SWa and SWb to the control input terminals of the inverters INV1 and INV2 and the input capacitance Cin of the inverters INV1 and INV2 are added.

Therefore, the drive circuit for supplying the clock signal HCK and the inverted clock signal HCKX to the wiring must be designed in consideration of the maximum number of basic units to which the signals HCK and HCKX are simultaneously supplied.

If the shift register is composed of m basic units, the output signals D1, D2,... Dn,. It is indeterminate whether the level will be H level or L level. If all the output signals D1, D2,.
If Dn,... Dm become H level, the clock signal HCK and the inverted clock signal H are supplied to all m basic units.
CKX will be supplied.

Therefore, in the conventional shift register, after all, the clock signal HC is supplied to all m basic units.
Assuming that K and the inverted clock signal HCKX are supplied, it is necessary to use a circuit capable of driving a capacitance of m · (CL + Cin). In other words, as a driving circuit that supplies the clock signal HCK and the inverted clock signal HCKX,
In consideration of a heavy load at the time of turning on the power, it is necessary to use a device capable of supplying a large current at a high response speed, and there is a problem that the circuit configuration becomes large-scale and a large current consumption is required.

The present invention has been made in view of the above circumstances, and has as its object to increase the operation margin of a shift register and to operate the shift register stably. Another object is to provide a shift register or the like which can reduce the load on a driver circuit for supplying a clock signal and reduce power consumption.

[0016]

In order to achieve the above object, a shift register according to the present invention includes a plurality of scanning lines, a plurality of data lines, and a plurality of scanning lines each corresponding to an intersection between the scanning lines and the data lines. Used in a drive circuit for driving an electro-optical panel having pixel electrodes and switching elements arranged in a matrix, and by sequentially shifting a start pulse, a selection signal for selecting the data line or the scan line is generated. Shifting means for sequentially generating a plurality of shift unit circuits for sequentially shifting the start pulse based on a first clock signal and a second clock signal obtained by inverting the first clock signal and outputting an output signal; Clock signal supply means having a plurality of control unit circuits respectively provided corresponding to each of the shift unit circuits, wherein the shift unit circuit includes A signal is supplied to an input terminal and operates only during an active period of the first clock signal, and a first inverter that sets an output terminal to a high impedance state during the inactive period, and an output signal of the shift unit circuit is connected to an input terminal. A second inverter that is supplied and operates only during an active period of the second clock signal, and sets the output terminal to a high impedance state during the inactive period and connects the output terminal to the output terminal of the first inverter; A third inverter in which a connection point between the first inverter and the second inverter is connected to an input terminal, and an input terminal of the second inverter is connected to an output terminal; The signal voltage at the connection point in the circuit and the signal voltage in the previous shift unit circuit Among the signal voltage of the connection point, only during a period in which either one is active,
The clock signal and the inverted clock signal are supplied to a corresponding shift unit circuit.

According to the present invention, the control unit circuit generates the clock based on the signal voltage at the connection point between the first inverter and the second inverter in the corresponding shift unit circuit and the signal voltage at the connection point in the preceding shift unit circuit. This controls whether the signal and the inverted clock signal are supplied to the shift unit circuit. The change in the signal voltage at the connection point is the first
And when the second inverter makes a transition from active to inactive or from inactive to active, and the transition timing is directly synchronized with the first clock signal and the second clock signal. Therefore, the control unit circuit can supply the first and second clock signals to the shift unit circuit with a short delay time. In addition, the supply of the first and second clock signals is not affected by the response characteristics of the third inverter.
As a result, the operation margin can be increased, and the reliability of the shift register can be increased.

Further, the shift register according to the present invention comprises a plurality of scanning lines, a plurality of data lines, pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines. A shift register for generating a selection signal for selecting the data line or the scanning line by sequentially shifting a start pulse, the first clock being used for a driving circuit for driving an electro-optical panel having a first clock. A shift means in which a plurality of shift unit circuits for sequentially shifting the start pulse based on a signal and a second clock signal obtained by inverting the signal and outputting an output signal are cascaded; Clock signal supply means having a plurality of control unit circuits provided, wherein the shift unit circuit is configured such that an output signal of a preceding stage is supplied to an input terminal. A first inverter that operates only during an active period of the first clock signal and sets an output terminal in a high impedance state during the inactive period, and an output signal of the shift unit circuit is supplied to an input terminal, and the second clock signal Operates only during the active period, while the output terminal is in a high impedance state during the inactive period, the output terminal is connected to the output terminal of the first inverter, the second inverter is connected to the input terminal, and the reset signal is applied to one input terminal. The other input terminal is connected to a connection point between the first inverter and the second inverter, and inverts a signal voltage at the connection point during an inactive period of the reset signal to input an input terminal of the second inverter. And output as the output signal of the shift unit circuit A logic circuit for resetting an output signal of the shift unit circuit during an active period of the reset signal, wherein the control unit circuit is configured to control a signal voltage of the connection point in a corresponding shift unit circuit and a signal voltage of a preceding shift unit circuit. The clock signal and the inverted clock signal are supplied to the corresponding shift unit circuit only during a period in which one of the signal voltage at the connection point is active.

According to the present invention, by supplying the reset signal, it is possible to reset all the output signals of the respective shift unit circuits constituting the shift means and to make the second inverter inactive. Also, the control unit circuit supplies the clock signal and the inverted clock signal to the corresponding shift unit circuit only during a period in which one of the signal voltages at the connection point of the corresponding shift unit circuit and the connection point of the preceding stage is active. Therefore, even if the output signals of all the shift unit circuits are activated when the power of the shift register is turned on, if reset by the reset signal, the control unit circuit does not supply the clock signal and the inverted clock signal to the shift unit circuit. . Therefore, once the reset signal is activated after the power is turned on, the load on the driving circuit for supplying the clock signal can be reduced, and further, the power consumption can be reduced.

Here, if the start pulse becomes active at H level, the control unit circuit outputs the clock signal and the inverted clock signal based on an output signal of the NAND circuit and the NAND circuit. First and second
First and second transfer gates each supplying an inverter, a third transfer gate supplying a logic voltage to the first inverter to make it inactive when the first transfer gate is in a high impedance state, A second transfer gate for supplying a logic voltage to activate the second inverter when the second transfer gate is in a high impedance state.

In this case, when the signal voltage at the connection point is at L level, the output signal of the NAND circuit becomes H level,
A clock signal and an inverted clock signal are supplied to the first and second inverters, respectively.

If the start pulse is active at the L level, the control unit circuit converts the clock signal and the inverted clock signal based on the output signal of the NOR circuit and the NOR circuit. First and second transfer gates respectively supplying first and second inverters, and third transfer for supplying a logic voltage to the first inverter to make it inactive when the first transfer gate is in a high impedance state It is preferable to include a gate and a fourth transfer gate for supplying a logic voltage to activate the second inverter to the second inverter when the second transfer gate is in a high impedance state.

In this case, when the signal voltage at the connection point is at the H level, the output signal of the NOR circuit goes to the L level, and the clock signal and the inverted clock signal are supplied to the first and second inverters, respectively. .

In the above-described shift register receiving the supply of the reset signal, if the reset signal is active at the H level, the logic circuit is preferably a NOR circuit. Is active at the L level, the logic circuit is preferably a NAND circuit.

Next, a data line driving circuit according to the present invention includes any of the above-described shift registers, and based on the selection signal output from the shift register,
It is characterized in that input image data is latched, the latched input image data is converted from a digital signal to an analog signal, and supplied to each data line. In this case, the input image data is latched based on the selection signal. However, since the operation margin of the shift register is large, the input image data can be reliably latched at a predetermined timing. This makes it possible to provide a data line driving circuit that is resistant to temperature changes and aging.

The data line driving circuit according to the present invention includes any one of the above-described shift registers, and based on the selection signal output from the shift register,
The input image signal may be sampled, and each data line may be driven based on the sampling result. According to the present invention, since the input image signal can be sampled reliably at a predetermined timing, it is possible to provide a data line driving circuit that is resistant to temperature change and aging.

Next, a scanning line driving circuit according to the present invention includes any of the above-described shift registers, and based on the selection signal output from the shift register,
Each of the scanning lines is driven. According to this scanning line drive circuit, since the selection signal can be generated by reliably transferring the start pulse, the scanning line is driven stably even when the temperature changes greatly or the use period becomes long. be able to.

Next, a method of controlling a shift register according to the present invention is characterized in that the reset signal is activated every field or every plural fields. In this case, since the shift register is reset every field or every plural fields, the shift register is reset in the first field after the power is supplied to the shift register. Even when the output signals of the shift unit circuits are all active and the load when supplying the clock signal is extremely heavy, the load can be reduced by resetting. As a result, the circuit configuration of the driving circuit for driving the clock signal can be simplified, and the power consumption can be reduced. Further, even if a malfunction occurs in an output signal due to noise or the like in a certain field,
Since the shift register can be reset at a predetermined reset cycle, malfunction due to noise or the like can be recovered at the reset cycle.

Further, in the shift register control method according to the present invention, the reset signal is supplied during a part of a period from when a power supply voltage is supplied to the shift register to when the clock signal is supplied. , At least active. In this case, the shift register is always reset during a period from when the power supply voltage is supplied to the shift register to when the clock signal is supplied. Therefore, even when the power is turned on, all the output signals of the shift unit circuit are output. Even when the load becomes extremely active and the clock signal is supplied, the load can be reduced by resetting. As a result, the circuit configuration of the driving circuit for driving the clock signal can be simplified, and the power consumption can be reduced.

Next, in the electrical engineering panel of the present invention, a plurality of scanning lines, a plurality of data lines, and pixels arranged in a matrix corresponding to intersections of the scanning lines and the data lines. A pixel region having electrodes and switching elements, a data line driver circuit using the above-described shift register, and a scan line driver circuit for driving the scan line are provided. Further, an electrical engineering panel using the above-described shift register as a scan line driver circuit may be used. According to these configurations, a drive circuit is built on the electro-optical panel. In this case, the switching element formed in the pixel region is a thin film transistor, and the driving circuit is preferably formed of a thin film transistor.

An electronic apparatus according to the present invention includes the above-described electro-optical panel, and includes, for example, a view finder used for a video camera, a mobile phone, a notebook computer, a video projector, and the like. I do.

[0032]

Embodiments of the present invention will be described below with reference to the drawings.

<1. First Embodiment><1-1: Overall Configuration of Liquid Crystal Device> First, a liquid crystal device using liquid crystal as an electro-optical material will be described as an example of an electro-optical device according to the present invention. The main part of the liquid crystal device is
As will be described later, an element substrate on which a thin film transistor (hereinafter, referred to as a “TFT”) is formed as a switching element and a counter substrate are attached to each other with an electrode forming surface facing each other and a constant gap. The liquid crystal panel has a liquid crystal sandwiched in the gap.

FIG. 1 is a block diagram showing the overall configuration of the liquid crystal device according to the first embodiment. This liquid crystal device has an image display area A and a data line driving circuit 1 on a liquid crystal panel element substrate.
00, a scanning line driving circuit 200, and a timing generation circuit 300 as an external processing circuit.

The input image data D supplied to the liquid crystal device is in a 3-bit parallel format. In this example, in order to simplify the following description, the input image data D is described as corresponding to one color, but the present invention is not limited to this, and the input image data D corresponds to three primary colors of RGB. Of course, it may be.

Here, the timing generation circuit 300 synchronizes with the input image data D to generate a Y clock signal YCK, an inverted Y clock signal YCKB, an X clock signal XCK, an inverted X clock signal XCKB, a Y transfer start pulse DY, and an X transfer. By generating a start pulse DX, a latch pulse LAT, and the like, the data line driving circuit 100 and the scanning line driving circuit 2
00 is supplied.

<1-2: Image Display Area> Next, as shown in FIG. 1, the image display area A has m scanning lines 3a.
Are arranged in parallel along the X direction, while n
The data lines 6a are arranged in parallel along the Y direction. Near the intersection of the scanning line 3a and the data line 6a, the gate of the TFT 50 is connected to the scanning line 3a.
While the source of the TFT 50 is connected to the data line 6a.
And the drain of the TFT 50 is connected to the pixel electrode 9a. Each pixel includes a pixel electrode 9a and a counter electrode (described later) formed on a counter substrate.
And a liquid crystal sandwiched between these electrodes. As a result, the pixels are arranged in a matrix corresponding to each intersection of the scanning line 3a and the data line 6a.

The scanning signals Y1, Y2,..., Ym are applied to each scanning line 3a to which the gate of the TFT 50 is connected in a pulsed line-sequential manner. For this reason, when a scanning signal is supplied to a certain scanning line 3a, the TFT 50 connected to the scanning line is turned on, so that the image signals X1 and X1 supplied from the data line 6a at a predetermined timing.
X2,..., Xn are written in the corresponding pixels in order, and are held for a predetermined period.

Here, since the orientation and order of the liquid crystal molecules change according to the voltage level applied to each pixel, gray scale display by light modulation becomes possible. For example, in a normally white mode, the amount of light passing through the liquid crystal is limited as the applied voltage increases, while in a normally black mode, the amount of light is reduced as the applied voltage increases. Then, light having a contrast according to the image signal is emitted for each pixel. For this reason, a predetermined display is possible.

Further, in order to prevent the held image signal from leaking, a storage capacitor 51 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. For example, since the voltage of the pixel electrode 9a is held by the storage capacitor 51 for a time that is three orders of magnitude longer than the time during which the source voltage is applied, the holding characteristics are improved, and a high contrast ratio is realized. Become.

<1-3: Data Line Driving Circuit> Next, as shown in FIG. 1, the data line driving circuit 100 includes an X shift register 110A and image data supply lines L1 to L3 to which image data D0 to D2 are supplied. , Switches SW1 to SW3n,
A first latch 120, a second latch 130, and a D / A converter 140 are provided.

First, the X shift register 110A sequentially shifts the X transfer start pulse DX according to the X clock XCK and the inverted X clock XCKB to sequentially generate the sampling pulses SR1, SR2,..., SRn. . The detailed configuration of the X shift register 110A will be described later.

Next, the image data supply lines L1 to L3 are connected to the first latch 120 via the switches SW1 to SW3n, and the control input terminals of the switches SW1 to SW3n are connected to the sampling pulses SR1, SR2, …, S
Rn is supplied. Also, switch S
W1 to SW3n are 3 corresponding to the image data D0 to D2.
Each set has one set. Therefore, in synchronization with the sampling pulses SR1, SR2,.
The image data D0 to D2 are simultaneously supplied to the first latch 120.

Next, the first latch 120 is connected to the switch SW
Image data D0 to D2 supplied from 1 to SW3n are latched, whereby data scanned in dot-sequential manner is obtained. Also, the second latch 130
Each output data of the first latch 120 is latched by a latch pulse LAT.
Latch. Here, the latch pulse LAT is 1
This signal is active every horizontal scanning period. Therefore, the second latch 130 converts each data of the first latch 120 input in a dot-sequential manner into each data in a line-sequential manner.

Next, the D / A converter 140 converts the 3-bit image data D0 to D2 from a digital signal to an analog signal, generates data line signals X1 to Xn, and applies these to the data lines 6a. Supplying.

<1-4: Configuration of X Shift Register> Next, the configuration of the X shift register 110A will be described. FIG. 2 is a circuit diagram showing a detailed configuration of the X shift register. As shown in the figure, the X shift register 110A
It includes a shift register 111A and a clock control circuit 112.

First, the shift register 111A is configured by cascade-connecting the shift register unit circuits Ua1 to Uan + 2. Each shift register unit circuit Ua1 to Uan + 2 is
Clocked inverters 501 and 502 and inverter 50
And the first shift register unit circuit Ua1 includes an inverter Z.

Clocked inverters 501 and 502
When the control terminal voltage is at H level, each input signal is inverted and output, and when the control terminal voltage is at L level, the output terminal is brought into a high impedance state. Each control terminal is supplied with a clock signal XCK and an inverted X clock signal XCKB which are active only for a predetermined period.

For example, in the shift register unit circuit Ua1, when the control signal Q1 is at the H level, the clocked inverter 501 inverts and outputs the input signal. At this time,
Since the control signal Q2 is at the L level, the output terminal of the clocked inverter 502 is in a high impedance state. Therefore, in this case, the input signal is output via clocked inverter 501 and inverter 503. On the other hand, when control signal Q2 is at H level, clocked inverter 502 inverts the input signal and outputs the inverted signal.
At this time, since the control signal Q1 is at the L level,
The output terminal of clocked inverter 501 is in a high impedance state. In this case, the clocked inverter 502 and the inverter 503 form a latch circuit.

Next, the clock control circuit 112 controls each control unit circuit Ub1 including the NAND circuit 506, the inverter 507, and the transfer gates 508 to 511 as one set.
To Ubn + 2 in cascade. Each of the control unit circuits Ub1, Ub2,..., Ubn + 2 is a shift register unit circuit Ua.
1, Ua2,..., Uan + 2.

Here, focusing on the second control unit circuit Ub1, the signal P1 is supplied to one input terminal of the NAND circuit 506, and the signal P2 is supplied to the other input terminal. Signals P1 and P2 are voltages at connection points A1 and A2 of clocked inverters 501 and 502, respectively.

The reason why the clock control signal N2 for controlling the transfer gates 508 to 511 is generated based on the signal P1 and the signal P2 in order to prevent deterioration of the waveform characteristics due to the inverter 503. . In the conventional shift register shown in FIG. 20, a clock control signal is generated based on an output signal between adjacent basic units, that is, an output signal of an inverter INV3 (corresponding to the inverter 503 of the present embodiment). Was. For this reason, the rising edge and the falling edge of the clock control signal are affected by the response characteristics of the inverter INV3, and the slopes thereof become gentle.

On the other hand, the voltage at the connection points A1, A2,... Is determined by the output voltage of the clocked inverter 501 or 502. As shown in FIG.
2 transfers the signal P1, so that the clock control signal N2 changes its logic level in synchronization with the falling edge of the signal P1 and the rising edge of the signal P2.
The logic levels of the signals P1 and P2 are the X clock signal X
Since it is determined based on CK and the inverted X clock signal XCKB, the X clock signal XCK and the inverted X clock signal XCK are determined.
The delay time of the clock control signal N2 with respect to B can be reduced, and the waveform deterioration due to the inverter 503 can be prevented.

Next, the transfer gates 508 and 509 are for supplying the X clock signal XCK to the clocked inverter 501. As a result, when the output signal of the NAND circuit 506 is at the H level, X control is applied to the control input terminal of the clocked inverter 501.
While the clock signal XCK is supplied and the output signal is at the L level, the transfer gate 508
Is in a high impedance state, so that the supply of the X clock signal XCK is stopped.

Transfer gates 510 and 511 supply the inverted X clock signal XCKB to clocked inverter 502. As a result, when the output signal of NAND circuit 506 is at the H level, inverted X clock signal XCKB is supplied to the control input terminal of clocked inverter 502. On the other hand, when the output signal is at the L level, transfer gate 510 is turned off. Since the state becomes the high impedance state, the supply of the inverted X clock signal XCKB is stopped.

That is, a certain control unit circuit Ubj is one of the signal voltage of the connection point Aj in the corresponding shift register unit circuit Uaj and the signal voltage of the connection point Aj-1 in the preceding shift register unit circuit Uaj-1. Only during a period in which one becomes active (in this example, L level), X
Clock signal XCK and inverted X clock signal XCKB
Is supplied to the shift register unit circuit Uaj.

<1-5: Operation of X Shift Register> Next, the operation of the X shift register 110A will be described with reference to FIG. FIG. 3 shows an X shift register 110A.
6 is a timing chart showing the operation of FIG.

First, at time T1, when the X transfer start pulse DX rises from L level (inactive) to H level (active), the signal P0 changes to L level,
Clock control signal N1 attains H level. Transfer gates 508 and 510 are connected to clock control signal N1.
Is turned on when H is at the H level.
The clock signal XCK and the inverted X clock signal XCKB are supplied to the clocked inverters 501 and 502, respectively.

At time T2, X clock signal XCK goes high, and clocked inverter 501 becomes active. Therefore, the signal P1 becomes H at time T2.
It falls from the level to the L level.

Next, at time T3, the X clock signal X
While CK goes low, the inverted X clock signal XCK
Since B goes high, the clocked inverter 501
Becomes inactive while the clocked inverter 50
2 becomes active. Since clocked inverter 502 and inverter 503 constitute a latch circuit, signal P1 is maintained at L level.

Thereafter, at time T4, when the X transfer start pulse DX falls from H level to L level, the signal P0
Transitions from the L level to the H level.
1 remains at the L level, the clock control signal N1 is at the H level.
Maintain levels. Then, at time T5, the clocked inverter 501 becomes active in synchronization with the X clock signal XCK, and the clocked inverter 502 becomes inactive in synchronization with the inverted X clock signal XCKB. Since the X transfer start pulse DX at the time T5 is at the L level, the signal P1 goes to the H level at this point, and the clock control signal N1 transitions from the H level to the L level. Then, transfer gates 508 and 510
Is turned off, while the transfer gate 509 is turned off.
And 511 are turned on.

That is, during the period when the clock control signal N1 is at the H level (active), the X clock signal XCK
And the inverted X clock signal XCKB are supplied to the clocked inverters 501 and 502.

In the second shift register unit circuit Ua2, a clock control signal N2 is generated based on the signals P1 and P2, and the other shift register unit circuits Ua2 to Ubn + 2 are similarly processed. A clock control signal is generated.

In this embodiment, the clock control signal is supplied to the connection points A1 and A1 between the clocked inverters 501 and 502.
Since it is generated from the signal voltages P1, P2,.
X clock signal XCK and inverted X clock signal XCK
The delay time from the occurrence of the edge of B to the occurrence of the edge of the clock control signal can be reduced, and
The rise and fall of the waveform can be made steep. As a result, the operation margin of the X shift register 110A is expanded, so that the X transfer start pulse DX can be reliably transferred even if there is a temperature change or an aging change.

<1-6: Another Configuration Example of X Shift Register> The X shift register 110A described above corresponds to a positive logic in which the X transfer start pulse DX becomes active at the H level. X shift register 11 of this modified example
0A 'corresponds to negative logic in which the X transfer start pulse DX' is active at the L level.

FIG. 4 is a circuit diagram showing a detailed configuration of the X shift register 110A ', and FIG. 5 is a timing chart thereof. The X shift register 110A 'includes the shift register 111A and the clock control circuit 11 described above.
2 '. Here, the clock control circuit 112 ′
2 differs from the clock control circuit 112 shown in FIG. 2 in that a NOR circuit 506 'is used instead of the NAND circuit 506.

As shown in FIG. 5, the X transfer start pulse DX '
Become active at the L level, the signal P0 and the signal voltages P1, P2,... Of the connection points A1, A2,. In addition, the clock control signal N
Are active at the L level.

Therefore, also in this example, as in the case of the positive logic, a certain control unit circuit Ubj determines which one of the signal voltage Pj at the connection point Aj and the signal voltage Pj-1 at the preceding connection point Aj-1. The X clock signal XCK and the inverted X clock signal XCKB are supplied to the shift register unit circuit U only during a period in which one of them becomes active (in this example, H level).
supply to aj.

<1-7: Scan Line Drive Circuit> Next, the scan line drive circuit 200 will be described. FIG. 6 is a block diagram illustrating a configuration of the scanning line driving circuit 200. As shown in this figure, the scanning line driving circuit 200
10, a level shifter 203 and a buffer 204.

The Y shift register 210 includes a clock control circuit 201 and a shift register 202. The clock control circuit 201 includes a point to which the Y clock signal YCK and the inverted Y clock signal YCKB are supplied instead of the X clock signal XCK and the inverted X clock signal XCKB, and m control unit circuits corresponding to m scanning lines. X shift register 110A described above, except that
Is the same as that of the clock control circuit 112. In addition, the shift register 202 uses Y instead of the X transfer start pulse DX.
This is the same as the shift register 111A of the X shift register 110A described above, except that the transfer start pulse DY is supplied and that m shift register unit circuits corresponding to the m scanning lines are provided.

Therefore, Y shift register 210
Since the operation margin is large as in the case of the above-described X shift register 110A, the Y transfer start pulse DY can be reliably transferred even if there is a temperature change or an aging change.

The level shifter 203 includes a shift register 2
02 is shifted to a level suitable for driving the scanning line 3a. Buffer 2
04 converts each output signal of the level shifter 203 into low impedance, and outputs the scanning line drive signals Y1, Y2,.
Is output to each scanning line 3a.

In the scanning line driving circuit 200, the clock control circuit 201 and the shift register 20
As a matter of course, it is of course also possible to apply a negative logic shown in FIG.

<1-8: Example of Configuration of Liquid Crystal Panel> Next, the overall configuration of the liquid crystal panel according to the above-described electrical configuration will be described with reference to FIGS. Here, FIG.
FIG. 8 is a perspective view illustrating a configuration of a liquid crystal panel, and FIG. 8 is a cross-sectional view taken along line ZZ ′ in FIG.

As shown in these figures, the liquid crystal panel has an element substrate 151 such as glass or semiconductor on which the pixel electrodes 9a and the like are formed, and a transparent counter substrate 152 such as glass on which the common electrodes 158 and the like are formed. And a sealing material 154 in which spacers 153 are mixed so as to keep a certain gap therebetween so that the electrode forming surfaces face each other, and a liquid crystal 155 as an electro-optical material is sealed in this gap. I have. Note that the sealant 154 is formed along the periphery of the counter substrate 152,
5 is partially open to enclose it. Therefore, after the liquid crystal 155 is sealed, the opening is sealed by the sealing material 156.

Here, the data line driving circuit 100 described above is formed on one side of the sealing material 154 on the opposite surface of the element substrate 151 to drive the data line 6a extending in the Y direction. It has a configuration. further,
A plurality of connection electrodes 157 are formed on one side, and various signals and image data D0 from the timing generation circuit 300 are provided.
To D2. A scanning line driving circuit 200 is formed on one side adjacent to the one side, and is configured to drive the scanning lines 3a extending in the X direction from both sides.

On the other hand, the common electrode 158 of the opposite substrate 152
Of the four corners of the portion to be bonded to the element substrate 151
By the conductive material provided in at least one place,
Electrical continuity with the element substrate 151 is achieved. In addition, depending on the use of the liquid crystal panel,
For example, first, color filters arranged in a stripe, mosaic, triangle, or the like are provided. Second, for example, a metal material such as chromium or nickel, or carbon or titanium is dispersed in a photoresist. Third, a black matrix such as resin black is provided.
A backlight for irradiating the liquid crystal panel with light is provided.
In particular, in the case of color light modulation, a black matrix is provided on the counter substrate 152 without forming a color filter.

In addition, on the opposing surfaces of the element substrate 151 and the opposing substrate 152, an alignment film or the like rubbed in a predetermined direction is provided, and on the back side thereof, a polarizing plate (corresponding to the alignment direction) is provided. (Not shown) are provided. However, when a polymer-dispersed liquid crystal in which fine particles are dispersed in a polymer is used as the liquid crystal 155, the above-described alignment film, polarizing plate, and the like become unnecessary, and the light use efficiency is increased. This is advantageous in terms of low power consumption and the like.

Instead of forming part or all of the peripheral circuits such as the data line driving circuit 100 and the scanning line driving circuit 200 on the element substrate 151, for example, TAB (Tape A)
The driving IC chip mounted on the film using the utomated bonding technique may be electrically and mechanically connected via an anisotropic conductive film provided at a predetermined position on the element substrate 151. The IC chip itself is mounted on the element substrate 1 using COG (Chip OnGrass) technology.
It may be configured to be electrically and mechanically connected to a predetermined position 51 via an anisotropic conductive film.

<2. Second Embodiment> In the above-described first embodiment, the X shift registers 110A and 110A 'and the Y shift register 210 supply clock signals to the clocked inverters 501 and 502 of the j-th shift register unit circuit Uaj. The clock control signal is supplied to the connection point Aj-1 of the j-1st shift register unit circuit Uaj-1 and the jth shift register unit circuit Uaj-1.
Since the signal is generated based on the signal voltages Pj and Pj-1 at the connection point Aj of aj, the delay time of the clock control signal can be shortened and the slope of the signal waveform can be made steeper. The operation margin was expanded to improve reliability.

However, it is a matter of probability whether the signal voltage at the connection point A goes high or low when the power is turned on. Therefore, the X shift registers 110A and 110A 'and the Y shift register of the first embodiment are used. 210
Has to assume that the clock signal and the inverted clock signal are supplied to all the shift register unit circuits Ua when the power is turned on, as in the conventional shift register shown in FIG. For this reason, it is necessary to use a driving circuit that can supply a large current at a high response speed in consideration of a heavy load when the power is turned on, as a driving circuit for driving the clock signal and the inverted clock signal.

The second embodiment has been made in view of this point, and has as its object to reduce the power consumption when the power is turned on while performing the shift operation with high reliability.

<2-1: Overall Configuration of Liquid Crystal Device> First, the overall configuration of the liquid crystal device according to the second embodiment is substantially the same as the liquid crystal device of the first embodiment shown in FIG. The detailed configuration of the X shift register 110B of the scanning line driving circuit 200 and the Y shift register 210 of the scanning line driving circuit 200 are different. Further, the timing generation circuit 300 outputs a reset signal SIN which becomes active at the start of each field.
A difference from the first embodiment is that T is generated and supplied to the data line driving circuit 100 and the scanning line driving circuit 200.

The liquid crystal device of this embodiment resets the internal state of the X shift register 110B based on the reset signal SINT, as described later.

<2-2: Configuration of X Shift Register> FIG.
FIG. 9 is a circuit diagram illustrating a detailed configuration of an X shift register according to a second embodiment. As shown in the figure, the X shift register 1
10B includes the shift register 111B and the clock control circuit 112 described in the first embodiment.

First, the shift register 111B is configured by cascade-connecting the shift register unit circuits Ua1 to Uan + 2. Each shift register unit circuit Ua1 to Uan + 2 is
In addition to the clocked inverters 501 and 502, a NOR circuit 503a is provided instead of the inverter 503.
The first shift register unit circuit Ua1 has an inverter Z
It has.

In each of the shift register unit circuits Ua1 to Uan + 2, the NOR circuit 503a calculates the logical sum of the reset signal SINT and the output signal of the clocked inverter 502 and inverts and outputs the result.
Is at L level, it functions as an inverter that inverts the output signal of clocked inverter 502. Therefore, during the period when reset signal SINT is at L level (inactive period), clocked inverter 502
And the NOR circuit 503a function as a latch circuit.

On the other hand, in the period when the reset signal SINT is at the H level (active period), the NOR circuit 503a
Is forcibly reset to the L level. The reset signal SINT is a signal of one field cycle as described above, and becomes active during a very short period of a field start (for example, a part of a vertical blanking period). Therefore, each shift register unit circuit Ua1 to Uan
The +2 output signal is always reset at the start of each field and goes to the L level.

Now, the control signal supplied to the clocked inverter 502 and the output signal of the NAND circuit 506 when the power is turned on will be examined. First, when the output signal of the NAND circuit 506 is at the L level, the H-level voltage is supplied to the clocked inverter 502 as a control signal via the transfer gate 511. Then, the clocked inverter 502 operates as a normal inverter and forms a latch circuit together with the inverter 503, so that the voltages at the connection points A1 to An + 2 become H level and are maintained.

Next, when the output signal of NAND circuit 506 is at H level, inverted X clock signal XCKB is supplied via transfer gate 510. Since the inverted X clock signal XCKB goes to the H level in the initial state, the clocked inverter 502
Operates as a normal inverter, and the connection points A1 to An + 2
Is at the H level and is maintained.

In addition, since the X transfer start pulse DX at power-on is at L level, the inverter Z
, The signal level supplied to the first-stage NAND circuit 506 becomes H level.

Therefore, at the time of power-on, the output signals of NOR circuit 506 in each of control unit circuits Ub1 to Ubn + 2 are all at L level, and X clock signal XCK and inverted X clock signal XCKB are output to shift register 11
1B.

<2-3: Operation of X Shift Register> Next, the operation of the X shift register 110B will be described with reference to FIG. 10 and FIG. FIG. 10 is a timing chart showing the operation of the X shift register 110B during the vertical scanning period. FIG. 11 is a timing chart showing the operation of the X shift register 110B in the first horizontal scanning period after the power is turned on.

First, as shown in FIG. 10, at the start of one field period, the reset signal SINT becomes active (H level in this example), and thereafter, the Y transfer start pulse DY becomes active. Then, after the Y transfer start pulse DY rises from the L level to the H level,
A clock signal YCK is generated.

The 1/2 cycle of the Y clock signal YCK coincides with one horizontal scanning period, and within one horizontal scanning period, the X transfer start pulse DX, the X clock signal XCK and the inverted X clock shown in FIG. The signal XCKB is supplied to the X shift register 110B.

Therefore, assuming that the liquid crystal device is turned on at time T0 shown in FIG.
A reset signal SINT is generated. Thereafter, the X clock signal XCK and the inverted X clock signal XC shown in FIG.
The KB is supplied to the clock control circuit 112. In other words, the X clock signal XCK to the clock control circuit 112
And before the supply of the inverted X clock signal XCKB,
A reset signal SINT is generated, whereby the output signal of each shift register unit circuit included in the shift register 111B is reset to L level, and the signal voltages at the connection points A1 to An + 2 are reset to H level. Will be. In addition, since the X transfer start pulse DX at time T1 shown in FIG. 11 is at L level (inactive), the output signal level of the inverter Z at time T1 is at H level.

As described above, each control unit circuit operates when the signal voltages of the connection points A1 to An + 2, which are the input signals of the NAND circuit 506, and the output signal of the inverter Z are at the H level.
The X clock signal XCK and the inverted X clock signal XCKB are not supplied to the shift register 111B.

More specifically, at time T1, the transfer gates 508 and 510 of each of the control unit circuits Ub1 to Ubn + 2 are all in a high impedance state.
For example, focusing on the first shift register unit circuit Ua1 and the control unit circuit Ub1, at time T1, the output signal N1 of the NAND circuit 506 is at L level (inactive).
Therefore, the transfer gates 508 and 510
Is in a high impedance state.

In this case, the transfer gate 5
Since 09 and 511 are turned on, the signal Q1 goes low and the signal Q2 goes high as shown in FIG. Therefore, the output terminal of clocked inverter 501 is in a high impedance state, while the output terminal of clocked inverter 502 is in a low impedance state. Therefore, a latch circuit is formed by the clocked inverter 502 and the NOR circuit 503a.
The output signal of the second shift register unit circuit Ua1 is maintained at the L level which is the logic level at the time of reset, and the connection point A
1 is maintained at the H level.

Here, transfer gates 508 or 510 are supplied from control input terminals of clocked inverters 501 or 502 constituting each shift register 111B.
The capacitance value up to is represented by Ca, and other wiring capacitances are ignored. In this case, the input capacitance C when viewing the inside of the clock control circuit 112 from the input terminal of the X clock signal XCK at the time T1 becomes “0” as shown in the figure. This state is maintained until time T2.

Next, at time T2, when the X transfer start pulse DX, which is the input signal of the first shift register unit circuit Ua1, changes from L level to H level (active), the signal N1 changes from L level to H level. And the transfer gates 508 and 510 of the control unit circuit Ub1 are turned on. However, at time T2, the connection point A in each shift register unit circuit Ua1 to Uan + 2
Are still at the H level, the transfer gates 508 and 510 in the second to last control unit circuits Ub2 to Ubn + 2 are in a high impedance state. I have. Therefore, the input capacitance C at time T2 becomes “Ca” as shown in the figure. This state is maintained until time T3.

Next, the X transfer start pulse D at time T3
Since X is at the H level and the signal N1 is at the H level, the X clock signal XCK and the inverted X clock signal XCKB are supplied to the first shift register unit circuit Ua1. At time T3, the X clock signal XCK changes from L level to H level, while the inverted X clock signal XCKB changes from H level to L level.
The signal Q1 becomes H level and the clocked inverter 50
1 operates, while the signal Q2 goes low, and the output of the clocked inverter 502 goes into a high impedance state. As a result, the X transfer start pulse DX is output as the signal P1 via the clocked inverter 501,
The logic level changes from H level to L level.

Then, the NAND circuit 5 of the control unit circuit Ub2
06 output signal N2 changes from L level to H level, and transfer gates 508 and 510 are turned on. Therefore, at time T3, the X clock signal XCK and the inverted X clock signal XCKB are supplied to the first and second shift register unit circuits Ua1 and Ua2 via the first and second control unit circuits Ub1 and Ub2. Is done. As a result, the input capacitance C becomes "2Ca" as shown in FIG. This state is maintained until time T4.

In the second shift register unit circuit Ua2, the inverted X clock signal XCKB is applied to the signal Q.
3 is supplied to the clocked inverter 501, while the X clock signal XCK is supplied to the clocked inverter 50.
2 during the period from time T3 to time T4, the output terminal of the clocked inverter 501 is in the high impedance state, while the clocked inverter 5 is in the high impedance state.
02 operates.

Next, at time T4, X clock signal X
When the logical levels of CK and the inverted X clock signal XCKB are inverted, the clocked inverter 501 operates in the second shift register unit circuit Ua2,
The output terminal of clocked inverter 502 enters a high impedance state. Therefore, the signal P1 is output from the NOR circuit 5
03a via the third shift register unit circuit Ua3
Supplied to At this time (time T4), the signal P2 becomes L level, so that the output signal N3 of the NAND circuit 506 changes from L level to H level in the third control unit circuit Ub3. Then, the transfer gates 508 and 510 in the third control unit circuit Ub3 are turned on, and the X clock signal XCK and the inverted X clock signal XCK are turned on.
B is supplied to the third shift register unit circuit Ua3.

At time T4, signals N1 and N1
2 is at the H level, so that the X clock signal XCK
And the inverted X clock signal XCKB are the first and second
It is also supplied to the shift register unit circuits Ua1 and Ua2. Therefore, the input capacitance C becomes "3Ca" as shown in FIG. This state is maintained until time T5.

Next, at time T5, X clock signal X
When CK changes from the L level to the H level and the inverted X clock signal XCKB changes from the H level to the L level, the clocked inverter 501 operates while the clocked inverter 502 operates in the first shift register unit circuit Ua1. Is in a high impedance state, the signal voltage at the connection point A is obtained by inverting the logical level of the X transfer start pulse DX. At this time, X
Since the transfer start pulse DX is at L level,
At T5, the signal N1 changes from H level to L level. Thereby, in the first control unit circuit Ub1, the transfer gates 508 and 510 are turned off.

On the other hand, at time T5, the signal P3 in the third shift register unit circuit Ua3 changes from the H level to the L level, so that the fourth control unit circuit outputs the X clock signal XCK and the XCK signal from the time T5. The inverted X clock signal XCKB is supplied to the fourth shift register unit circuit.

Therefore, at time T5, transfer gates 506 and 508 are turned on in the second to fourth control unit circuits. As a result, the input capacitance C becomes "3Ca" as shown in the figure. Thereafter, the shift register unit circuit to which the X clock signal XCK and the inverted X clock signal XCKB are supplied shifts every half cycle of the X clock signal XCK.

As described above, the X shift register 11 described above is used.
According to 0B, each control unit circuit Ub1 to Ubn + 2 corresponds to the X clock signal XCK and the inverted X clock signal XCKB only during the period when the corresponding shift register unit circuits Ua1 to Uan + 2 perform the transfer operation. Since the power supply is supplied to the respective shift register unit circuits Ua1 to Uan + 2, the power consumption can be reduced.

Each shift register unit circuit Ua1-Ua
Since the output signal of an + 2 and the voltages of the connection points A1 to An + 2 are reset every field by the reset signal SINT, each of the control unit circuits Ub1 to Ub1
transfer gates 508 and 51 constituting bn + 2
0 is always off at the start of the field. Here, considering a driving circuit for supplying the X clock signal XCK and the inverted X clock signal XCKB to the clock control circuit 112, the maximum output current of the driving circuit is the maximum number of the transfer gates 508 and 510 that are turned on. Is determined by In this example, since the output signals of the shift register unit circuits Ua1 to Uan + 2 are reset every field by the reset signal SINT, the logic level of the output signal becomes H level when the power is turned on. However, even when the first field starts after the power is turned on, all the voltages at the connection points A1 to An + 2 can be forcibly reset.

Therefore, the drive capability of the drive circuit is sufficient if it can drive up to three clocked inverters. In particular, in a liquid crystal device that displays a high-definition image, the number of data lines 6a increases, and accordingly, the number of control unit circuits also increases. For example, in an XGA type liquid crystal device, since there are 1024 data lines 6a,
If reset is not performed, it is necessary to use a drive circuit that can drive up to 1024 inverters.
In the above-described example, it is sufficient to drive three inverters, so that the circuit configuration of the drive circuit can be significantly reduced and current consumption can be reduced.

Further, since the number of inverters connected to the wiring for supplying X clock signal XCK and inverted X clock signal XCKB in clock control circuit 112 is reduced, the parasitic capacitance of the wiring can be reduced. Therefore, the signal waveforms of the X clock signal XCK and the inverted X clock signal XCKB flowing through the wiring can be sharply changed. As a result, the change in the signal waveform can be made closer to the ideal, the timing deviation is reduced, and high reliability of the shift register operation is ensured.

<2-4: Another Configuration Example of X Shift Register> The X shift register 110B described above has a positive logic in which the reset signal SINT, the X transfer start pulse DX, and the like are active at the H level. Of course, this may be constituted by negative logic. The X shift register 110B ′ corresponding to negative logic can be configured as shown in FIG. This X shift register 110B '
The shift register 11 is used instead of the shift register 111B.
1B ′ and the above-described clock control circuit 112 ′ (FIG. 4 of the first embodiment). The shift register 111B 'is similar to the shift register 111B shown in FIG. 9 except that a NAND circuit 503b is used instead of the NOR circuit 503a. 6 and 7 show the X shift register 1
It is a timing chart which shows operation | movement of 10B '.

<2-5: Configuration Example of Reset Signal Generation Circuit> In this example, a reset signal SINT which becomes active at the start of each field is generated by the timing generation circuit 300, and this is generated by the data line drive circuit 100 and the scanning line. Although the reset signal SINT is supplied to the drive circuit 200, the reset signal SINT may be generated once for a plurality of fields. Alternatively, the power-on time may be detected, the reset signal SINT may be generated based on the detection result, and the reset signal SINT may not be generated at the start of each field. Further, when the power is turned on, the reset signal SI
NT may be generated, and the reset signal SINT may be generated even at the start of each field. In short, the period from power-on to generation of the X clock signal XCK and the inverted X clock signal XCKB, or
Any signal may be used as long as the reset signal SINT is active during the period from when the power is turned on to when the Y clock signal YCK and the inverted Y clock signal YCKB are generated.

Now, an example of a reset signal generation circuit that detects when power is turned on and generates a reset signal SINT based on the detection result will be described. This reset signal generation circuit is configured inside the timing generation circuit 300. FIG. 15 is a circuit diagram of the reset signal generation circuit, and FIG. 16 is a timing chart thereof.

As shown in FIG. 15, a resistor 311 and a capacitor 312 are provided between the high potential power supply VDD and the low potential power supply VSS.
Are connected in series. The connection point of these elements is connected to the input terminal of the inverter 313, and the output signal of the connection is connected to the inverters 314 and 315.
The output signal of the inverter 313 is supplied to one input terminal of the exclusive OR circuit 316 via the other input terminal, and to the other input terminal. Then, the output signal of the exclusive OR circuit 316 is extracted as a reset signal SINT. The threshold voltage of the inverter 313 is Vth
It has become.

In the above configuration, the power supply of the liquid crystal device is turned on, and at time T10, the voltage of the high potential power supply VDD becomes low.
When the level rises from the level to the H level, charging of the capacitor 312 via the resistor 311 is started. After this, the time
At T11, when the charging voltage of the capacitor 312 exceeds the threshold voltage Vth, the output signal of the inverter 313 falls from H level to L level. Since this output signal is delayed by inverters 314 and 315, if the delay time is ΔT, the output signal of inverter 315 is as shown in the figure. As described above, the exclusive OR circuit 316 calculates the exclusive OR of the output signal of the inverter 315 and the output signal of the inverter 313. Therefore, the reset signal SINT is set at the time T as shown in FIG.
At 11, the level rises from the L level to the H level, and the period Δ
After maintaining H level by T, it falls to L level.
In the timing generation circuit 300, the X clock signal XCK or the inverted X clock is used after a predetermined time has elapsed from the reference time with the falling edge of the reset signal SINT falling from the H level to the L level as a reference time. Signal XCKB, Y clock signal YCK and inverted Y
A clock signal YCKB (not shown) is generated.

<3. Application Example><3-1: Configuration of Element Substrate> In each of the above-described embodiments, the element substrate 151 of the liquid crystal panel is formed of a transparent insulating substrate such as glass, and a silicon thin film is formed on the substrate. In addition, the switching element (TFT50) of the pixel and the data line driving circuit 10 are formed by the TFT having the source, the drain and the channel formed on the thin film.
Although the description has been made assuming that 0 and the elements of the scanning line driving circuit 200 are included, the present invention is not limited to this.

For example, the element substrate 151 is formed of a semiconductor substrate, and the switching element of the pixel and the elements of various circuits are formed by the insulated gate field effect transistor having the source, drain and channel formed on the surface of the semiconductor substrate. You may comprise. When the element substrate 151 is formed of a semiconductor substrate as described above, it cannot be used as a transmissive display panel. Therefore, the pixel electrode 9a is formed of aluminum or the like and used as a reflective type. Alternatively, the element substrate 151 may simply be a transparent substrate and the pixel electrode 9a may be of a reflection type.

Further, in the above-described embodiment,
Although the switching element of the pixel has been described as a three-terminal element represented by a TFT, it may be configured with a two-terminal element such as a diode. However, when a two-terminal element is used as the switching element of the pixel, the scanning line 3a is formed on one substrate, the data line 6a is formed on the other substrate, and the two-terminal element is connected to the scanning line 3a or the data line. 6a and the pixel electrode.
In this case, the pixel is composed of a liquid crystal and a two-terminal element connected in series between the scanning line 3a and the data line 6a.

Although the present invention has been described as an active matrix type liquid crystal display device, the present invention is not limited to this.
It is also applicable to a passive type using an N (Super Twisted Nematic) liquid crystal or the like. Further, as the electro-optical material, in addition to the liquid crystal, the present invention can be applied to a display device which uses an electroluminescence element or the like to perform display by the electro-optical effect. That is, the present invention is applicable to all electro-optical devices having a configuration similar to the above-described liquid crystal device.

<3-2: Electronic Apparatus> Next, a case where the above-described liquid crystal device is applied to various electronic apparatuses will be described.

<3-2-1: Projector> First, a projector using this liquid crystal device as a light valve will be described. FIG. 17 is a plan view showing a configuration example of the projector.

As shown in this figure, the projector 1
Inside 100, a lamp unit 1102 composed of a white light source such as a halogen lamp is provided. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and is used as a light valve corresponding to each primary color. Liquid crystal panels 1110R, 1110B and 1110
G is incident.

The configuration of the liquid crystal panels 1110R, 1110B and 1110G is the same as that of the above-described liquid crystal panel.
It is driven by G and B primary color signals, respectively. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112,
The R and B lights are refracted at 90 degrees, while the G light goes straight. Therefore, as a result of combining the images of each color, a color image is projected on a screen or the like via the projection lens 1114.

Here, each liquid crystal panel 1110R, 111
Focusing on the display images by 0B and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally inverted with respect to the display image by the liquid crystal panels 1110R and 1110B.

Note that the liquid crystal panels 1110R, 1110B
And 1110G have a dichroic mirror 1108
Accordingly, light corresponding to each of the primary colors R, G, and B is incident, so that it is not necessary to provide a color filter.

<3-2-2: Mobile Computer>
Next, an example in which the liquid crystal panel is applied to a mobile personal computer will be described. FIG. 18 is a perspective view showing the configuration of this personal computer.
In the figure, a computer 1200 includes a keyboard 12
02 with the liquid crystal display unit 12
06. This liquid crystal display unit 12
Reference numeral 06 is configured by adding a backlight to the back surface of the liquid crystal panel 1005 described above.

<3-2-3: Mobile Phone> Further, an example in which this liquid crystal panel is applied to a mobile phone will be described.
FIG. 19 is a perspective view showing the configuration of the mobile phone. In the figure, a mobile phone 1300 has a plurality of operation buttons 13.
02 and a reflective liquid crystal panel 1005. In this reflection type liquid crystal panel 100,
A front light is provided on the front surface as needed.

In addition to the electronic devices described with reference to FIGS. 17 to 19, a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, Word processor, workstation, videophone, POS terminal,
A device including a touch panel is exemplified. It goes without saying that the present invention can be applied to these various electronic devices.

[0132]

As described above, according to the present invention, the operation margin of the shift register can be expanded, and the shift register can be operated stably. Further, since the shift register can be reset for a predetermined period after the power is turned on, the configuration of a driving circuit for driving the shift register can be simplified, and power consumption can be reduced. Further, the signal waveform of the clock signal can be made sharp.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a liquid crystal device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a detailed configuration of an X shift register 110A of the same device.

FIG. 3 is a timing chart of the X shift register 110A.

FIG. 4 is an X shift register 110 corresponding to negative logic.
It is a circuit diagram of A '.

FIG. 5 is a timing chart of the X shift register 110A ′.

FIG. 6 is a block diagram illustrating a configuration of a scanning line driving circuit 200.

FIG. 7 is a perspective view illustrating the structure of the liquid crystal panel.

FIG. 8 is a partial cross-sectional view illustrating the structure of the liquid crystal panel.

FIG. 9 is a circuit diagram illustrating a detailed configuration of an X shift register 110B used in the liquid crystal device according to the second embodiment.

FIG. 10 is a timing chart showing an operation of the X shift register 110B during a vertical scanning period.

FIG. 11 is a timing chart showing an operation of the X shift register 110B in a first horizontal scanning period after power-on.

FIG. 12 shows an X shift register 110 corresponding to negative logic.
It is a circuit diagram of B '.

FIG. 13 is a timing chart showing an operation of the X shift register 110B ′ during a vertical scanning period.

FIG. 14 is a timing chart showing an operation of the X shift register 110B ′ in a first horizontal scanning period after power is turned on.

FIG. 15 is a circuit diagram showing an example of a reset signal generation circuit 310 used in the first embodiment.

16 is a timing chart showing an operation of the reset signal generation circuit shown in FIG.

FIG. 17 is a cross-sectional view of a video projector as an example of an electronic apparatus to which the liquid crystal device is applied.

FIG. 18 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which the liquid crystal device is applied.

FIG. 19 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the liquid crystal device is applied.

FIG. 20 is a circuit diagram showing a configuration of a conventional shift register.

21 is a timing chart showing the operation of the shift register shown in FIG.

[Explanation of symbols]

3a ... scanning line 6a ... data line 9a ... pixel electrode 50 ... TFT (switching element) SR1-SRn ... sampling pulse D0-D2 ... image data 100 ... data line drive circuit 110 ... X shift register 111A, 111B shift registers (shift means) 112, 112 'clock control circuits (clock signal supply means) 200 scanning line drive circuits 300 timing generator circuits Ua1 to Uan + 2 shift register unit circuits (Shift unit circuit) Ub1 to Ubn + 2 ... Control unit circuit

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat II (reference) G11C 19/00 G11C 19/00 K F term (reference) 2H093 NA16 NA43 NA53 NA64 NC13 NC16 NC21 NC22 NC23 NC26 NC34 ND37 ND39 NE06 NG02 5C006 AF83 BC03 BC12 BF03 BF04 BF26 BF27 EC11 FA43 FA47 5C080 BB05 DD26 JJ02 JJ03 JJ04 JJ06

Claims (14)

[Claims] 1. An electro-optical panel having a plurality of scanning lines, a plurality of data lines, and pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines. A shift register for sequentially generating a selection signal for selecting the data line or the scanning line by sequentially shifting a start pulse, wherein the first clock signal and the inverted first clock signal are used. A shift means cascading a plurality of shift unit circuits for sequentially shifting the start pulse based on two clock signals and outputting an output signal; and a plurality of control unit circuits respectively provided corresponding to each of the shift unit circuits The shift unit circuit, wherein the output signal of the preceding stage is supplied to an input terminal, and the shift unit circuit receives the first clock signal. While operates only I blanking period, a first inverter to an output terminal at its non-active period in a high impedance state, the output signal of the shift unit circuit is supplied to the input terminal,
A second inverter that operates only during an active period of the second clock signal, sets an output terminal in a high impedance state during the inactive period, and connects the output terminal to an output terminal of the first inverter; A third inverter in which a connection point between the inverter and the second inverter is connected to an input terminal, and an input terminal of the second inverter is connected to an output terminal; The clock signal and the inverted clock signal are supplied to the corresponding shift unit circuit only during a period during which one of the signal voltage at the connection point and the signal voltage at the connection point in the preceding shift unit circuit is active. A shift register, characterized in that: 2. An electro-optical panel having a plurality of scanning lines, a plurality of data lines, and pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines. A shift register for sequentially generating a selection signal for selecting the data line or the scanning line by sequentially shifting a start pulse, wherein the first clock signal and the inverted first clock signal are used. A shift means cascading a plurality of shift unit circuits for sequentially shifting the start pulse based on two clock signals and outputting an output signal; and a plurality of control unit circuits respectively provided corresponding to each of the shift unit circuits The shift unit circuit, wherein the output signal of the preceding stage is supplied to an input terminal, and the shift unit circuit receives the first clock signal. While operates only I blanking period, a first inverter to an output terminal at its non-active period in a high impedance state, the output signal of the shift unit circuit is supplied to the input terminal,
The second inverter operates only during the active period of the second clock signal, while the output terminal is in a high impedance state during the inactive period, and the output terminal is connected to the output terminal of the first inverter; A reset signal is supplied to a terminal, the other input terminal is connected to a connection point between the first inverter and the second inverter, and during a non-active period of the reset signal, a signal voltage at the connection point is inverted to form the 2
A logic circuit that supplies the output signal of the shift unit circuit to the input terminal of the inverter and outputs the output signal as an output signal of the shift unit circuit, and resets the output signal of the shift unit circuit during the active period of the reset signal. The clock signal and the inverted clock signal correspond only to a period during which one of the signal voltage at the connection point in the shift unit circuit to be activated and the signal voltage at the connection point in the preceding shift unit circuit is active. A shift register for supplying to a shift unit circuit. 3. The start pulse becomes active at an H level, and the control unit circuit outputs the first clock signal and the inverted clock signal based on an output signal of the NAND circuit and the NAND circuit. First and second transfer gates respectively supplying to the two inverters, a third transfer gate supplying a logic voltage to deactivate the first inverter when the first transfer gate is in a high impedance state, 3. The shift register according to claim 1, further comprising: a fourth transfer gate that supplies a logic voltage to activate the second inverter when the second transfer gate is in a high impedance state. 4. The control unit circuit according to claim 1, wherein the start pulse becomes active at L level, and the control unit circuit outputs the first clock signal and the inverted clock signal based on an output signal of the NOR circuit and the NOR circuit. First and second transfer gates respectively supplying to the two inverters, a third transfer gate supplying a logic voltage to deactivate the first inverter when the first transfer gate is in a high impedance state, 3. The shift register according to claim 1, further comprising: a fourth transfer gate that supplies a logic voltage to activate the second inverter when the second transfer gate is in a high impedance state. 5. The shift register according to claim 2, wherein the reset signal becomes active at an H level, and the logic circuit is a NOR circuit. 6. The shift register according to claim 2, wherein the reset signal becomes active at an L level, and the logic circuit is a NAND circuit. 7. A shift register according to claim 1, wherein input image data is latched based on the selection signal output from the shift register, and the latched input image is latched. A data line drive circuit that converts data from a digital signal to an analog signal and supplies it to each data line. 8. A shift register according to claim 1, wherein an input image signal is sampled based on the selection signal output from the shift register, and the shift register is sampled based on a sampling result. A data line drive circuit that drives each data line. 9. A scanning line drive circuit comprising: the shift register according to claim 1; and driving each of the scanning lines based on the selection signal output from the shift register. 10. The control method of a shift register according to claim 2, wherein the reset signal is activated for every one field or every plural fields. 11. The method of controlling a shift register according to claim 2, wherein the reset signal is a part of the shift register during a period from when a power supply voltage is supplied to the shift register to when the clock signal is supplied. , A method for controlling a shift register, wherein the method is at least active. 12. A plurality of scanning lines, a plurality of data lines,
A pixel region having pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines, a data line driving circuit according to claim 7 or 8, An electro-optical panel, comprising: a scanning line driving circuit for driving. 13. A plurality of scanning lines, a plurality of data lines,
10. A pixel region having pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines, and a data line driving circuit for driving the data lines. An electro-optical panel comprising: the scanning line driving circuit according to any one of the preceding claims. 14. An electronic apparatus comprising the electro-optical panel according to claim 12.