JP2002162942A - Driving method of optoelectronic device, driving circuit of optoelectronic device, optoelectronic device and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the memory capacity required and the power consumption in the case of using an optoelectronic device such as a subfield driving type liquid crystal display as a display device for various equipment. SOLUTION: First and second latch circuits 1420 and 1430 latch binary signals DS being supplied from a memory not shown by Figure and output them as data signals d1, d2, d3,..., dn for every line of every subfield. The signals d1, d2, d3,..., dn are converted into data signals d1', d2', d3',..., dn' through a potential selecting circuit 1440 and supplied to each pixel. On the other hand, during an interval equivalent to a voltage Va at which transmissivity characteristics of he electrooptical device starts to rise, signals S-on or S-off from a decoder not shown in the figure are supplied to the circuit 1440. When these signals are supplied, all data signals d1', d2', d3',..., dn' are set to an H or an L level regardless of the contents of the signals DS, Thus, no need exits to provide a memory region corresponding to the interval and power consumption required to access the memory is also reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method of an electro-optical device suitable for driving an electro-optical device, a driving circuit of the electro-optical device, an electro-optical device, and an electronic apparatus.

[0002]

2. Description of the Related Art An electro-optical device, for example, a liquid crystal display device using liquid crystal as an electro-optical material is a cathode ray tube (CRT).
It is widely used as a display device in place of a display unit of various information processing equipment and a liquid crystal television. Here, the conventional electro-optical device is configured as follows, for example. That is, in a conventional electro-optical device, a pixel electrode arranged in a matrix and a TFT (Thin Film Transistor) connected to the pixel electrode are used.
And a counter substrate on which a counter electrode facing the pixel electrode is formed, and a liquid crystal as an electro-optical material filled between the two substrates.

In such a configuration, when a scanning signal is applied to a switching element via a scanning line, the switching element becomes conductive. In this conductive state, when an image signal of a voltage corresponding to the gradation is applied to the pixel electrode via the data line, a charge corresponding to the voltage of the image signal is applied to the liquid crystal layer between the pixel electrode and the counter electrode. Stored. After the charge storage, even if the switching element is turned off, the charge storage in the liquid crystal layer is maintained by the capacitance of the liquid crystal layer itself, the storage capacitance, and the like. As described above, when the switching elements are driven and the amount of charge to be stored is controlled according to the gradation, the alignment state of the liquid crystal changes for each pixel, so that the density changes for each pixel. Therefore, it is possible to perform gradation display.

[0004] At this time, it is sufficient to accumulate electric charges in the liquid crystal layer of each pixel during a part of the period. First, each scanning line is sequentially selected by a scanning line driving circuit, and secondly,
In the scanning line selection period, the data lines are sequentially selected by the data line driving circuit, and thirdly, the selected data lines are sampled with an image signal of a voltage corresponding to a gray scale. Time-division multiplex driving in which a line is shared by a plurality of pixels becomes possible.

[0005] However, the image signal applied to the data line is a voltage corresponding to a gradation, that is, an analog signal. For this reason, the peripheral circuit of the electro-optical device includes D / A
Since a conversion circuit and an operational amplifier are required, the cost of the entire apparatus is increased. In addition, these D /
Display unevenness occurs due to the non-uniformity of characteristics such as A conversion circuit and operational amplifier and various wiring resistances.
There is a problem that high quality display is extremely difficult,
This is particularly noticeable when performing high-definition display. further,
In an electro-optic material such as a liquid crystal, the relationship between the applied voltage and the transmittance differs depending on the type of the electro-optic material. For this reason, a general-purpose circuit that can cope with various electro-optical devices is desired as a drive circuit for driving the electro-optical device.

[0006]

SUMMARY OF THE INVENTION Under the circumstances described above,
The present applicant has proposed a technique in which one frame is divided into a plurality of subfields, and each pixel is turned on / off for each subfield (patent application dated Sep. 27, 1999, reference number J0075192, unpublished). ). According to this technique, the applied voltage when the pixel is turned on / off in each subfield is constant regardless of the gradation, and the duty ratio (or the effective voltage value) at which the pixel is turned on in one frame. Determines the gradation of the pixel.

Here, when observing the gradation of the electro-optical device while changing the duty ratio between 0% and 100%, it is found that the duty ratio changes near 0% or 100%. Regardless, there is a region where the gradation does not change. The manner in which this region occurs varies depending on the composition of the liquid crystal, but may occur only at a duty ratio of around 0%, only around 100%, or both. Accordingly, there is a period in which pixels are always set to ON or OFF irrespective of the designated gradation, corresponding to these regions where the gradation does not change. The period during which the pixel is always on is V_on
A period that is always turned off is called a V_off period.

In the technique of the above-mentioned patent application, the on / off state of each pixel in each subfield is stored in a field memory as binary data of "1" or "0".
The on / off state of each pixel is controlled based on the data. The same applies to the V_on period and the V_off period, and the on / off state of each pixel during the V_on and V_off periods is also stored in the field memory.

However, as described above, during the V_on period, the pixel is always in the ON state, so that the corresponding data in the field memory always becomes one of "1" or "0", similarly corresponding to the V_off period. The data was always the other of "1" or "0". Storing and reading known data in the field memory in this way is a waste of storage capacity of the field memory, and wasteful power is consumed for memory access and the like. The present invention has been made in view of the above circumstances, and provides a driving method of an electro-optical device, a driving circuit of an electro-optical device, an electro-optical device, and an electronic apparatus that can reduce a required storage capacity and reduce power consumption. It is intended to be.

[0010]

Means for Solving the Problems In order to solve the above problems, the present invention is characterized by having the following configuration. Note that the contents in parentheses are examples. The driving method of the electro-optical device according to the present invention is a driving method of an electro-optical device for displaying a plurality of pixels arranged in a matrix in a gray scale. Storing on or off of each pixel in a memory for each field;
Setting a turn-on or turn-off state of each pixel for each of the plurality of subfields according to the contents of the memory during a first period occupying a part of a frame; Setting the all pixels to the on or off state based on a predetermined timing signal regardless of the contents of the memory during the period 2. Further, in the above driving method, the pixel is provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and when a scanning signal is supplied to the scanning line, the pixel is applied to the data line. The scanning signal is sequentially supplied to each of the scanning lines for each of the sub-fields in the first period, and is turned on or off according to the gradation of each pixel. A signal indicating OFF is supplied to each data line corresponding to each pixel based on the contents of the memory,
In the second period, the scanning signal is sequentially supplied to each of the scanning lines, and a signal for instructing ON or OFF of a pixel according to a threshold value of a transmittance characteristic with respect to an applied voltage of the electro-optical material is provided. And supplying the data to each data line regardless of the contents of the memory. Note that the second
During the period, a signal for only giving an instruction to turn on the pixel may be made. Further, the second period may include both a period for supplying a signal for instructing turning on of the pixel and a period for supplying a signal for instructing turning off of the pixel. The driving circuit of the electro-optical device according to the present invention includes a plurality of scanning lines (112) and a plurality of data lines (11).
4) and the pixel electrodes (11
8) and a switching element (116) provided for each pixel electrode and provided with a scanning signal to the scanning line to conduct between the data line and the pixel electrode. A drive circuit for an optical device, comprising: a memory (30) for storing an on or off state of each pixel for each of a plurality of subfields in accordance with a gradation of each pixel;
4) and a memory-corresponding control circuit that sets an on or off state of each of the pixels for each of the plurality of subfields according to the contents of the memory during a first period occupying a part of one frame. Latch circuit 1420, second latch circuit 1430), and in a second period, which is another period in the one frame, all pixels are turned on or off based on a predetermined timing signal regardless of the contents of the memory. A memory non-corresponding control circuit (decoders 218 and 219) for setting a state. In addition,
In the second period, a signal for giving only an instruction to turn on the pixel may be made. Further, the second period may include both a period for supplying a signal for instructing turning on of the pixel and a period for supplying a signal for instructing turning off of the pixel. Further, the electro-optical device of the present invention,
A pixel electrode (118) disposed corresponding to each intersection of the plurality of scanning lines (112) and the plurality of data lines (114);
An element substrate (101) provided for each pixel electrode, the element substrate including a switching element for controlling conduction between the data line and the pixel electrode by a scanning signal supplied through the scanning line; A counter substrate (102) having a counter electrode (108) disposed opposite to the substrate, an electro-optic material (liquid crystal 105) sandwiched between the element substrate and the counter substrate, and a sub-divided frame. A scanning line driving circuit (130) for sequentially supplying the scanning signal to each of the scanning lines for each field, and an on or off state of each of the pixels for each of a plurality of sub-fields in accordance with a gradation of each of the pixels. A memory (304) for storing, and in a first period occupying a part of one frame, an on or off state of each pixel for each of the plurality of subfields according to the contents of the memory. The constant memory corresponding control circuit (first latch circuit 1420, the second latch circuit 1430),
In a second period, which is another period in the one frame, a memory non-correspondence control circuit (decoder 218, 219). In the second period,
A signal for giving only an instruction to turn on the pixel may be provided. Further, the second period may include both a period for supplying a signal for instructing turning on of the pixel and a period for supplying a signal for instructing turning off of the pixel. According to another aspect of the invention, there is provided an electronic apparatus including the above-described electro-optical device.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Configuration of Embodiment Next, the configuration of an electro-optical device according to an embodiment of the present invention is shown in FIG.
This will be described with reference to FIG. In the figure, a timing signal generation circuit 200 generates various timing signals and clock signals described below according to a vertical scanning signal Vs, a horizontal scanning signal Hs, and a dot clock signal DCLK supplied from a higher-level device (not shown). Is what you do. First,
The AC conversion signal FR is a signal whose level is inverted every frame. The drive signal LCOM is a signal applied to the counter electrode of the counter substrate, and has a constant voltage (zero voltage) in the present embodiment. The start pulse DY is a pulse signal output first in each subfield, V_on period and V_off period. The clock signal CLY is a signal that defines a horizontal scanning period on the scanning side (Y side). The latch pulse LP is a pulse signal output at the beginning of the horizontal scanning period, and is output when the clock signal CLY transitions in level (ie, rises and falls). The clock signal CLX is a signal that defines a so-called dot clock.

On the other hand, in the display area 101a on the element substrate 101, a plurality of scanning lines 112 are formed in the X (row) direction in the drawing. A plurality of data lines 114 are formed along the Y (column) direction. The pixels 110 are provided corresponding to the intersections of the scanning lines 112 and the data lines 114, and are arranged in a matrix. Here, for convenience of explanation, in the present embodiment, the total number of the scanning lines 112 is m, and the data lines 1
Although the total number of 14 is n (m and n are each an integer of 2 or more), a matrix-type display device having m rows and n columns will be described, but the present invention is not limited to this.

1.1. <Configuration of Pixel> As a specific configuration of the pixel 110, for example, FIG.
Examples shown in (a) are given. In this configuration, the gate of the transistor (MOS type FET) 116 is connected to the scanning line 112, the source is connected to the data line 114, and the drain is connected to the pixel electrode 118, respectively. Further, a liquid crystal 105 serving as an electro-optical material is sandwiched between the pixel electrode 118 and the counter electrode 108 to form a liquid crystal layer. Here, the opposing electrode 108 is a transparent electrode formed on one surface of the opposing substrate so as to actually face the pixel electrode 118 as described later. Further, the pixel electrode 118 and the counter electrode 1
Between 08 and 08, a storage capacitor 119 is formed to prevent leakage of charges stored in the liquid crystal layer. In addition,
In this embodiment, the storage capacitor 119 is formed between the pixel electrode 118 and the counter electrode 108, but may be formed between the pixel electrode 118 and the ground potential GND or between the pixel electrode 118 and the gate line.

Here, in the configuration shown in FIG.
Since only one channel type is used as the transistor 116, an offset voltage is required. However, as shown in FIG. 2B, a P-channel transistor and an N-channel transistor are complementarily combined. With such a configuration, the influence of the offset voltage can be canceled. However, in this complementary configuration, it is necessary to supply mutually exclusive levels as scanning signals, so that the scanning lines 112a, 112
b is required.

1.2. <Start Pulse Generation Circuit> As described above, in the present embodiment, the switching of the subfield, the V_on period, and the V_off period (hereinafter, referred to as “subfields and the like” in this specification) is controlled by the start pulse DY. The start pulse DY is generated inside the timing signal generation circuit 200, and according to the number of gray levels required for the electro-optical device (here, 8 gray levels), as shown in FIG. Is set. First, the start pulse DY rises at the beginning of one frame, and V_on
The period starts.

Next, the start pulse DY within one frame
Rises eight times, and a period from each rising timing to the next rising timing (a period from the last V_off period to the next frame) is a V_on period, subfields Sf1 to Sf7, and a V_off period. The length of each of the subfields Sf1 to Sf7 is “1 field length−V_on
Period-V_off period "is set to almost" 1/7 ",
The value is gradually increased or decreased according to the non-linear characteristics of the electro-optical device.

Next, a block diagram of the start pulse generating circuit 210 for generating the above-mentioned start pulse DY is shown in FIG.
Shown in As shown in FIG.
Reference numeral 10 denotes a counter 211, a comparator 212, a multiplexer 213, a ring counter 214, a D flip-flop 215, an OR circuit 216, and a decoder 21.
8, 219. The counter 211 counts the line clock signal LCLK.
The count value is reset by the 16 output signals. One input terminal of the OR circuit 216 has a line clock signal L at the start of a frame.
A reset signal RSET which becomes H level only during one cycle of CLK is supplied. Therefore,
The count value of the counter 211 is reset at least at the start of a frame.

The comparator 212 compares the count value of the counter 211 with the output data value of the multiplexer 213, and outputs a H-level coincidence signal when they match. The multiplexer 213 has a start pulse DY
, DS7,..., DS7, based on the count result of the ring counter 214 for counting the number of
Selectively outputs D_off. Here, data D_on, DS1,
DS2,..., DS7, D_off correspond to the respective subfields V_on, Sf1, Sf2,..., Sf7, V_off shown in FIG. Here, the length of the data D_on, that is, the V_on period, is determined according to the threshold voltage Vth of the liquid crystal (voltage effective value at which a change in gradation starts to appear with respect to a change in the effective voltage value). It is possible to change.

For example, it may be set in advance for each product type of the electro-optical device, or may be adjusted at the time of shipment in order to compensate for variations in each product. Here, the sum of the data D_on and D_off is constant, and when the value of the data D_on increases or decreases, the value of the data D_off is changed accordingly. In this way, the length of the V_on period can be changed by changing only the data D_on and D_off without changing the data DS1, DS2,..., DS7. If the V_on period is made variable in accordance with the temperature characteristics of the electro-optical device in this manner, the effective value of the voltage applied to the liquid crystal can be changed following the change in the environmental temperature. The displayed gradation and contrast ratio can be kept constant.

The comparator 212 outputs a coincidence signal when the count value of the counter reaches the end of the subfield. This coincidence signal is fed back to the reset terminal of the counter 211 via the OR circuit 216, so that the counter 211 starts counting again from the break of the subfield. Further, the D flip-flop 215 latches the output signal of the OR circuit 216 by the line clock signal LCLK, and generates a start pulse DY. Decoder 218
Is based on the count result of the ring counter 214,
The signal S_on which becomes H level during the V_on period is output. Similarly, the decoder 219 includes the ring counter 214
And outputs a signal S_off that goes to the H level within the V_off period based on the count result.

1.3. <Scanning Line Driving Path> The description returns to FIG. 1 again. The scanning line driving circuit 130 is a so-called Y shift register, transfers a start pulse DY supplied at the beginning of a subfield in accordance with a clock signal CLY, and sends the scanning signals G1, G2, G3 to each of the scanning lines 112. ,..., Gm are sequentially and exclusively supplied.

1.4. <Data Line Driving Circuit> The data line driving circuit 140 sequentially latches n binary signals Ds corresponding to the number of the data lines 114 in a certain horizontal scanning period, and then latches n latched binary signals Ds.
Are applied to the data signals d1 ', d2', d3 ',... Dn' on the corresponding data lines 114 in the next horizontal scanning period.
Are supplied all at once. Here, a specific configuration of the data line driving circuit 140 is as shown in FIG. That is, the data line driving circuit 140 includes an X shift register 1410, a first latch circuit 1420, a second latch circuit 1430, and a potential selection circuit 1440.

The X shift register 1410 transfers the latch pulse LP supplied at the beginning of the horizontal scanning period in accordance with the clock signal CLX, and latches the latch signal S1,
S2, S3,..., Sn are sequentially supplied to the user. Next, the first latch circuit 1420 outputs the binary signal Ds
Are sequentially latched at the falling edges of the latch signals S1, S2, S3,... Sn. Then, the second latch circuit 1430 simultaneously latches each of the binary signals Ds latched by the first latch circuit 1420 at the falling edge of the latch pulse LP, and outputs the result to the data signals d1, d2, d3. , ..., dn. The potential selection circuit 1440 includes an alternating signal FR, signals S_on, S_
off and the data signal d based on the truth table of FIG.
1, d2, d3,... Dn are converted to data signals d1 ′, d2 ′, d3 ′,
.. Dn 'and apply to the data line 114.

1.5. <Data Conversion Circuit> Next, the data conversion circuit 300 will be described. H level or L level according to the gradation for each of the subfields Sf1 to Sf7
In order to write the level, it is necessary to convert the gradation data corresponding to the pixel in some way. The data conversion circuit 300 in FIG. 1 is provided for this purpose.
The detailed configuration will be described with reference to FIG.

The gradation data PD0 to PD2 input to the subfield data generation circuit 302 are converted based on the truth table of FIG. 7A, and are converted in the field memory 304 by a write control signal from the write control circuit 301. Is written as a logical value of "1" or "0" in the memory corresponding to each pixel of each field of "1". Read control circuit 3
Numeral 03 sequentially reads out the output level of each pixel in each subfield by a read control signal in synchronization with the clock signal CLX and outputs it as a binary signal Ds. The determination of which field should be read is made by the counter 30 reset by the output from the edge detection circuit 305 which counts the start pulse DY and detects the change point of the AC signal FR.
The determination is made based on the count value of 6.

As described above, the contents of the field memory 304 are sequentially updated based on the gradation data PD0 to PD2, and the binary signal Ds is continuously generated based on the contents of the field memory 304.

Since the binary signal Ds needs to be output in synchronization with the operation of the scanning line driving circuit 130 and the data line driving circuit 140, the read control circuit 303 defines a horizontal scanning period. The latch pulse LP and the dot clock signal CLX are supplied. Further, as described above, in the data line driving circuit 140, during a certain horizontal scanning period, the first latch circuit 14
20 latches the binary signals dot-sequentially, and in the next horizontal scanning period, the second latch circuit 1430 sets the potential selection circuit 1440 as the data signals d1 ', d2', d3 ',. The read control circuit 303 is configured to supply the data to the data lines 114 at the same time via the scan line driving circuit 130 and the data line driving circuit 140. To read the binary signal Ds.

1.6. <Structure of Liquid Crystal Device> FIGS. 10A and 10B show the structure of the above-mentioned electro-optical device.
This will be described with reference to FIG. Here, FIG. 1A is a plan view showing the configuration of the electro-optical device 100, and FIG.
It is sectional drawing of the AA 'line in (a). As shown in these figures, the electro-optical device 100 includes a pixel electrode 11
8 and the like and a counter electrode 108
The opposing substrate 102 on which is formed is adhered to each other with a constant gap by a sealant 104, and a liquid crystal 105 as an electro-optical material is sandwiched in the gap. Actually, the sealing material 104 has a notch, through which the liquid crystal 10 is cut.
5 is sealed with a sealing material after being sealed, but is omitted in these figures.

Here, the element substrate 101 and the opposing substrate 1
02 is an amorphous substrate such as glass or quartz. And
The pixel electrodes 118 and the like are formed by TFTs formed by depositing a semiconductor thin film on the element substrate 101. That is,
The electro-optical device 100 will be used as a transmission type.

On the element substrate 101, a light-shielding film 106 is provided inside the sealant 104 and outside the display area 101a. In the region where the light-shielding film 106 is formed, the scanning line driving circuit 130 is formed in the region 130a, and the data line driving circuit 140 is formed in the region 140a. That is, the light shielding film 106
Prevents light from entering the drive circuit formed in this region. The light shielding film 106 has a counter electrode 108
At the same time, the driving signal LCOM is applied. For this reason, in the region where the light shielding film 106 is formed,
Since the voltage applied to the liquid crystal layer becomes almost zero, the pixel electrode 1
The display state is the same as the display state of No voltage 18.

In the element substrate 101, a plurality of connection terminals are formed outside the region 140a where the data line driving circuit 140 is formed and separated from the sealing material 104 by a plurality of connection terminals. It is configured to input signals and power. On the other hand, the opposing electrode 108 of the opposing substrate 102 is provided with a conductive material (not shown) provided in at least one of four corners of the substrate bonding portion.
Thus, electrical continuity with the light-shielding film 106 and the connection terminals on the element substrate 101 is achieved. That is, the drive signal LCOM is applied to the light-shielding film 106 via a connection terminal provided on the element substrate 101 and further to the counter electrode 108 via a conductive material.

In addition, depending on the use of the electro-optical device 100, for example, in the case of a direct-view type, first, a color filter arranged in a stripe shape, a mosaic shape, a triangle shape, etc. Second, a light-shielding film (black matrix) made of, for example, a metal material or a resin is provided. In the case of color light modulation, for example, when used as a light valve of a projector described later, no color filter is formed. In the case of a direct-view type, a front light that irradiates the electro-optical device 100 with light from the counter substrate 102 side or a backlight that irradiates the electro-optical device 100 from the element substrate 101 side is provided as necessary. In addition, the element substrate 101 and the counter substrate 10
An alignment film (not shown) rubbed in a predetermined direction is provided on each of the two electrode forming surfaces to define the alignment direction of the liquid crystal molecules in a state where no voltage is applied. And a polarizer (not shown) corresponding to the orientation direction. However, when a polymer-dispersed liquid crystal in which fine particles are dispersed in a polymer is used as the liquid crystal 105, the above-described alignment film and polarizer are not required, and the light use efficiency is increased. This is effective in reducing power consumption.

2. Next, the operation of the electro-optical device according to the above-described embodiment will be described. FIG. 8 is a timing chart for explaining the operation of the electro-optical device. First, the alternating signal FR is a signal whose level is inverted every frame (1f). On the other hand, the start pulse DY is supplied at the start of each subfield.

Here, when the start pulse DY is supplied in one frame (1f) in which the alternating signal FR is at the L level, the scan line driving circuit 130 (see FIG. 1) transfers the start pulse DY according to the clock signal CLY. , Gm are sequentially and exclusively output in the period (t). The period (t) is set to a period shorter than the shortest subfield.

The scanning signals G1, G2, G3,...
Each of the scanning signals G1 corresponding to the first scanning line 112 counted from the top has a pulse width corresponding to a half cycle of the clock signal CLY. , And is output with a delay of at least a half cycle of the clock signal CLY. Therefore, one shot (G0) of the latch pulse LP is supplied to the data line driving circuit 140 from the supply of the start pulse DY to the output of the scanning signal G1.

Therefore, consider the case where one shot (G0) of the latch pulse LP is supplied. First, when one shot (G0) of the latch pulse LP is supplied to the data line driving circuit 140, the data line driving circuit 140 (see FIG. 6) transfers the latch signals S1, S2, S3,…, S
n are sequentially and exclusively output during the horizontal scanning period (1H).
Each of the latch signals S1, S2, S3,..., Sn has a pulse width corresponding to a half cycle of the clock signal CLX.

At this time, the first latch circuit 1 shown in FIG.
420 is a signal to the pixel 110 corresponding to the intersection of the first scanning line 112 counted from the top and the first data line 114 counted from the left at the falling of the latch signal S1.
The value signal Ds is latched, and then, at the falling of the latch signal S2, the first scanning line 112 counted from the top,
The binary signal Ds to the pixel 110 corresponding to the intersection with the second data line 114 counted from the left is latched, and thereafter, similarly, the first scanning line 112 counted from the top and n counted from the left. Pixel 11 corresponding to the intersection with the first data line 114
Latch the binary signal Ds to 0.

As a result, first, in FIG.
2 for one row of pixels corresponding to the intersection with the actual scan line 112
The value signal Ds is point-sequentially latched by the first latch circuit 1420. The data conversion circuit 3
00 outputs the data of each ON / OFF pixel stored for each subfield as a binary signal Ds in accordance with the latch timing of the first latch circuit 1420.

Next, when the clock signal CLY falls and the scanning signal G1 is output, the first scanning line 112 counted from the top in FIG. All the transistors 116 of the corresponding pixel 110 are turned on. On the other hand, the falling edge of the clock signal CLY outputs the latch pulse LP. Then, at the falling timing of the latch pulse LP, the second latch circuit 1430 performs dot-sequential latching by the first latch circuit 1420 in a dot-sequential manner.
The value signal Ds is applied to each of the corresponding data lines 114 via the potential selection circuit 1440 by the data signals d1 ', d2', d.
3 ', ... dn' are supplied all at once. Therefore, in the pixels 110 in the first row counted from the top, the data signal d
Writing of 1 ', d2', d3 ',... Dn' is performed simultaneously.

In parallel with this writing, a binary signal Ds for one row of pixels corresponding to the intersection with the second scanning line 112 from the top in FIG. Is done. Then, the same operation is performed after m
This is repeated until the scanning signal Gm corresponding to the actual scanning line 112 is output. That is, a certain scanning signal Gi (i
Is an integer satisfying 1 ≦ i ≦ m) in one horizontal scanning period (1H), the data signals d1 ′ and d for one row of the pixel 110 corresponding to the i-th scanning cycle 112
.. Dn ′ and the dot-sequential latching of the binary signal Ds for one row of the pixels 110 corresponding to the (i + 1) -th scanning line 112 are performed in parallel. become. The data signal written to the pixel 110 is
The data is held until writing in the next subfield Sf2.

Hereinafter, the same operation is repeated every time the start pulse DY defining the start of the subfield is supplied. Then, the data conversion circuit 300 (see FIG. 1)
Regarding the conversion from the gradation data PD0 to PD2 to the binary signal Ds, the item of the corresponding subfield among the subfields Sf1 to Sf7 is referred to. However, V_on
In the period and the V_off period, regardless of the level of the binary signal Ds, the data signals d1 'and d2 are set to levels corresponding to the signals S_on and S_off based on the truth table of the potential selection circuit 1440 in FIG. , d3 ',... dn' are set.

Next, the voltage applied to the liquid crystal layer in the pixel 110 by performing such an operation will be discussed. FIG. 9 is a timing chart showing the gradation data and the waveform applied to the pixel electrode 118 in the pixel 110. For example, when the alternating signal FR is at the L level, the gradation data PD0 to PD2 of a certain pixel is “000”.
In the case of, as a result of following the conversion contents shown in FIGS. 7A and 7B, the pixel electrode 118 of the relevant pixel has an H level (voltage V1) during the V_on period, as shown in FIG. An L level (zero voltage) is written in the subfield. Here, when the H level is written in the subfield Sf0 as described above, the maximum value of the voltage applied to the liquid crystal layer is V1 and the effective value is Va. Therefore, the transmittance of the pixel is 0% corresponding to the gradation data “000”.

Further, gradation data PD0 to PD of a certain pixel
When “2” is “010”, as a result of following the conversion contents shown in FIGS. 7A and 7B, as shown in FIG. The H level indicates that the other subfields Sf3 to Sf7
, The L level is written. As described above, as the grayscale data PD0 to PD2 becomes higher, the time ratio of being at the H level in one frame (1f) increases, and accordingly, the transmittance of the pixel becomes higher. When the gradation data PD0 to PD2 of a certain pixel is “111”, as a result of following the conversion contents shown in FIGS. 7A and 7B, the pixel electrode 118 of the pixel is shown in FIG. As described above, one frame (1
The H level is written over f). Therefore,
The transmittance of the pixel is 100% corresponding to the gradation data “111”.

On the other hand, even when the alternating signal FR is at the H level, the operation up to the previous stage of the potential selection circuit 1440 is the same as when the alternating signal FR is at the L level.
However, according to FIG. 7 (b), the output potential ds' is set to + V1 when the AC signal FR is at the H level and the signal ds is at the H level, and the signal ds is at the H level when the AC signal FR is at the L level. In this case, the output potential ds' is set to -V1. That is, when the zero potential, which is an intermediate value between the potential + V1 and the potential -V1, is used as a reference for the potential, when the AC signal FR is at the H level, the applied voltage of each night crystal layer is the L level of the AC signal FR. The applied voltage in this case is the one whose polarity is inverted, and has the same absolute value. Therefore, a situation in which a DC component is applied to the liquid crystal layer is avoided, so that deterioration of the liquid crystal 105 is prevented.

According to the electro-optical device according to such an embodiment, one frame (1f) is divided into subfields Sf1 to Sf7 according to the voltage ratio of the gradation characteristic, and each subfield has a pixel. By writing the H level or the L level, the effective voltage value in one frame is controlled. Therefore, the data signals d1 ', d supplied to the data line 114
2 ′, d3 ′,... Dn ′ are only three types of voltage ± V1 and zero voltage. Therefore, in a peripheral circuit such as a drive circuit, a circuit for processing an analog signal, such as a high-precision D / A conversion circuit or an operational amplifier, becomes unnecessary.
Therefore, the circuit configuration is greatly simplified, and the cost of the entire device can be reduced. Further, the data signals d1 ', d2', d supplied to the data line 114
Since there are three types of 3 ′,... Dn ′, display unevenness due to non-uniformity such as element characteristics and wiring resistance does not occur in principle. Therefore, according to the electro-optical device according to the present embodiment, high-quality and high-definition gradation display can be performed.

In this embodiment, a V_on period for turning on the pixel regardless of the gradation is assigned to one frame, and the length of the V_on period can be adjusted by the voltage Va at which the transmittance characteristic of the liquid crystal starts to rise. Thus, the invention can be applied to an electro-optical device using various liquid crystals, and the versatility of the device can be expanded.

In particular, in the present embodiment, the signals S_on and S_off are generated in the start pulse generation circuit 210, and the signals S_on and S_off are generated in the potential selection circuit 1440.
Since the data signals d1 ', d2', d3 ',... dn' for the V_on and V_off periods are output to the data line 114 based on the off and the alternating signal FR, the field memory 304 There is no need to store any data. For this reason, the memory capacity of the field memory 304 can be reduced, and the power required for data access can be reduced.

3. Specific examples of electronic device 3.1. <Projector> Next, some examples in which the above-described electro-optical device is used in specific electronic devices will be described. First, a projector using the electro-optical device according to the embodiment as a light valve will be described. FIG. 11 is a plan view showing the configuration of this projector. As shown in this figure, inside the projector 1100, a polarized light illuminating device 1110 is arranged along the system optical axis PL. In the polarized light illuminating device 1110, light emitted from the lamp 1112 is reflected by the reflector 1114 to become a substantially parallel light flux, and enters the first integrator lens 1120. As a result, the light emitted from the lamp 1112 is split into a plurality of intermediate light beams. This split intermediate beam is
The polarization conversion element 1130 having the second integrator lens on the light incident side converts the light into one type of polarized light beam (s-polarized light beam) having a substantially uniform polarization direction, and emits it from the polarized light illuminating device 1110.

Now, the s-polarized light beam emitted from the polarized light illuminating device 1110 is reflected by the s-polarized light beam reflecting surface 1141 of the polarizing beam splitter 1140. Of this reflected light beam, the light beam of blue light (B) is reflected by the blue light reflecting layer of the dichroic mirror 1151, and is modulated by the reflection-type electro-optical device 100B. Further, among the light beams transmitted through the blue light reflecting layer of the dichroic mirror 1151, the light beam of red light (R) is the dichroic mirror 11
The light is reflected by the red light reflection layer 52 and is modulated by the reflection-type electro-optical device 100R. On the other hand, of the light flux transmitted through the blue light reflecting layer of the dichroic mirror 1151,
The luminous flux of the green light (G) passes through a dichroic mirror 1152
Of the reflection type electro-optical device 10
Modulated by 0G.

Thus, the electro-optical device 100R,
The red, green, and blue lights, each of which has been color-modulated by 100G and 100B, are output to a dichroic mirror 115.
2, 1151, and sequentially synthesized by the polarization beam splitter 1140, and then projected on the screen 1170 by the projection optical system 1160. The dichroic mirrors 1151 and 1152 attach R, G, and E to the electro-optical devices 100R, 100B, and 100G.
Since a light beam corresponding to each primary color of B enters, no color filter is required.

3.2. <Mobile Computer> Next, an example in which the electro-optical device is applied to a mobile personal computer will be described. FIG.
FIG. 2 is a front view illustrating a configuration of the personal computer. In the figure, a mobile computer 1200 is:
It comprises a main body 1204 having a keyboard 1202 and a display unit 1206. The display unit 1206 is configured by adding a front light to the front surface of the electro-optical device 100 described above.
In this configuration, since the electro-optical device 100 is used as a reflection direct-view type, it is preferable that the pixel electrode 118 has a configuration in which unevenness is formed so that reflected light is scattered in various directions.

3.3. <Cellular Phone> Further, an example in which the electro-optical device is applied to a cellular phone will be described. FIG. 13 is a perspective view showing the configuration of the portable electronic magazine. In the figure, a mobile phone 1300 is
In addition to a plurality of operation buttons 1302, the electro-optical device 100 is provided together with an earpiece 1304 and a mouthpiece 1306. The electro-optical device 100 is also provided with a front light on its front surface as needed. Also, in this configuration, since the electro-optical device 100 is used as a reflection direct-view type, a configuration in which unevenness is formed on the pixel electrode 118 is desirable.

3.4. <Others> In addition to the electronic devices described above, in addition to those described above, LCD televisions, viewfinders, video tape recorders of the direct-view monitor type, car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, video phones, Examples include a POS terminal, a device equipped with a touch panel, and the like. It goes without saying that the above-described electro-optical device can be applied to these various electronic devices.

4. Modifications The present invention is not limited to the embodiments described above,
For example, various modifications are possible as follows. (1) In the above-described embodiment, the level of the AC signal FR is inverted at a cycle of one frame. However, the present invention is not limited to this. For example, the level is inverted at a cycle of two frames or more. It is good also as composition.

(2) In the above embodiment, the counter electrode 10
Although the drive signal LCOM applied to the pixel 8 is a zero voltage, the voltage applied to each pixel may shift depending on the characteristics of the transistor 116, the storage capacitor 119, the capacity of the liquid crystal, and the like. In such a case, the level of the drive signal LCOM applied to the counter electrode 108 may be shifted according to the amount of voltage shift.

(3) In the above embodiment, the element substrate 101 constituting the electro-optical device is an amorphous substrate such as glass or quartz.
Although T was formed, the present invention is not limited to this. For example, when the element substrate 101 is formed of an opaque semiconductor substrate, the pixel electrode 118 is formed of a reflective metal such as aluminum, and the counter substrate 102 is formed of glass or the like, the electro-optical device 100 can be used as a reflection type. .

(4) Further, in the above embodiment, an example in which the present invention is applied to an electro-optical device using a liquid crystal has been described. Other electro-optical devices, in particular, binary display of ON or OFF is performed. The present invention can be applied to all electro-optical devices that perform gradation display using pixels. As such an electro-optical device, an electroluminescent device, a plasma display, or the like can be considered. In particular, in the case of an organic EL, there is no need to perform AC driving like a liquid crystal, and there is no need to perform polarity inversion.

(5) In the above embodiment, an adjustment knob is provided so that the adjustment of the data D_on for defining the length of the V_on period is left to the user, and the user operates the adjustment knob to change the value of the data D_on. You may make it variable. In addition, the temperature of the liquid crystal display device or the temperature around the liquid crystal display device may be detected by a temperature sensor, and the value of the data D_on may be varied according to the temperature characteristics of the liquid crystal based on the detected temperature.

Here, since the sum of the data D_on and D_off is constant, when increasing or decreasing the value of the data D_on, it is preferable to change the value of the data D_off accordingly. By doing so, it is possible to change only the data D_on and D_off and change the length of the V_on and V_off periods without changing the data DS1, DS2,..., DS7.
If the V_on and V_off periods are made variable in accordance with the temperature characteristics of the liquid crystal in this manner, the effective value of the voltage applied to the liquid crystal can be changed following the change in the environmental temperature. The displayed gradation and contrast ratio can be kept constant.

[0060]

As described above, according to the present invention, 1
In the second period in the frame, all pixels are set to the ON or OFF state based on a predetermined timing signal regardless of the contents of the memory, so that the required storage capacity of the memory can be reduced and power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an electrical configuration of an electro-optical device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a pixel in the embodiment.

FIG. 3 is a timing chart of a start pulse DY at each gradation number in the embodiment.

FIG. 4 is a data conversion circuit 300 according to the embodiment.
It is a block diagram of.

FIG. 5 is a block diagram of a start pulse generation circuit 210 in the embodiment.

FIG. 6 shows a data line driving circuit 14 in the embodiment.
0 is a block diagram of FIG.

FIG. 7 is a diagram showing conversion contents of gradation data in the data conversion circuit 300 and the potential selection circuit 1440 of the embodiment.

FIG. 8 is a timing chart of the electro-optical device according to the embodiment.

FIG. 9 is a timing chart showing a relationship between gradation data and a waveform applied to a pixel electrode 118 in the embodiment.

FIG. 10 is a structural diagram of the electro-optical device in the embodiment.

FIG. 11 is a diagram illustrating a configuration of a projector 1100 as an example of an electronic apparatus to which the electro-optical device is applied.

FIG. 12 is a front view of a mobile computer 1200 as an example of an electronic apparatus to which the electro-optical device is applied.

FIG. 13 is a perspective view of a mobile phone 1300 as an example of an electronic apparatus to which the electro-optical device is applied.

[Explanation of symbols]

100, 100R, 100G, 100B ... electro-optical device 101 ... element substrate 101a ... display area 102 ... counter substrate 105 ... liquid crystal 106 ... light shielding film 108 ... counter electrode 110 ... pixel 112 ... scanning line 114 Data line 116 Transistor 118 Pixel electrode 130 Scan line drive circuit 140 Data line drive circuit 200 Timing signal generation circuit 210 Start pulse generation circuit 211 Counter 212 Comparator 213 Multiplexer 214 Ring counter 215 D flip-flop 216 OR circuit 218, 219 Decoder 300 Data conversion circuit 301 Write control circuit 302 Write latch circuit 303 Read control circuit 304 …… Field memory 1100 … Projector 1110… Polarized illumination device 1112… Lamp 1114… Reflector 1120… First integrator lens 1130… Polarization conversion element 1140… Polarized beam splitter 1141… s-polarized light beam reflecting surface 1151… dichroic mirror 1152 dichroic mirror 1160 projection optical system 1170 screen 1200 mobile computer 1202 keyboard 1204 main body 1206 display unit 1300 mobile phone 1302 operation buttons 1304 reception Mouth 1306 mouthpiece 1420 first latch circuit 1430 second latch circuit 1440 potential selection circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme court ゛ (Reference) G09G 3/20 641 G09G 3/20 641E 641A (72) Inventor Akihiko Ito 3-3 Yamato, Suwa City, Nagano Prefecture No. 5 Seiko Epson Corporation (72) Inventor Ryo Ishii 3-3-5 Yamato, Suwa-shi, Nagano F-term in Seiko Epson Corporation (reference) 2H093 NA16 NA31 NA51 NC03 NC09 NC16 NC22 NC24 NC26 NC29 NC34 ND06 ND09 ND10 NE04 NE06 5C006 AA14 AF04 AF54 AF71 BB11 BC03 BC13 BC16 BF02 EC05 EC11 EC13 FA16 FA44 FA47 5C080 AA10 BB05 DD26 DD30 EE25 JJ02 JJ04 JJ06 KK02 KK07 KK43

Claims (11)

[Claims] 1. A method of driving an electro-optical device for displaying a plurality of pixels arranged in a matrix in a gray scale, wherein the method comprises the steps of: Storing on or off in a memory; and setting an on or off state of each of the pixels for each of the plurality of subfields according to the contents of the memory during a first period occupying a part of one frame. Setting a pixel to an on or off state based on a predetermined timing signal, regardless of the contents of the memory, in a second period, which is another period in the one frame. Driving method of the electro-optical device. 2. The pixel is provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and when a scanning signal is supplied to the scanning line, a voltage applied to the data line is provided. In the first period, for each of the sub-fields,
The scanning signal is sequentially supplied to each of the scanning lines, and a signal for instructing ON or OFF in accordance with the gradation of each pixel is supplied to each data line corresponding to each pixel based on the contents of the memory. In the second period, the scanning signal is sequentially supplied to each of the scanning lines, and a pixel is turned on or off in accordance with a threshold value of a transmittance characteristic with respect to a voltage applied to the electro-optical material. Signal
2. The method according to claim 1, wherein the data is supplied to each data line regardless of the contents of the memory. 3. The apparatus according to claim 1, wherein in the second period, a signal for only giving an instruction to turn on the pixel is supplied.
Or the driving method of the electro-optical device according to 2. 4. The apparatus according to claim 1, wherein the second period includes both a period for supplying a signal for instructing turning on of the pixel and a period for supplying a signal for instructing turning off of the pixel. 3. The method for driving an electro-optical device according to claim 1 or 2. 5. A pixel electrode provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and a pixel electrode provided for each pixel electrode, wherein a scanning signal is supplied to the scanning line. A driving circuit of an electro-optical device that drives a pixel including a switching element that conducts between the data line and the pixel electrode, wherein each of a plurality of subfields corresponds to a gradation of the pixel. A memory for storing an on or off state of a pixel; and an on or off state of each pixel is set for each of the plurality of subfields according to the contents of the memory during a first period occupying a part of one frame. A memory correspondence control circuit, wherein in a second period, which is another period in the one frame, all pixels are set to an on or off state based on a predetermined timing signal regardless of the contents of the memory. And a non-memory-compatible control circuit. 6. The apparatus according to claim 3, wherein during the second period, a signal for instructing only the turning on of the pixel is supplied.
A driving circuit for the electro-optical device according to claim 1. 7. The second period includes both a period for supplying a signal for instructing the pixel to be turned on and a period for supplying a signal for instructing the pixel to be turned off. 4. A driving circuit of the electro-optical device according to 3. 8. A pixel electrode provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and a scanning signal provided for each pixel electrode and supplied through the scanning line. An element substrate including a switching element that controls conduction between the data line and the pixel electrode; an opposing substrate including an opposing electrode disposed to oppose the pixel electrode; and the element substrate and the opposing substrate. An electro-optical material, a scanning line driving circuit for sequentially supplying the scanning signal to each of the scanning lines for each subfield obtained by dividing one frame, and a plurality of A memory for storing the ON or OFF state of each pixel for each subfield; and a pixel for each of the plurality of subfields according to the contents of the memory during a first period occupying a part of one frame. A memory-corresponding control circuit for setting an on or off state; and, in a second period, which is another period in the one frame, turning on or off all pixels based on a predetermined timing signal regardless of the contents of the memory. An electro-optical device, comprising: a memory non-corresponding control circuit for setting a state. 9. The apparatus according to claim 8, wherein during the second period, a signal for instructing ON of the pixel is supplied.
An electro-optical device according to claim 1. 10. The apparatus according to claim 1, wherein the second period includes both a period for supplying a signal for instructing turning on of the pixel and a period for supplying a signal for instructing turning off of the pixel. 9. The electro-optical device according to 8. 11. An electronic apparatus comprising the electro-optical device according to claim 8.