JP2002287141A - Light emission controlling device, optoelectronic device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain uniform luminance at a low cost in a back light or the like of a liquid crystal display device. SOLUTION: Blue LEDs 124, 126, 128 are used as the light source and driven by pulses. The duty ratio of the driving signals is increased or decreased according to the illuminance of the environment and slightly controlled according to the individual difference of the blue LEDs 124, 126, 128. A phosphor film 121 consisting of a YAG phosphor is applied between a color filter 120 and a propagation path 122 of light. Thereby, the yellow light emitted from the fluorescent film 121 and the blue light transmitting through the phosphor film 121 are synthesized to emit white light to the color filter 120.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a light emission control device, an electro-optical device, and an electronic apparatus suitable for displaying various information.

[0002]

2. Description of the Related Art Electro-optical devices, for example, liquid crystal display devices using liquid crystal as an electro-optical material, are widely used as display devices in place of cathode ray tubes (CRTs) for display sections of various information processing equipment and liquid crystal televisions. I have. Here, the conventional electro-optical device is configured as follows, for example. That is, a conventional electro-optical device includes an element substrate provided with pixel electrodes arranged in a matrix and a switching element such as a TFT (Thin Film Transistor) connected to the pixel electrodes;
A counter substrate on which a counter electrode facing the pixel electrode is formed,
A liquid crystal, which is an electro-optical material, is filled between these two substrates.

In such a configuration, when a scanning signal is applied to a switching element via a scanning line, the switching element becomes conductive. In this conductive state, when an image signal of a voltage corresponding to the gradation is applied to the pixel electrode via the data line, a charge corresponding to the voltage of the image signal is applied to the liquid crystal layer between the pixel electrode and the counter electrode. Stored. After the charge storage, even if the switching element is turned off, the charge storage in the liquid crystal layer is maintained by the capacitance of the pixel electrode and the counter electrode, the storage capacitance, and the like. As described above, when each switching element is driven and the amount of charge to be stored is controlled in accordance with the gradation, light is modulated for each pixel to change the displayed density. Therefore, it is possible to display gradation.

At this time, it is sufficient that the electric charge is stored in the electrode of each pixel in a part of the period for displaying one screen, and firstly, each scanning is performed by the scanning line driving circuit. Secondly, the data lines are sequentially selected by the data line driving circuit during the scanning line selection period, and thirdly, the selected data line has an image of a voltage corresponding to the gradation. With the configuration to sample the signal,
Time-division multiplex driving in which a scanning line and a data line are shared by a plurality of pixels is possible.

Since the liquid crystal display device does not emit light by itself,
There is known a method in which a liquid crystal display device is configured to be a reflection type and a front light is irradiated from the front. However, when the liquid crystal display device is used for displaying a color image, a structure in which the liquid crystal display device is configured to be of a transmission type and a backlight is irradiated from the back is common. This is because color display can be easily performed by adding a color filter to the liquid crystal display device.

In recent years, white LEDs have been frequently used as backlights for small electronic devices such as mobile phones. White LED
Are provided, for example, on the rear side of the liquid crystal display device in accordance with the size of the display surface of the liquid crystal display device. The plurality of white LEDs are connected in series, and a power supply voltage is applied to the series circuit. The reason why the white LEDs are connected in series is to minimize the luminance difference by setting the current flowing through them to a constant value.

[0007]

However, there is an individual difference between white LEDs, and there is a difference in emission color and emission efficiency for each LED. Further, there is a property that the emission color changes depending on the ambient temperature. Therefore, conventionally, it is necessary to visually select LEDs having similar characteristics as those used in the same electronic device. Such an operation is complicated and has led to an increase in cost. Further, there is a problem that the white LED has a low luminous efficiency, and the cost is higher than that of the LED of another color in order to obtain a desired luminance. The present invention has been made in view of the circumstances described above, and has as its object to provide a light emission control device, an electro-optical device, and an electronic device that can achieve uniform luminance at low cost with respect to a backlight or the like of a liquid crystal display device. And

[0008]

Means for Solving the Problems In order to solve the above problems, the present invention is characterized by having the following constitution. Note that the contents in parentheses are examples. In the configuration according to claim 1, the first to n-th (n is an integer of 2 or more) light-emitting elements (blue LEDs 124, 126, and 128) and the first light-emitting element
A first to an n-th switching element (transistor 13
4, 136, 138) and the first to n-th control signals having different phases to the first to n-th switching elements so that the first to n-th light-emitting elements are periodically turned on. And a timing control circuit (LED control unit 139) for adjusting the on / off duty ratio in the first to nth control signals so as to average the luminance of the first to nth light emitting elements. It is characterized by doing. Further, in the configuration according to the second aspect, the main body (element substrate 101, liquid crystal 105, counter substrate 102) for setting the light transmittance for each part according to the information to be displayed.
And a light source (blue LEDs 124, 126, 128, light propagation path 12) for emitting light of a predetermined color to one surface of the main body.
2) and a fluorescent film (121) that covers the one surface of the main body and emits a complementary color when the light of the predetermined color is emitted. Further, in the configuration according to claim 3, in the electro-optical device according to claim 2,
The light source is a blue light emitting diode, and the phosphor film is Y
It is an AG phosphor. According to a fourth aspect of the invention, there is provided a light emission control device according to the first aspect. According to a fifth aspect of the present invention, there is provided the electro-optical device according to the second or third aspect.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Configuration of Embodiment Next, the configuration of an electro-optical device according to an embodiment of the present invention is shown in FIG.
This will be described with reference to FIG. In the figure, a timing signal generation circuit 200 receives a vertical synchronization signal V from a higher-level device (not shown).
s, horizontal synchronizing signal Hs, and input gradation data D0 to D2
Is supplied. Further, the oscillation circuit 150 outputs the basic clock R of the read timing.
CLK is supplied to the timing signal generation circuit 200. The timing signal generation circuit 200 generates various timing signals and clock signals described below in accordance with these signals. First, the AC signal FR
Is a signal whose polarity is inverted every frame.

The drive signal LCOM is a signal applied to the counter electrode of the counter substrate, and has a constant potential (zero potential) in the present embodiment. In the present embodiment, 1
A frame is divided into a plurality of sub-fields SF0 to SF3, and a pixel is turned on / off for each sub-field, whereby gradation display is performed. The start pulse DY is a pulse signal output first in each subfield. The clock signal CLY is a signal that defines a horizontal scanning period on the scanning side (Y side). The latch pulse LP is a pulse signal output at the beginning of the horizontal scanning period, and is output when the clock signal CLY transitions in level (ie, rises and falls). The clock signal CLX is a dot clock signal for display.

Here, the outline of the subfield driving will be described with reference to the waveform of the start pulse DY in FIG. First, a subfield SF0 is provided at the beginning of a frame. The length of the subfield is set to a length at which the transmittance of the liquid crystal rises from 0% (in the case of normally black). That is, when the effective value of the voltage applied to the pixel is gradually increased from zero voltage, the transmittance does not change at first, but the transmittance increases according to the effective value from when a certain threshold voltage Vth is reached. I will be.
The length of giving the threshold voltage Vth within one frame is set to the length of the subfield SF0.

Further, subfields SF1, SF2, S
F3 is set to a length having a weight corresponding to each bit of the input gradation data D0 to D2. That is,
The sub-field SF1 corresponds to the grayscale data D0 which is the least significant bit.
It is set to a length that causes a change in transmittance corresponding to 0 on / off. The subfields SF2 and SF3 are also set to a length that causes a change in transmittance corresponding to the on / off of the grayscale data D1 and D2 due to the on / off of each. That is, the subfields SF2 and SF3 are about twice and four times as long as the subfield SF1, respectively.

Returning to FIG. 1, a plurality of scanning lines 112 are formed in the display area 101a on the element substrate 101 so as to extend in the X (row) direction in the drawing. Also, a plurality of data lines 114 are formed extending along the Y (column) direction. Then, the pixel 110 has a scanning line 112.
And the data lines 114 are provided corresponding to the respective intersections, and are arranged in a matrix. Here, the total number of the scanning lines 112 is m, and the total number of the data lines 114 is n (m and n are each an integer of 2 or more).

1.1. <Configuration of Pixel> As a specific configuration of the pixel 110, for example, FIG.
Examples shown in (a) are given. In this configuration, the gate of the thin film transistor (TFT) 116 is connected to the scanning line 11.
2, the source is connected to the data line 114, and the drain is connected to the pixel electrode 118, respectively.
Liquid crystal 10 which is an electro-optical material between
5 are sandwiched to form a liquid crystal layer. Here, the counter electrode 108 is a transparent electrode formed on one surface of the counter substrate so as to face the pixel electrode 118. In addition, a storage capacitor 119 is formed in parallel with the pixel electrode 118 and the counter electrode 108 to reduce the influence on the display due to the leakage of charge from the pixel electrode 118. Note that, in this embodiment, one potential of the storage capacitor 119 is applied to the counter electrode 108.
However, the potential may be the same as the ground potential GND or the potential of the gate line.

Here, in the configuration shown in FIG.
Since only one of the channel types is used as the transistor 116, an offset voltage is required. However, as shown in FIG. 2B, a P-channel transistor and an N-channel transistor are complementarily combined. With such a configuration, the influence of the offset voltage can be canceled. However, in this complementary configuration, it is necessary to supply mutually exclusive levels as scanning signals, so that the scanning lines 112a, 112
Two scanning lines b are required.

1.2. <Scanning Line Driving Circuit 130> The description returns to FIG. The scanning line driving circuit 130 transfers the start pulse DY supplied at the beginning of the subfield in accordance with the clock signal CLY, and supplies the scanning lines 112 exclusively and sequentially as the scanning signals G1, G2, G3,..., Gm. Is what you do.

1.3. <Data Conversion Circuit 300> The data conversion circuit 300 is provided with a dot clock signal DCLK.
Is converted into a binary signal Ds synchronized with the clock signal CLX and output. Here, the detailed configuration of the data conversion circuit 300 will be described with reference to FIG. In the figure, 320, 32
Reference numerals 1 and 322 denote memory blocks, each of which has gradation data D
0, D1 and D2 are provided, and the element substrate 1
Each has a memory space of m × n bits corresponding to 01 display areas (m rows × n columns).

Memory blocks 320, 321, 322
Are configured to execute the write and read operations asynchronously and independently. Reference numeral 310 denotes a write address control unit, which includes a vertical synchronization signal Vs and a horizontal synchronization signal H.
The write enable signal WE and the write address WAD are supplied to the memory blocks 320, 321, 322 in synchronization with the dot clock signal DCLK.

That is, the write address control section 310 counts up the dot clock signal DCLK, outputs the count result as a write address WAD, and outputs a write enable signal WE every time the value of the write address WAD is determined. The count result in the write address control unit 310 is reset every time the vertical synchronization signal Vs is input. As a result, each memory block 320, 321, 322 has its m ×
A write address WAD for sequentially accessing the n-bit memory space is supplied, and the gradation data D0 to D2 are sequentially stored at addresses corresponding to the display positions of the corresponding memory blocks.

When each subfield period is started, display address control section 330 outputs an address signal RAD for accessing bit data of a corresponding display row. The address signal RAD is incremented “n−1” times in accordance with the number of display columns in synchronization with the clock signal CLX. As a result, an address signal RAD for sequentially accessing the bits in the first to n-th columns for the corresponding display row is output. Also, the read signal RD0 is set in the subfield S
During F1, it is always enabled. However, the read signals RD1 and RD2 are always turned off in the subfield SF1. Thereby, the memory block 32
Only 0 is in a readable state, and the other memory blocks are in a read prohibited state. Then, the memory block 32
From 0, the grayscale data D0 of the least significant bit of the grayscale data in the first to nth columns of the corresponding display row is read.

The read signal RD1 is always enabled during the subfield SF2. However, the read signals RD0 and RD2 are always turned off in the subfield SF2. As a result, only the memory block 321 is accessed, and
The bit gradation data D1 is read. Similarly, the read signal RD2 is always enabled during the subfield SF3. However, the read signals RD0 and RD1 are always turned off in the subfield SF3. As a result, only the memory block 322 is accessed, and the grayscale data D2 of the most significant bit is read.
When the subfield SF0 starts, the ON signal S_on is fixed at the H level during the period of n cycles of the clock signal CLX. Then, the OR circuit 332 outputs the logical sum of the gradation data D0, D1, D2 and the ON signal S_on as a binary signal Ds.

1.4. <Data Line Driving Circuit 140> Next, the data line driving circuit 140 sequentially latches n binary signals Ds corresponding to the number of data lines 114 in a certain horizontal scanning period, and then latches n latched binary signals. Ds
In the next horizontal scanning period.
Are simultaneously supplied to the corresponding data lines 114 as data signals d1, d2, d3,... Dn. Here, a specific configuration of the data line driving circuit 140 is as shown in FIG. That is, the data line driving circuit 140 includes an X shift register 1410, a first latch circuit 1420, a second latch circuit 1430,
And a potential selection circuit 1440.

The X shift register 1410 transfers the latch pulse LP supplied at the beginning of the horizontal scanning period in accordance with the clock signal CLX, and latches the latch signal S1,
S2, S3,..., Sn are sequentially and exclusively supplied. Next, the first latch circuit 1420 outputs the binary signal Ds
Are sequentially latched at the falling edges of the latch signals S1, S2, S3,..., Sn. Then, the second latch circuit 1430 simultaneously latches each of the binary signals Ds latched by the first latch circuit 1420 at the falling edge of the latch pulse LP, and the potential selection circuit 1440
Transfer to

The potential selection circuit 1440 receives the AC signal FR
, And converts these latched binary signals into potentials, and applies them to the data lines 114 as data signals d1, d2, d3,..., Dn. That is, the AC signal F
If R is at L level, data signals d1, d2, d3,...
The H level of dn is converted to a potential V1, and the L level is converted to zero potential. On the other hand, if the AC signal FR is at the H level, the H level of the data signals d1, d2, d3,.
The L level is converted to zero potential.

1.5. <Structure of Liquid Crystal Device> The structure of the above-described electro-optical device will be described with reference to FIGS. 6 (a) and 6 (b). Here, FIG. 1A is a plan view showing the configuration of the electro-optical device 100, and FIG.
FIG. 3 is a sectional view taken along line AA ′ in FIG. As shown in these drawings, in the electro-optical device 100, an element substrate 101 on which a pixel electrode 118 and the like are formed, and a counter substrate 102 on which a counter electrode 108 and the like are formed,
4, the bonding is performed while maintaining a constant gap, and a liquid crystal 105 as an electro-optical material is sandwiched in the gap. In addition, actually, the sealing material 1
04 has a cutout portion, and after the liquid crystal 105 is sealed through the cutout portion, it is sealed with a sealing material, but is omitted in these drawings. Here, the element substrate 101 and the counter substrate 102 are amorphous substrates such as glass and quartz. The pixel electrodes 118 and the like are formed by TFTs formed by depositing a semiconductor thin film on the element substrate 101. That is, the electro-optical device 100 is used as a transmission type.

On the element substrate 101, a light-shielding film 106 is provided inside the sealant 104 and outside the display area 101a. In the region where the light-shielding film 106 is formed, the scanning line driving circuit 130 is formed in the region 130a, and the data line driving circuit 140 is formed in the region 140a. That is, the light shielding film 106
Prevents light from entering the drive circuit formed in this region. The light shielding film 106 has a counter electrode 108
At the same time, the driving signal LCOM is applied. For this reason, in the region where the light shielding film 106 is formed,
Since the voltage applied to the liquid crystal layer becomes almost zero, the pixel electrode 1
The display state is the same as the display state of No voltage 18.

In the element substrate 101, a plurality of connection terminals are formed outside the region 140a where the data line drive circuit 140 is formed and in the region 107 separated by the sealant 104, so that control from outside can be performed. It is configured to input signals and power. On the other hand, the opposing electrode 108 of the opposing substrate 102 is provided with a conductive material (not shown) provided in at least one of four corners of the substrate bonding portion.
Thus, electrical continuity with the light-shielding film 106 and the connection terminals on the element substrate 101 is achieved. That is, the drive signal LCOM is applied to the light-shielding film 106 via a connection terminal provided on the element substrate 101 and further to the counter electrode 108 via a conductive material.

Next, in FIG. 2B, reference numeral 120 denotes a color filter, which is fixed to the lower surface of the element substrate 101 at a portion corresponding to the display area 101a and has a stripe shape or the like.
It is composed of filter elements of each primary color (R, G, B) arranged in a mosaic shape, a triangle shape or the like. Reference numeral 121 denotes a fluorescent film, which is formed by applying a YAG fluorescent material to the lower surface of the color filter 120. Reference numeral 122 denotes a rectangular plate-shaped light propagation path, which is fixed to the lower surface of the fluorescent film 121. 124, 126, 12
Reference numeral 8 denotes a blue LED.
2 buried in the upper part.

In addition, the element substrate 101 and the opposing substrate 1
An alignment film (not shown) rubbed in a predetermined direction is provided on the electrode forming surface of No. 02 to define the alignment direction of the liquid crystal molecules when no voltage is applied.
A polarizing plate (not shown) corresponding to the orientation direction is provided on the element substrate 101 and the counter substrate 102. However, the liquid crystal 10
As 5, the use of a polymer-dispersed liquid crystal dispersed as fine particles in a polymer eliminates the need for the above-mentioned alignment film and polarizer, resulting in an increase in light use efficiency, resulting in higher brightness and lower power consumption. It is effective in terms of conversion.

1.6. <Configuration of LED Driving Unit> Next, the configuration of a driving unit that drives the blue LEDs 124, 126, and 128 will be described with reference to FIG. 13 in the figure
Reference numerals 4, 136, and 138 denote transistors, each of which has a source terminal connected to each of the cathode terminals of the blue LEDs 124, 126, and 128. These transistors and a series circuit including the transistors are connected in parallel, and a predetermined power supply voltage is applied from a power supply 133 to the parallel circuit.

Reference numeral 132 denotes an optical sensor that measures ambient illuminance. 131 is a ROM, which is a blue LED 124, 1
The difference in luminance when the power supply voltage is applied to 26 and 128 is stored. The contents of the ROM 131 are set when the product is shipped. 139 is an LED control unit, which is shown in FIG.
And generating drive signals Pa, Pb, Pc as shown in (c),
The voltage is applied to the gate terminals of the transistors 134, 136, and 138. These transistors 134, 136, 138
Are turned on when the corresponding drive signals Pa, Pb, Pc are at H level, and turned off when they are at L level. As a result, the time-averaged luminance of the blue LEDs 124, 126, and 128 is determined according to the duty ratio of the drive signals Pa, Pb, and Pc.

In the LED control section 139, the driving signals Pa, Pa,
The duty ratio of Pb, Pc is set. That is, when the surrounding illuminance is low, the duty ratio is set low as shown in FIG.
The duty ratio is set high as shown in FIG. this is,
When the surroundings are bright, the backlight must be brightened, but when the surroundings are dark, the power consumption of the backlight is reduced.

In the LED control section 139, the drive signals Pa, Pb, Pc are changed in accordance with the luminance difference stored in the ROM 131 so that the time-averaged luminance of each of the blue LEDs 124, 126, 128 becomes a constant value. The duty ratio is increased or decreased little by little. In other words, the rising timings of the drive signals Pa, Pb, Pc are shifted by “2π / 3”, but the falling timings are blue LEDs 124, 12.
It will be set according to 6,128 individual differences. As a result, it is possible to prevent flicker due to fluctuations in the luminance of the backlight.

2. Next, the operation of the electro-optical device according to the above-described embodiment will be described. FIG. 7 is a timing chart for explaining the operation of the electro-optical device. First, the alternating signal FR is a signal whose polarity is inverted every frame (1F). On the other hand, the start pulse DY is supplied at the start of each subfield.

Here, when the start pulse DY is supplied in one frame (1F) in which the alternating signal FR is at the L level, the scan line driving circuit 130 (see FIG. 1) transfers the start pulse DY according to the clock signal CLY. , Gm are sequentially and exclusively output in the period (t). The period (t) is set to a period shorter than the shortest subfield SF1.

The scanning signals G1, G2, G3,..., Gm are
Each of the scanning signals G1 corresponding to the first scanning line 112 counted from the top has a pulse width corresponding to a half cycle of the clock signal CLY. , And is output with a delay of at least a half cycle of the clock signal CLY. Therefore, one shot (G0) of the latch pulse LP is supplied to the data line driving circuit 140 from the supply of the start pulse DY to the output of the scanning signal G1.

Therefore, consider the case where one shot (G0) of the latch pulse LP is supplied. First, when one shot (G0) of the latch pulse LP is supplied to the data line driving circuit 140, the data lines driving circuit 140 (see FIG. 4) transfers the latch signals S1, S2, S3,…, S
n are sequentially and exclusively output during the horizontal scanning period (1H).
Each of the latch signals S1, S2, S3,..., Sn has a pulse width corresponding to a half cycle of the clock signal CLX.

At this time, the first latch circuit 1 shown in FIG.
420 latches the binary signal Ds to the pixel 110 corresponding to the intersection of the first scanning line 112 counted from the top and the first data line 114 counted from the left at the falling of the latch signal S1. Next, at the falling of the latch signal S2, the first scanning line 112 counted from the top,
The binary signal Ds to the pixel 110 corresponding to the intersection with the second data line 114 counted from the left is latched, and thereafter, similarly, the first scanning line 112 counted from the top and n counted from the left. Pixel 11 corresponding to the intersection with the first data line 114
Latch the binary signal Ds to 0.

As a result, first, in FIG.
The binary signal Ds for one row of pixels corresponding to the intersection with the actual scanning line 112 is latched dot-sequentially by the first latch circuit 1420. The data conversion circuit 3
In the case of 00, it goes without saying that the grayscale data D0 to D2 of each pixel is converted into a binary signal Ds and output in accordance with the latch timing of the first latch circuit 1420.

Next, when the clock signal CLY falls and the scanning signal G1 is output, the first scanning line 112 counted from the top in FIG. All the transistors 116 of the corresponding pixel 110 are turned on. On the other hand, the falling edge of the clock signal CLY outputs the latch pulse LP. Then, at the falling timing of the latch pulse LP, the second latch circuit 1430 responds to the binary signal Ds, which is point-sequentially latched by the first latch circuit 1420, via the potential selection circuit 1440. Data signals d1, d2, d3,
..., dn are supplied all at once. Therefore, in the pixels 110 in the first row counted from the top, the data signals d1, d2,
The writing of d3,..., dn is performed simultaneously.

In parallel with this writing, the binary signal Ds for one row of pixels corresponding to the intersection with the second scanning line 112 from the top in FIG. Latched. Then, the same operation is repeated until the scanning signal Gm corresponding to the m-th scanning line 112 is output. That is, a certain scanning signal Gi (i
Is an integer satisfying 1 ≦ i ≦ m) in one horizontal scanning period (1H), the data signals d1, d2, and d for one row of the pixel 110 corresponding to the i-th scanning line 112 are output.
Writing of d3,..., dn and the (i + 1) th scanning line 112
Are performed in parallel with the point-sequential latching of the binary signal Ds for one row of the pixels 110 corresponding to. Note that the data signal written to the pixel 110 is held until writing in the next subfield Sf2.

Thereafter, the same operation is repeated every time the start pulse DY defining the start of the subfield is supplied. However, in the subfield SF0, the level of the binary signal Ds is always at the H level. Further, even after the lapse of one frame, the same operation is repeated in each subfield even when AC signal FR is inverted to the H level.

On the other hand, in the LED control section 139, the illuminance detected by the optical sensor 132 and the ROM 131
The duty ratios of the drive signals Pa, Pb, and Pc are set according to the luminance difference stored in the blue LED, and the blue LEDs 124, 126, and 128 are turned on and off as shown in FIGS. 9B and 9C. . The blue light emitted from the blue LEDs 124, 126, 128 is emitted to the fluorescent film 121 via the light propagation path 122. A part of the irradiated blue light is absorbed by the fluorescent film 121, that is, the YAG phosphor, and yellow light is emitted from the part. On the other hand, the unabsorbed blue light passes through the fluorescent film 121 and is emitted to the color filter 120.

The color filter 120 emits blue light and yellow light. Since both colors have complementary colors, they are combined into white light. As a result, the R, G, and B primary colors are changed to the color filter 120, the liquid crystal 105, and the counter substrate 1 respectively.
02 will be emitted.

3. Specific examples of electronic device 3.1. <Mobile Computer> Next, some examples in which the above-described electro-optical device is used in specific electronic devices will be described. First, an example in which the electro-optical device is applied to a mobile personal computer will be described. FIG. 8A is a front view showing the configuration of this personal computer. In the figure, a mobile computer 5200 includes a keyboard 5202
And a display unit 5206. This display unit 5206 is configured by the electro-optical device 100 described above.

3.2. <Cellular Phone> Next, an example in which the electro-optical device is applied to a cellular phone will be described. FIG. 8B is a perspective view showing the configuration of the mobile phone. In the figure, the mobile phone 5300
Is a plurality of operation buttons 5302 and an earpiece 530
4. The electro-optical device 100 is provided as a display device together with the mouthpiece 5306.

3.3. <Others> In addition to the electronic devices described above, in addition to those described above, LCD televisions, viewfinders, video tape recorders of the direct-view monitor type, car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, video phones, Examples include a POS terminal, a device equipped with a touch panel, and the like. It goes without saying that the above-described electro-optical device can be applied to these various electronic devices.

4. Modifications The present invention is not limited to the embodiments described above,
For example, various modifications are possible as follows. (1) In the embodiment described above, the light source is blue L
White light was synthesized by using the EDs 124, 126, and 128 and using a YAG phosphor that emits yellow light as the fluorescent film 121. However, the combination of the complementary colors is not limited to the blue light and the yellow light, and the light source and the fluorescent film 121 can use any emission color that forms the complementary color. The blue LED 12
A white LED may be used instead of 4, 126, 128. In such a case, the fluorescent film 121 itself can be omitted.

[0049]

As described above, according to the present invention, the on / off duty ratio of the first to n-th control signals is set to the first value.
To adjust the luminance of the n-th light emitting element to average,
Alternatively, since a fluorescent film that emits a light complementary to the emission color of the light source is provided, uniform luminance can be realized at low cost with respect to a backlight or the like of a liquid crystal display device.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an electrical configuration of an electro-optical device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a pixel in the embodiment.

FIG. 3 is a data conversion circuit 300 according to the embodiment.
It is a block diagram of.

FIG. 4 is a data line drive circuit 14 according to the embodiment.
0 is a block diagram of FIG.

FIG. 5 is a diagram showing a relationship between gradation data and a waveform applied to a pixel electrode 118 in the embodiment.

FIG. 6 is a structural diagram of the electro-optical device according to the embodiment.

FIG. 7 is a timing chart of the electro-optical device according to the embodiment.

FIG. 8 is a diagram illustrating examples of various electronic apparatuses to which the electro-optical device is applied.

FIG. 9 is a block diagram and a drive waveform diagram of a drive unit that drives the LEDs 124, 126, and 128.

[Explanation of symbols]

100 electro-optical device 101 element substrate (main body) 101a display area 102 counter substrate (main body) 104 sealing material 105 liquid crystal (main body) 106 light-shielding film 107 Region 108 Counter electrode 110 Pixel 112 Scan line 114 Data line 116 Thin film transistor 118 Pixel electrode 119 Storage capacitance 120 Color filter 121 Fluorescent film 122 Light propagation path (Light source) 124, 126, 128 Blue LED (light emitting element, light source) 130 Scanning line drive circuit 131 ROM 132 Optical sensor 133 Power supply 134, 136, 138 Transistor (switching element) 139 LED control unit (timing control circuit) 140 Data line drive circuit 150 Oscillation circuit 200 Mining signal generation circuit 300 Data conversion circuit 310 Write address control section 320, 321, 322 Memory block 330 Display address control section 332 OR circuit 1410 Shift register 1420 First latch Circuit 1430 Second latch circuit 1440 Potential selection circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H091 FA02Y FA08X FA08Z FA41Z FA45Z GA01 GA13 LA18 LA30 2H093 NA31 NC22 NC26 NC34 NC42 NC53 ND06 ND09 ND54 NE01 5G435 AA04 BB12 BB15 CC09 CC12 EE23 EE26 EE30 GG23 GG23GG

Claims (5)

[Claims] A first to an n-th light emitting element (n is an integer of 2 or more); a first to an n-th switching element for turning on and off a current supplied to the first to the n-th light emitting element; Supplying first to n-th control signals having different phases to the first to n-th switching elements so that the first to n-th light emitting elements are periodically turned on;
A light emission control device comprising: a timing control circuit that adjusts an on / off duty ratio in the first to n-th control signals so as to average luminance of the first to n-th light-emitting elements. 2. A main body for setting a light transmittance for each portion in accordance with information to be displayed, a light source for emitting light of a predetermined color to one surface of the main body, and An electro-optical device, comprising: a fluorescent film that covers one surface and emits a complementary color when the light of the predetermined color is emitted. 3. The light source is a blue light emitting diode.
The electro-optical device according to claim 2, wherein the fluorescent film is a YAG phosphor. 4. An electronic apparatus comprising the light emission control device according to claim 1. 5. An electronic apparatus comprising the electro-optical device according to claim 2.