JP2002158727A - Reception synchronization method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reception synchronization method that conducts reception synchronization processing that reduces the effect by an offset frequency. SOLUTION: Although the phase of a transition pattern of a preamble after delay detection is rotated by an offset frequency, the feature of repetitive transition between two points is not lost. This method conducts the reception synchronization processing by utilizing the characteristic.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reception synchronization process in a digital radio communication system using a .pi. / 4 shift QPSK modulation system, and more particularly to a high-speed synchronization in which no synchronization is established at the start of communication. It relates to the improvement of the synchronization processing.

[0002]

2. Description of the Related Art A conventional reception synchronization process will be described with reference to FIGS. FIG. 2 is a block diagram showing a configuration of a conventional reception synchronization block. 101 is an in-phase signal (I) input terminal, 102 is a quadrature signal (Q) input terminal, 113 is a root roll-off filter (RROF), 114 is a synchronous word detection unit, 115 is an identification point extraction processing unit, and 116 is a signal storage Section, 117 is an offset frequency (Δf) correction section, 118 is a delay detection section, 119 is a sign determination section, 1
20 is a reception success / failure judgment unit, 201 is a preamble correlation operation unit, 2
02 is a sum of squares calculation unit, 203 is a specified value comparison unit, 204 is a reception synchronization processing timing generation unit, and 205 is an offset frequency (Δf) detection unit. FIG. 9 is a diagram illustrating an example of a synchronous burst pattern.

In FIG. 2, a synchronization burst used for reception synchronization has a configuration shown in FIG. 9, and a preamble portion is a repetition of a signal of bits “1, 0, 0, 1”. The in-phase signal (I) and the quadrature signal (Q) after the quadrature detection of the π / 4 shift QPSK modulation signal are input to the in-phase signal (I) input terminal 1 respectively.
01 and the quadrature signal (Q) input terminal 102 are input. The input in-phase signal (I) and quadrature signal (Q) are both supplied to preamble correlation operation section 201 and RROF 113, respectively. In this conventional example, the signal input interval is set to 1/4 of one symbol, and is hereinafter referred to as one sample.

Here, the preamble correlation operation section 201 will be described with reference to FIG. FIG. 3 is a block diagram showing a configuration of the preamble correlation operation unit 201. 301 is an in-phase signal (I) input terminal, 302 is a quadrature signal (Q) input terminal, 303-1,
303-2, ‥‥‥, 303- (N-1) are 4-sample delay processing unit, 30
4-0, 304-1, ‥‥‥, 304- (N-1) are complex multipliers, 305-1,
305-2, ‥‥‥, and 305- (N-1) are complex adders, 306 is an in-phase signal output terminal, and 307 is a quadrature signal output terminal. Where N
Is a natural number. In FIG. 3, in-phase signal (I) input terminal 30
1 and a quadrature signal (Q) input terminal 302 receive the in-phase signal (I) and the quadrature signal (Q), respectively, and supply them to a 4-sample delay processing unit 303-1 and a complex multiplier 304-0. The complex multiplier 304-0 performs a complex multiplication operation on the input in-phase signal (I) and quadrature signal (Q) with the conjugate complex number P ₀ of the preamble pattern, and outputs the obtained result to the complex adder 305- Give to one. In the 4-sample delay processing section 303-1, the input in-phase signal (I) and quadrature signal (Q)
Are delayed by four samples, respectively, and then the complex multiplier 30
4-1 and the 4-sample delay processing section 303-2. Similarly, multiplication is performed at four sample intervals, the respective results are added, and the obtained result is supplied to the sum of squares calculation unit 202 in FIG. 2 via the in-phase signal output terminal 306 and the quadrature signal output terminal 307. .

[0005] The sum of squares calculation section 202 squares the input in-phase signal (I) and quadrature signal (Q) and then adds the squared signals, and supplies the result to a specified value comparison section 203. The specified value comparison unit 203 compares the input sum of squares of the correlation with the specified value. If the sum of squares of the correlation is larger than the specified value, a preamble is detected as "1". Otherwise, "0" is output. Is output to the reception synchronization timing generator 204. When “1” is input, the reception timing generation unit 204 determines the synchronization word detection section in consideration of the processing delay due to the RROF 114 and the number of symbols up to the synchronization word section. A control signal of “1” is supplied to the synchronization word detection unit 114 in other cases.

[0006] The RROF 113 performs band limiting filter processing, and supplies band-limited signals (in-phase signal and quadrature signal) to the synchronization word detecting unit 114 and the discrimination point extracting unit 115. In accordance with the control signal from the reception synchronization timing generation section 204, the synchronization word detection section 114 performs a correlation operation on the input signal with the synchronization word pattern, obtains the maximum value in the detection section, and obtains the identification point extraction timing. The determined identification point extraction timing is provided to the identification point extraction unit 115. In addition, the synchronization word detection unit 114 provides the offset frequency detection unit 205 and the offset frequency correction unit as information on which position in the signal storage unit 116 the head of the synchronization word is located in. The discrimination point extraction unit 115 extracts a discrimination point based on the timing information from the synchronization word detection unit 114, and provides the information of the extracted discrimination point to the signal storage unit 116.

[0007] The offset frequency detection unit 205 reads the synchronization word from the signal storage unit 116 from the beginning, obtains the offset frequency from the phase change amount in the synchronization word section, and supplies the offset frequency to the offset frequency correction unit 117. The offset frequency correction unit 117 obtains the amount of signal phase correction based on the offset frequency information given from the offset frequency detection unit,
The synchronization word signal in the signal storage unit 116 is corrected, and the phase-corrected in-phase signal (I) and quadrature signal (Q) are supplied to the delay detection unit 118, respectively.

In the delay detection section 118, the input in-phase signal
(I), a quadrature signal (Q), and a conjugate complex number of the in-phase signal (I) and the quadrature signal (Q) input one symbol before, and a complex multiplication operation are performed, and the result is given to the code determination unit 119. The code determination unit 119 determines whether the input in-phase signal (I) and quadrature signal (Q) are positive or negative, obtains bit information, and provides the bit information to the reception success / failure determination unit 120. The reception success / failure determination unit 120 compares the bit pattern of the synchronization word part with the input bit information to determine the number of error bits. If the value is equal to or less than a specified value, the reception is determined to be successful, otherwise, the reception failure is determined. . If the reception is successful, the subsequent processing is performed using the timing information obtained by the processing up to now, and if the reception fails, the processing from the preamble detection processing is repeated again.

Referring to FIG. 4, a preamble transition pattern depending on the presence or absence of an offset frequency will be described. FIG.
FIG. 5 is a diagram showing the preamble transition pattern on the IQ plane when there is no offset frequency (FIG. 4A) and when there is an offset frequency (FIG. 4B). The horizontal axis represents the in-phase signal component I and the vertical axis represents the quadrature signal component Q. Normally, the preamble changes as shown in FIG. 4A, but when an offset frequency exists, the preamble pattern changes and changes as shown in FIG. 4B. In the prior art described above, the transition pattern is detected by performing a correlation operation between the ideal preamble pattern and the input signal.
As shown in FIG. 4B, when the offset frequency exists, the transition position changes, and it is difficult to specify the preamble pattern.

[0010]

In the above-mentioned prior art,
It is difficult to identify a preamble pattern because the transition changes according to the offset frequency because the transition changes according to the offset frequency because the preamble is detected by using the transition for several symbols of the preamble section. There were disadvantages. SUMMARY OF THE INVENTION An object of the present invention is to provide a reception synchronization system that eliminates the above-mentioned disadvantages and performs reception synchronization processing in which the influence of the offset frequency is reduced.

[0011]

In order to achieve the above object, the present invention provides a reception synchronization method in which a preamble portion is a repetition of the same signal in several symbol periods, and an in-phase signal obtained when the preamble portion is subjected to delay detection. Since the transition of the orthogonal signal and the transition of the orthogonal signal repeat the same transition, the phase is rotated by the offset frequency, but the characteristic of repeating the transition between two points is not lost. The reception synchronization process is performed using this. That is, in the reception synchronization method of the present invention, since the transition of the in-phase signal and the transition of the quadrature signal when the preamble part is delayed detected are the same transitions, the reception synchronization method is present even if an offset frequency exists. Even if not, the phase is rotated by the offset frequency,
Using the characteristic of repeating transitions between points, the phase difference between the signal point that outputs this maximum value and the signal point when there is no offset frequency is determined as the offset frequency.

That is, according to the reception synchronization method of the present invention, the received complex baseband signal is subjected to delay detection, the root-mean-square value of the delayed-detected signal is calculated, and the delayed-detected signal is compared with the ideal-state delayed-detection signal pattern. When the calculated mean square value of the correlation value is larger than a predetermined value, the calculated mean square value of the correlation value is compared with the mean square value of the delayed detection signal. The point in time when the root mean square of the value becomes larger than the root mean square of the signal subjected to delay detection is determined as preamble detection. Further, the obtained correlation value is monitored for a certain section, the maximum value of the correlation value is obtained, and the offset frequency is obtained from the in-phase signal component and the quadrature signal component at the time when the maximum value is obtained.

That is, in the method of obtaining the offset frequency in the reception synchronization method of the present invention, the received complex baseband signal is subjected to delay detection, the signal point at which the amplitude of the delayed detection signal has the maximum value is obtained, Signal points that are values,
A phase difference from a signal point when there is no offset frequency is obtained, and an offset frequency is calculated from the obtained phase difference. Still further, in the reception synchronization method of the present invention, the received complex baseband signal is delay-detected, and the delay-detected signal is
The position coordinates of the signal point having the maximum amplitude are obtained, the phase difference between the position coordinates and the signal point when there is no offset frequency is obtained, and the offset frequency is calculated from the obtained phase difference.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a block diagram showing a configuration of a reception synchronization block according to one embodiment of the present invention. Components having the same functions as those described in the related art are denoted by the same reference numerals. In addition, 103 is a preamble detection delay detection processing unit, 104 is a sum of squares average calculation unit, 105 is a multiplier, 106 is a correlation processing unit, 107 is a sum of squares calculation unit, 108 is an average calculation unit, 109
Denotes a determination unit, 110 denotes a reception synchronization processing timing generation unit, 111 denotes a maximum value search unit, and 112 denotes an offset frequency (Δf) detection unit. In FIG. 1, the in-phase signal (I) and the quadrature signal (Q) after quadrature detection of the π / 4 shift QPSK modulation signal are respectively an in-phase signal (I) input terminal 101 and a quadrature signal (Q) input terminal 102. Enter more. The synchronization burst used for the reception synchronization is the same as in FIG. 2 and has the configuration shown in FIG. 9, and the preamble portion is a repetition of a signal of bits “1, 0, 0, 1”.

The input in-phase signal (I) and quadrature signal (Q) are both preamble-detected delay detector 103 and RROF1
13 and given to. In this embodiment, as in the description of the related art, the signal input interval is set to 1/4 interval of one symbol. RR
The OF113 performs band limiting filter processing, and converts the band-limited signals (in-phase signal and quadrature signal) into the synchronous word detection unit 11.
4 and the identification point extraction unit 115.

Here, the preamble detection delay detector 10
3 will be described with reference to FIG. FIG. 6 is a block diagram showing an example of the configuration of the delay detection unit 103 for detecting a preamble. 601 is an in-phase signal (I) input terminal, 602 is a quadrature signal (Q)
An input terminal, 603 is a 4-sample delay processing unit, 604 is a conjugate complex number calculation unit, 605 is a complex multiplication unit, 606 is an in-phase signal output terminal,
Reference numeral 607 denotes a quadrature signal output terminal. In FIG. 6, an in-phase signal (I) input terminal 601 and a quadrature signal (Q) input terminal 602 receive an in-phase signal (I) and a quadrature signal (Q), respectively. This is given to the multiplier 605. At this time, the signal input to the complex multiplier 605 is the current signal. The 4-sample delay processing unit 603 receives the input signal (the in-phase signal (I) and the quadrature signal
(Q)) are delayed by four samples, respectively, and given to the conjugate complex number calculation unit 604. The conjugate complex number calculation unit 604 obtains a conjugate complex number of the input signal and supplies the conjugate complex number to the complex multiplication unit 605. At this time, the signal input to the complex multiplier 605 is a delay signal. The complex multiplication unit 605 performs a complex multiplication of the current signal and the delay signal, and outputs an in-phase component output terminal 606 and a quadrature component output terminal 6.
The processing results (in-phase signal i and quadrature signal q) are shown in FIG.
To the sum-of-squares average calculation unit 104 and the correlation calculation unit 106.

Next, the correlation calculator 106 will be described with reference to FIG. FIG. 7 is a block diagram illustrating a configuration example of the correlation operation unit 106. 701 is an in-phase signal input terminal, 702 is a quadrature signal input terminal, 703-1, 703-2, ‥‥‥, 703- (N-1) are 4-sample delay processing units, 704-0, 704-1, ‥ ‥‥, 704- (N
-1) is a complex multiplication unit, 705-1, 705-2,..., 705- (N-1) are complex addition processing units, 706 is an in-phase component output terminal, and 707 is a quadrature component output terminal. Here, N = 16. The processing operation in FIG. 7 is the same as the correlation operation in FIG. However, in the example of FIG.
The coefficient values multiplied by 4-0, 305-1, ‥‥‥, and 305- (N-1) to the input signal are conjugate complex numbers P ₀ , P ₁ ,
‥‥‥, P _(N−1) , but in FIG. 7 of this embodiment, the input signals are multiplied by complex multipliers 704-0, 704-1, ‥‥‥, 704- (N−1). The coefficient value to be used is an ideal preamble pattern after differential detection.

That is, in FIG. 7, the correlation operation is performed on the input signal and the ideal preamble pattern after differential detection. The ideal preamble pattern after this differential detection is (-
It is represented by repetition of (1, 1) and (1, -1). And
Since the calculation is performed using a conjugate complex number during the correlation calculation, D _M = (−−
1, −1) and D _{M + 1} = (1, 1) (M = 0, 1, ‥‥‥, 7).
Therefore, the complex multiplier 704-0 and 704-1, as the coefficient _{P '0, D 0 = (} - 1, -1), the "-1" is multiplied by each of the input signals, the complex multiplier 704-2 When the 704-3, as the coefficient P _'1,
The input signal is multiplied by “1” of D ₁ = (1, 1), respectively.
Hereinafter, the complex multiplier 704-4 and 704-5, as the coefficient P _'2 and _{P' 3, D 2 = (} - 1, -1), the "-1", a complex multiplier 704-6 and 704
-7, the coefficients P ′ ₄ and P ′ ₅ are “1” of D ₃ = (1, 1), ‥‥‥, and the complex multipliers 704-14 and 704-15
As P _'14 and _{P' 15, D 7 = (} 1,1), the "1" is multiplied by each of the input signals. Processing result of correlation operation (in-phase signal
i ′ and the quadrature signal q ′) are supplied to the sum of squares calculation section 107 and the offset frequency detection section 112 in FIG.

The sum of squares calculation section 107 squares the input signals (in-phase signal i and quadrature signal q) and adds them, and then adds the processing result (= i ′ ² + q ′ ² ) to the average calculation section 108. This is given to the maximum value search unit 111. After performing the averaging process, the average calculation unit 108 provides the averaging process result P to the determination unit 109. The sum-of-squares calculation unit 104 squares the input signals and adds (= i ² + q ² ), further performs averaging processing, and provides the result to the multiplier 105. The multiplier 105 multiplies the constant k,
The multiplication result A is given to the judgment unit 109.

FIG. 8 is a diagram showing an example of a synchronous burst pattern and fluctuations of the correlation value and the comparison value. For example, in the case of the frame configuration as shown in the upper part of FIG. 8 (the same as that in FIG. 9), the averaging result P in the average calculator 108 and the multiplication result A in the multiplier 105 have the values shown in the lower part of FIG. Take. Judgment unit 1
In step 09, the multiplication result A is compared with the specified noise level to determine the no-signal section. If the multiplication result A is equal to or greater than a predetermined value (the specified noise level in FIG. 8), the average processing result P And the multiplication result A. When the average processing result P becomes equal to or larger than the multiplication result A (detection time in FIG. 8), it is determined that the preamble is detected, and the detection information is provided to the reception synchronization timing generation unit 110.

The reception synchronization timing generation section 110 receives the preamble pattern detection information,
For 4, the synchronization word part is considered, and the synchronization word detection timing is determined in consideration of the number of symbols and the processing delay of the RROF113.
In the case of the synchronization word section, a control signal of “1” is provided to the synchronization word detection unit 114 in other cases, and a control signal of “0” is provided. At this time, in consideration of the case where the preamble detection timing is temporally delayed, the synchronous word detection section includes several symbols before and after the synchronous word section. Also, the maximum value search unit 111
And the offset frequency detection unit 112 are provided with timing information so as to operate for several symbol times in the preamble section.

The maximum value search unit 111 compares the maximum value with the current value according to the input timing information. If the current value is larger than the maximum value, the maximum value is stored as the maximum value.
Control information is provided to the offset frequency detection unit 112 so as to store the in-phase and quadrature signals at that time. This operation is performed for several symbol times according to the timing information from the reception synchronization timing section 110. Offset frequency detecting section 112 obtains the offset frequency from the in-phase and quadrature components stored at the time when the maximum value detection ends, and supplies the offset frequency to offset frequency correcting section 117. A method for obtaining the offset frequency will be described with reference to FIG.

FIG. 5 shows a preamble detection delay detection unit 10.
FIG. 3 is a diagram showing a constellation of a preamble transition pattern after delay detection in FIG. FIG. 5A is a constellation when there is no offset frequency (the horizontal axis is the in-phase signal component I and the vertical axis is the quadrature signal component Q), and FIG. 5B is a constellation when there is an offset frequency. (The horizontal axis is the in-phase signal component I and the vertical axis is the quadrature signal component Q). FIG.
In the case where the transition of the in-phase signal and the transition of the quadrature signal when the preamble portion is detected by delay detection are repeated, the same transition is repeated. Although it is rotated by the minute, the feature of repeating the transition between two points is not lost.
The point when this maximum value is output is the point indicated by the black point in FIG. 5B, and the offset frequency can be obtained from the in-phase signal component and the quadrature signal component at that time. If there is no offset frequency, the transition shown in FIG.
As the angle difference Δω (= 2πΔfT) from the transition point at this time,
An offset frequency (f is an offset frequency) can be obtained.

On the other hand, the RROF 113 performs a band limiting filter process, and outputs the result to the synchronization word detection unit 114 and the identification point extraction unit 115. In accordance with the control signal from the reception synchronization timing generation section 110, the synchronization word detection section 114 performs a correlation operation on the input signal with the synchronization word pattern, calculates the maximum value in the detection section, and determines the identification point extraction timing.
The determined identification point extraction timing is provided to the identification point extraction unit 115. Further, the position of the head of the synchronization word in the signal storage unit 116 is given to the offset frequency correction unit 117.
The discrimination point extraction unit 115 extracts a discrimination point based on the timing information from the synchronization word detection unit 114 and supplies the discrimination point to the signal storage unit 116. The offset frequency correction unit 117 obtains the phase correction amount of the signal from the offset frequency information from the offset frequency detection unit 112, corrects the offset frequency of the synchronization word signal in the signal storage unit 116, and provides the same to the delay detection unit 118 . The delay detection unit 118 performs a multiplication operation on the conjugate complex number of the input signal and the signal one symbol before, and supplies the result to the sign determination unit 119. The sign determination unit 119 determines whether the input signal is positive or negative, obtains bit information, and provides the bit information to the reception success / failure determination unit 120. The reception success / failure determination unit 120 compares the bit pattern of the synchronization word part with the input bit information to determine the number of error bits. If the value is equal to or less than a specified value, the reception is determined to be successful, otherwise, the reception failure is determined. . If the reception is successful, the subsequent processing is performed using the timing information obtained by the processing up to now, and if the reception fails, the processing from the preamble detection processing is repeated again.

[0025]

As described above, the reception synchronization method according to the present invention makes it possible to reduce the undetection or erroneous detection of the preamble portion due to the phase error caused by the offset frequency, and realize the reception synchronization. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a reception synchronization block according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional reception synchronization block.

FIG. 3 is a block diagram illustrating a configuration example of a preamble correlation operation unit.

FIG. 4 is a diagram of a preamble transition pattern with and without an offset frequency.

FIG. 5 is a diagram showing a preamble transition pattern after differential detection.

FIG. 6 is a block diagram showing a configuration example of a preamble detection delay detection unit.

FIG. 7 is a block diagram showing a configuration example of a correlation operation unit 106.

FIG. 8 is a diagram showing an example of a synchronous burst pattern and a correlation value and a comparison value change.

FIG. 9 is a diagram showing an example of a synchronous burst pattern.

[Explanation of symbols]

101: In-phase signal (I) input terminal, 102: Quadrature signal (Q) input terminal, 103: Preamble detection delay detection processing unit, 10
4: Mean-square calculator, 105: Multiplier, 106: Correlation processor, 107: Sum-of-squares calculator, 108: Average calculator, 10
9: determination unit, 110: reception synchronization processing timing generation unit,
111: maximum value search unit, 112: offset frequency (Δf) detection unit, 113: root roll-off filter (RROF), 11
4: Sync word detector, 115: Identification point extraction processor, 11
6: signal storage unit, 117: offset frequency (Δf) correction unit, 118: delay detection unit, 119: sign determination unit, 120:
Receiving success / failure judgment section, 201: Preamble correlation operation section, 2
02: sum of squares calculation unit, 203: specified value comparison unit, 204: reception synchronization processing timing generation unit, 205: offset frequency
(Δf) detector, 301: In-phase signal (I) input terminal, 302: Quadrature signal (Q) input terminal, 303-1, 303-2, ‥‥‥, 303- (N-
1): 4-sample delay processing unit, 304-0, 304-1, ‥‥‥,
304- (N-1): complex multiplier, 305-1, 305-2, ‥‥‥, 305
-(N-1): Complex adder, 306: In-phase signal output terminal, 30
7: Quadrature signal output terminal, 601: In-phase signal (I) input terminal,
602: Quadrature signal (Q) input terminal, 603: 4-sample delay processing unit, 604: Conjugate complex number calculation unit, 605: Complex multiplication unit, 606: In-phase signal output terminal, 607: Quadrature signal output terminal, 701: In-phase Signal input terminal, 702: Quadrature signal input terminal, 703-1, 703-2, ‥‥‥, 703- (N-1): 4-sample delay processing unit, 704-0, 704-1, ‥‥‥, 704 -(N-1): Complex multiplier, 705-1, 705-2, ‥‥‥, 705- (N-1): Complex addition processor, 706: In-phase component output terminal, 707: Quadrature component output terminal.

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Claims (4)

[Claims] 1. A method for delay-detecting a received complex baseband signal, calculating a root-mean-square value of the delayed-detected signal, and calculating a correlation value between the delayed-detected signal and a signal pattern after differential detection in an ideal state. When the calculated mean square value of the correlation value is greater than a predetermined value, the calculated mean square value of the correlation value is compared with the mean square value of the differentially detected signal. A reception synchronization method, wherein a point in time when the root mean square value becomes larger than the root mean square value of the differentially detected signal is determined as preamble detection. 2. The reception synchronization method according to claim 1, wherein the obtained correlation value is monitored for a predetermined interval, a maximum value of the correlation value is obtained, and the in-phase signal component and the quadrature at the time point having the obtained maximum value are obtained. A reception synchronization method, wherein an offset frequency is obtained from a signal component. 3. The reception synchronization method according to claim 2,
The method of determining the offset frequency includes delay-detecting the received complex baseband signal, determining a signal point having the maximum amplitude for the delay-detected signal, a signal point having the maximum amplitude, and an offset frequency. A method for obtaining a phase difference from a signal point when there is no signal, and calculating an offset frequency from the obtained phase difference. 4. A delay detection of the received complex baseband signal, and for the delay-detected signal, a position coordinate of a signal point having a maximum amplitude is obtained, and the position coordinate and a signal point when there is no offset frequency are obtained. A reception synchronization method comprising: calculating a phase difference of the above; and calculating an offset frequency from the obtained phase difference.