JPH11150573A - Digital demodulator and digital demodulation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the processing time and the cost while maintaining discrimination capability against input preamble signal. SOLUTION: A signal outputted from a correlation section 14 is subjected to delay-sum processing at a delay-sum section 16. A threshold level detection section 18 of a next stage determines the possibility of burst signal having been inputted, based on the output of the delay-sum section 16. If the threshold level detection section 18 determines that the possibility is very high, clock synchronization is determined, based on a computation result of the delay-sum section 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital demodulator and a digital demodulation method, and more particularly, to a digital demodulator and a digital demodulation method for performing clock synchronization in wireless communication such as mobile communication and satellite communication.

[0002]

2. Description of the Related Art Conventionally, in radio communication such as mobile communication and satellite communication, TDMA (Time Division Multiple Acces
s) The method is widely used. In particular, a random access wireless packet communication is often used for control at the time of outgoing call or incoming call. In wireless packet communication using such a TDMA system or a random access system, it is necessary to supplement data sent in a burst at a high speed and to achieve high-speed synchronization using a timing synchronization signal included in the supplemented data. Was. In general, a configuration example of a frame used in these TDMA systems is as shown in FIG. That is, at the beginning of the frame,
For synchronization, a preamble composed of a sequence of binary characters is arranged. Subsequently, a UW (Unique Word) for indicating the beginning of the data and clarifying the attribute of the burst is arranged, and thereafter the data is arranged. Conventionally, such burst capture and clock synchronization are performed as shown in FIG.
A digital demodulator 50 as shown in FIG.

FIG. 7 shows a conventional digital demodulator 50.
First, the received signal is subjected to delay detection processing by the delay detection unit 52, and then input to the correlation unit 54 in order to detect clock synchronization. The correlation unit 54 performs correlation between signals output serially in time series as described later,
The output is input to a threshold detector 56, which determines whether a burst signal has been input based on whether the received signal has exceeded a threshold. Here, when the received signal exceeds the threshold value, it is determined that the possibility that the burst signal has been input is large, and the clock synchronization is determined based on the output result of the correlator 54. That is, the clock synchronization section 58 determines the clock synchronization point based on the waveform, and
The peak value is determined by determining whether the value of the data output from 2 is positive (plus) or negative (minus), and the UW comparison unit 62 compares the UWs to determine whether the data has been applied to itself. The burst supplementing section 64 performs digital demodulation processing in synchronization with a clock only when a burst signal is input and applied to itself. Correlation unit 54 shown in FIG.
For example, a plurality of delay units for holding and delaying data of the sampling time interval length of the digital demodulator 50 are serially connected, and a predetermined constant (C1 to CN) is set for each delay unit output. Are multiplied by each other (multiplication unit), and the respective multiplication results are respectively added (addition unit) to obtain a sum. For example, π / 4DQPSK
Using a modulation method based on (Quadrature Phase ShiftKeying), the preamble signal is converted into (1, 1), (0, 1),
In the case of transmission with a repetitive symbol pattern such as (1, 1), (0, 1),..., The above-mentioned constants C1 to CN are delayed by the time when the preamble signal is input to the digital demodulator 50. By configuring the output data of the detection unit 52 as a numerical pattern sampled at sampling time intervals by a digital modulator, when a preamble signal is input, data 66 as shown in FIGS. Is output.

When the sampling point in the digital demodulator 50 is operated at a sampling rate eight times the symbol rate of π / 4 DQPSK, the repetition pattern of the preamble is formed at a time interval of two symbols. The repetition pattern of the preamble can be represented by 16 times the sampling time. For example, the number of constants C1 to CN is 32 (N = 3
FIG. 8 shows output data from the correlator 54 when the data is composed of (2: 4 symbols). When the number of constants C1 to CN is 64 (N = 648 symbols), the output data from the correlation unit 54 is as shown in FIG. Further, the number of constants of C1 to CN is 160 (N =
160: 20 symbols), the output data from the correlation section 54 is as shown in FIG. in this way,
As the configuration of C1 to CN becomes longer, the output value from the correlator 54 becomes higher. Therefore, as shown in FIG. 8 → FIG. 9 → FIG. Becomes clearer and can be easily identified. Actually, if N = 64 is obtained (in the case of FIG. 9), it is possible to discriminate between the preamble signal input time and the other times, but when noise is added on the transmission path or in addition to the preamble signal, However, in consideration of the case where a pattern close to the pattern is input, N = 160 or more (in the case of FIG. 10).
4 is more desirable.

[0005]

However, in such a conventional digital demodulator, in consideration of the influence of noise and the like, the discriminating performance between when a preamble signal is input and when it is not is further improved. C in correlation section 54
It is desirable to increase the number of constants 1 to CN, but as the number increases, there is a disadvantage that the processing amount increases when the correlation unit 54 is processed by software. For example, when the above-described calculation processing is performed using a programmable processor such as a DSP (Digital Signal Processor), the multiplication unit and the addition unit can often calculate simultaneously with one instruction (one clock cycle of the processor). The correlator 54 can process the stored numerical data in the number of clock cycles of C1 to CN, but naturally, C1 to CN used for the correlation calculation.
If the processing time increases in proportion to the increase in the number of constants, there is an inconvenience that when the demodulation process is performed continuously as in the TDMA system, the process cannot catch up. Further, when these are configured by hardware, the circuit scale increases in proportion to the number of constants, so that there is an inconvenience of high cost. The present invention
An object of the present invention is to provide a digital demodulator and a digital demodulation method that require a short processing time and a low cost while maintaining the ability to determine whether a preamble signal is input. Is to provide.

[0006]

According to a first aspect of the present invention, there is provided a delay detecting means for delay detecting a received signal, a correlating means for correlating an output of the delay detecting means, and an output of the correlating means being a predetermined value. A threshold detecting means for determining whether a burst signal has been input based on whether or not the threshold value has been exceeded. A delay adding means for delaying the output correlated by the correlating means and adding the correlated outputs to each other. According to this, the delay-added means for delaying the correlated output by the correlating means and adding the correlated outputs is provided between the correlating means and the threshold value detecting means. The processing time can be shortened while accurately determining the presence / absence, and the cost can be reduced. According to a second aspect of the present invention, in the digital demodulator according to the first aspect, the correlating means includes a plurality of serially arranged first signals each holding and delaying an input signal from the differential detection means. A delay unit, a multiplication unit that multiplies each signal stored in the first delay unit using a predetermined constant, and a first addition unit that adds the multiplication results of the multiplication units. A plurality of second delay units arranged in series for holding and delaying the input signals correlated by the correlation unit, respectively, and the signals stored in the second delay unit; And a second adding unit for adding According to this, the correlation unit includes the first delay unit, the multiplication unit, and the first addition unit, and the delay addition unit includes the second delay unit.
, The processing time can be shortened and the cost can be reduced while accurately determining the presence or absence of the input of the preamble signal. According to a third aspect of the present invention, there is provided a detection process for delay-detecting a received signal, a correlation process for correlating an output signal after the delay detection, and determining whether the correlated output signal exceeds a predetermined threshold value. In the digital demodulation method including a judgment step of judging the possibility that a burst signal has been input based on whether the correlation signal and the judgment step are held and delayed during the correlation step and the judgment step And a delay addition step of adding the delayed signals to each other. According to this, a delayed addition process of holding and delaying the correlated output signal and adding the delayed signals is provided between the correlation process and the determination process, so that the input of the preamble signal is performed. It is possible to shorten the processing time and accurately reduce the cost while accurately determining the presence / absence.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS. FIG. 1 is a block diagram illustrating a schematic configuration of a digital demodulator 10 according to the present embodiment. In FIG. 1, the digital demodulator 10 includes a delay detection unit 12, a correlation unit 14, a delay addition unit 16, a threshold detection unit 18, a clock synchronization unit 20, a determination unit 22, a UW comparison unit 24, a burst supplement unit 26, and the like. It has. The digital demodulator 1 according to the present embodiment
0 is implemented as a digital demodulator used for mobile communication and satellite communication. First, as shown in FIG. 1, a received signal input to the digital demodulator 10 is delay-detected by the delay detection unit 12 and then input to the correlation unit 14. FIG. 2 shows a specific configuration example of the correlator 14. That is, in order to delay the sampling time interval in the digital demodulator 10, a plurality of delay units 32a,
, 32o are serially connected to each other to form a shift register.
Each of the outputs 32o is multiplied by constants 36a to 36p of C1 to CN of numerical data stored in advance by the multipliers 34a to 34p.
The sum is obtained by multiplying the output from each of the multipliers 34p and adding the outputs from the respective multipliers 34a to 34p using the adders 38b to 38p. A feature of the present embodiment is that a delay addition unit 16 for inputting the output from the correlation unit 14 is provided, and a specific configuration example of the delay addition unit 16 is shown in FIG. That is, the correlation unit 1 described above
The output of each of the delay units 42a to 42j corresponding to the time interval of the number of constants in which the delay units 32a to 32o are serially connected in the unit 4 is added by the adders 44a to 44j.

For this reason, the signal output from the correlation unit 14 in FIG.
Based on the output of the delay addition unit 16, the threshold detection unit 18 at the next stage determines the possibility of inputting a burst signal. When the threshold detector 18 determines that the possibility that the burst signal has been input is large, the clock synchronization is determined based on the calculation result of the delay adder 16. For example, the digital demodulator 10 shown in FIG.
, Consider a case where sampling is performed at eight times the symbol frequency. The preamble pattern output from the delay detection unit 12 is a pattern 28 as shown in FIG. This means that the preamble signal is converted into (1, 1), (0, 1), and π / 4 DQPSK using a modulation method.
When transmitted in a repetitive symbol pattern such as (1, 1), (0, 1),.
It shows an output pattern on the signal side. Points A and B in FIG. 4 indicate peak points of the positive (plus) and negative (minus) preamble patterns, respectively. Since the period of the repetition pattern of the preamble in this case is equivalent to two symbols, it can be considered that one repetition pattern is obtained by sampling 16 times. Therefore, in the present embodiment, for example, the number of constants (C1 to CN) in the correlation unit 14 is set to N = 16.

First, as shown in FIG. 1, when a preamble signal is input, a correlation is obtained by a correlation unit 14 with respect to an output from a delay detection unit 12 in which a pattern is repeated in 16 samples. Then, as shown in FIG. 3, the delay adder 14 at the next stage delays the time corresponding to the sample, which is the period of the repetition pattern of the preamble, by M
The delay units 42a to 42j are serially connected, and the outputs of the respective delay units 42a to 42j are added by the adders 44a to 44j, respectively. At this time, with respect to the time nt when the correlation is first obtained, (n
By taking a delay like (+16) t, (n + 32) t,..., All the correlated outputs are added. According to this method, the delay units 42a to 42j
Is provided, an output having substantially the same magnitude as the calculation result obtained by calculating the correlation by 16 × M can be obtained. FIG.
7 shows the output waveform of the delay addition unit 16 when M = 6 and M = 10, and it becomes possible to identify the input of the preamble to the same extent as in the case of the conventional FIG. The output of the delay adder 16 is output to a threshold detector 18
The threshold value detector 18 determines whether the burst signal has been input according to whether the received signal has exceeded the threshold value. Here, when the received signal exceeds the threshold value, it is determined that the possibility that the burst signal has been input is large, and the clock synchronization is determined based on the output result of the delay addition unit 16. That is, the clock synchronization unit 20 determines the clock synchronization point based on the waveform, and determines whether the value of the data output from the delay detection unit 12 is positive (plus) or negative (minus) to determine the peak point. Asked,
The UW comparison section 24 compares the UWs to determine whether or not the signal has been applied to itself, and the burst supplementing section 26 performs clock demodulation only when a burst signal is input and applied to itself, and performs digital demodulation. Processing is performed.

In this embodiment, a case will be described in which the above-described calculation processing is performed by software. For example, when processing is performed using a programmable processor such as a DSP (Digital Signal Processor),
When the same calculation processing as that of the configuration of the above-described embodiment is performed by software, the digital demodulator 10 delays the delay unit 42a at a time interval N times the sampling time interval.
Since the same calculation processing as that of the delay adder 16 provided with M pieces of .about.42j is performed, the processing time is greatly reduced as compared with the N + M clock time as the clock time interval of the processor and the conventional processing time N.times.M clock time. Can be shortened.
Therefore, even when digital demodulation processing is performed continuously as in the TDMA method, it is possible to prevent the processing time from increasing and preventing the processing from catching up. Incidentally, in this embodiment, since N = 16 and M = 10, the processing amount of the demodulation processing of the digital demodulator 10 is 16 + 1.
0 = 26 cycles, whereas in the conventional example, FIG.
When trying to obtain a signal output waveform with the same amplitude as
N = 160, and the processing time is 160
It can be seen from the cycle and the extremely long cycle that the technique of the present invention is working effectively. Further, even if the correlation unit 14 and the delay addition unit 16 are configured by hardware, the cost can be reduced because the circuit scale does not increase.

[0011]

As described above, according to the digital demodulators of the first and second aspects, the processing time is shortened and the cost is reduced while maintaining the ability to determine whether or not a preamble signal is input. Can be. According to the digital demodulation method of the third aspect, it is possible to shorten the processing time and reduce the cost while maintaining the ability to determine the presence or absence of the input of the preamble signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a digital demodulator according to the present embodiment.

FIG. 2 is a diagram illustrating a configuration example of a correlation unit in FIG. 1;

FIG. 3 is a diagram illustrating a configuration example of a delay addition unit in FIG. 1;

FIG. 4 is a diagram showing an output waveform when a preamble is input to the differential detection unit in FIG. 1;

FIG. 5 is a diagram illustrating an output waveform when a preamble is input to the delay addition unit in FIG. 1;

FIG. 6 is a diagram illustrating a configuration example of a frame used in the TDMA scheme.

FIG. 7 is a block diagram illustrating a configuration of a conventional digital demodulator.

8 is a diagram showing an output waveform at the time of inputting a preamble of the correlation unit in FIG. 7; (When N = 32)

9 is a diagram illustrating an output waveform when a preamble is input to the correlation unit in FIG. 7; (When N = 64)

10 is a diagram illustrating an output waveform when a preamble is input to the correlation unit in FIG. 7; (When N = 160)

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Digital demodulator 12 Delay detection part 14 Correlation part 16 Delay addition part 18 Threshold detection part 20 Clock synchronization part 22 Judgment part 24 UW comparison part 26 Burst supplementation part

Claims (3)

[Claims] 1. A delay detection means for delay-detecting a received signal, a correlation means for correlating an output of the delay detection means, and a burst signal is detected based on whether or not an output of the correlation means exceeds a predetermined threshold value. In a digital demodulator having threshold detecting means for determining the magnitude of the possibility of input, between the correlating means and the threshold detecting means, the output correlated by the correlating means is delayed. A digital demodulator comprising delay adding means for adding the correlated outputs. 2. The apparatus of claim 2, wherein the correlating means comprises: a plurality of first delay units arranged in series for holding and delaying input signals from the delay detection means, respectively; and each of the first delay units stored in the first delay unit A multiplying unit for multiplying each of the signals by using a predetermined constant, and a first adding unit for respectively adding the multiplication results of the respective multiplying units, wherein the delay adding means is correlated by the correlating means. A plurality of second delay units arranged in series for holding and delaying input signals, and a second delay unit for adding signals stored in the second delay units to each other
2. The digital demodulator according to claim 1, further comprising an adder. 3. A detection process for delay-detecting a received signal, a correlation process for correlating an output signal after the delay detection, and a burst depending on whether the correlated output signal exceeds a predetermined threshold value. In a digital demodulation method including a determination step of determining the possibility of input of a signal, between the correlation step and the determination step, a correlated output signal is held and delayed, and the delay is performed. A digital demodulation method characterized by comprising a delay addition step of adding signals obtained from each other.