JP2002118368A - Wiring substrate and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring substrate together with its manufacturing method where an electronic part is incorporated while cracking is hard to occur on a core substrate. SOLUTION: A wiring substrate 1 is provided which comprises a core substrate 2 comprising a front surface 3 and a rear surface 4, and a chip capacitor 10 of an electronic part incorporated in a through hole 5 through a resin 13 penetrating the front surface 3 and the rear surface 4. The chip capacitor 10 comprises an electrode 12 protruding from an upper end and a lower end, and the resin 13 comprises a silica filler (inorganic filler) (f). A maximum particle size D of the silica filler (f) is half of a height h of the electrode 12 or less.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board having an electronic component built in a core board and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the demand for higher density and higher performance of a wiring board, a wiring board in which electronic components are incorporated in a core board has been proposed. For example, the wiring board 40 shown in FIG. 6 is obtained by laminating insulating layers 43 and 43 on the front and back surfaces of the insulating layer 41 via wiring layers (not shown), and mounting an electronic component 45 on the first main surface. I have. The electronic component 44 and the chip capacitor are also provided in the through hole 42 of the insulating layer 41 located in the center in the thickness direction and the concave portion 42a opened on the surface side.
(Electronic components) 46 are inserted, and these are buried by a prepreg adhesive layer 47.

[0003]

However, in the wiring board 40 described above, the chip capacitor 46 built in the recess 42a is molded and buried with a thin prepreg adhesive layer 47. For this reason, cracks tend to occur in the adhesive layer 47 near the electrodes of the chip capacitor 46 that penetrate the adhesive layer 47. When such cracks are formed, there is a problem that the insulating properties and airtightness in the vicinity are reduced, and the characteristics of the chip capacitor 46 may become unstable. The present invention
Solving the problems in the conventional technology described above,
It is an object of the present invention to provide a wiring board in which electronic components are built in with less occurrence of cracks and the like in a core board and a method of manufacturing the same.

[0004]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a resin for molding and embedding an electronic component, including an inorganic filler, and associating a particle size of the filler with an electrode of the electronic component. It is made by paying attention to. That is, a first wiring board (claim 1) of the present invention includes a core substrate having a front surface and a back surface, and an electronic component built in a through hole penetrating the front surface and the back surface via a resin. The electronic component has electrodes protruding from at least one of an upper end and a lower end, and the resin contains an inorganic filler. Further, the second aspect of the present invention
The wiring board (Claim 2) includes a core substrate having a front surface and a back surface, and an electronic component embedded in a concave portion opened to the front surface or the back surface via a resin, wherein the electronic component has an upper end and At least one of the lower ends has an electrode protruding, and the resin contains an inorganic filler.

According to these, the resin is reinforced by the inorganic filler and the coefficient of thermal expansion is reduced, so that cracks do not occur in the resin in which the electronic component is buried, and particularly, the electrode is adjacent to the upper end or lower end of the electronic component from which the electrode protrudes. The thin resin portion that is hardly cracks or peels off. For this reason,
Electronic components can be built into the through holes and recesses of the core substrate with insulation and airtightness. Therefore, the function of the electronic component can be reliably exhibited, and the conduction with the wiring layer inside the substrate can be stably secured via the electrodes.

A third wiring board according to the present invention includes a core substrate having a front surface and a back surface, and an electronic component built in the core substrate, wherein the electronic component has at least an upper end and a lower end. It has an electrode protruding on one side, and the core substrate contains an inorganic filler.
According to this, since the core substrate itself containing the electronic component is reinforced by containing the inorganic filler, cracks do not occur around the electronic component, and particularly, the electrode is adjacent to the upper end or lower end of the protruding electronic component. The thin portion of the core substrate is less likely to crack or peel off the thin portion.
For this reason, since the electronic component can be built in the core substrate itself with insulation and airtightness, the function of the electronic component can be reliably exhibited, and the conduction with the wiring layer inside the substrate via the electrode can be stably performed. It is possible to secure.

The electronic components include passive components such as capacitors, inductors, filters, and resistors, active components such as low-noise amplifiers (LNA), transistors, semiconductor elements, and FETs, or SAW filters, LC filters, and antenna switches. Modules, couplers, diplexers, etc. are included. In addition, a chip-shaped electronic component and an electronic component unit in which a plurality of such chip-shaped electronic components are set are also included. Of these, different types of electronic components may be incorporated in the same through hole or recess. In addition, inorganic fillers include, but are not limited to, crystalline silica, fused silica, alumina, silicon nitride, and the like. By including the inorganic filler, the coefficient of thermal expansion of the resin is 40 ppm / ° C or less (however,
0 is not included), preferably 30 ppm / ° C or less (however, 0
Is not included), more preferably 25 ppm / ° C or less (however,
0 is not included), and more preferably 20 ppm / ° C. or less (however, 0 is not included). Thereby, the stress concentration based on the difference from the thermal expansion coefficient of the built-in electronic component can be reduced. In addition, in any of the above thermal expansion coefficients, the lower limit is preferably set to 10 ppm / ° C. or more.

In the present invention, the particle diameter of the inorganic filler is not more than one half of the height of the electrode (however, 0 is not included).
(Claim 4) is also included. According to this, since the thin resin portion adjacent to the upper and lower ends of the electronic component from which the electrodes protrude or the thin portion of the core substrate is strengthened, cracks due to thermal expansion or thermal contraction and peeling of the thin portion are prevented. Can be. That is, in the thin portion of the resin or the core substrate adjacent to the upper end or lower end of the electronic component from which the electrode protrudes, the inorganic filler does not easily turn around, but according to the present invention, the particle size of the inorganic filler is smaller than the height of the electrode. Since it is relatively small, the filler can penetrate securely and uniformly.
For this reason, the filler filling amount in the thin portion of these resins is not reduced, and the thermal expansion becomes uniform, so that cracks can be prevented.

When a wiring layer is formed as a build-up layer above and below a core substrate, the resin is roughened by using an oxidizing agent. However, according to the wiring substrate of the present invention, the filler becomes uniform. The resin can also be uniformly roughened. For this reason, it is possible to ensure the close contact between the resin in which the electronic component is embedded and the wiring layer formed on the surface thereof. The filler particle size refers to the maximum particle size in the filler particle size distribution. If the maximum particle size according to the particle size distribution of the inorganic filler exceeds half the height of the electrode, cracks and the like are more likely to occur, so this range is excluded. Further, the particle size of the inorganic filler is more preferably one third or less (however, 0 is not included) of the height of the electrode. The shape of the inorganic filler is desirably substantially spherical in order to increase the fluidity and filling rate of the resin and the material forming the core substrate, but may be elliptical having a major axis and a minor axis. Furthermore, in order to achieve a low viscosity and a high filling rate of the resin, the average particle diameter and the particle shape are different.
It is desirable to use more than one kind of inorganic filler.

Further, according to the present invention, the particle size of the inorganic filler is not more than 25 μm and the height of the electrode is 50 μm.
m or more is also included. According to this, since the thin resin portion adjacent to the upper end and the lower end of the electronic component from which the electrode protrudes or the thin portion of the core substrate is reinforced in an appropriate state, it is possible to reliably prevent cracks and peeling from occurring. Becomes possible. Here, the particle size is 25 μm
The following means that the maximum particle size in the particle size distribution is 25 μm (however, 0 is not included). When the particle size of the silica filler exceeds 25 μm, cracks and the like tend to be easily generated in the thin resin portion. Therefore, such a range is excluded, and the preferable particle size is 20 μm or less (however, 0 is included. Zu). However, the lower limit of the particle size of the silica filler is 0.1 μm or more, preferably 0.5 μm or more, in order to secure the fluidity of the resin. In this specification, the particle diameter is measured as a diameter when a projected image is approximated to a circle by a laser diffraction particle sizer.

When the height of the electrode is less than 50 μm, cracks and the like are liable to occur similarly to the above, so that the range is excluded. The upper limit of the electrode height is preferably 100 μm or less (however, 0 is not included) in order to prevent a short circuit between the electrodes. Furthermore,
The surface roughness of an electrode in an electronic component is a ten-point average roughness Rz.
Is 0.3 to 20 μm, preferably 0.5 to 10 μm, and more preferably 0.5 to 5 μm. As a result, the resin penetrates into the irregularities on the electrode surface, so that an anchor effect for improving the adhesion can be obtained. The control of the surface roughness is not particularly limited, and is performed by a method such as a surface roughening treatment by chemical etching, a micro etching treatment, a blackening treatment, or the like.

On the other hand, a method of manufacturing a wiring board according to the present invention (Claim 6) is characterized in that a core substrate having a front surface and a back surface and a recess formed in the through hole penetrating the front surface and the back surface or the front surface or the back surface are provided. A method of manufacturing a wiring board, comprising: an electronic component having electrodes protruding on at least one of an upper end and a lower end of the electronic component; A step of embedding and embedding the electronic component in a through hole or a recess with a resin containing, and a step of exposing the end face of the electrode by polishing and surface-regulating the surface of the resin,
Which is characterized in that

According to this, the thin resin portion adjacent to the upper and lower ends of the electronic component from which the electrodes protrude or the thin portion of the core substrate is strengthened, and it is possible to reliably provide a wiring substrate in which cracks and the like hardly occur. Further, since the inorganic filler is reliably filled also in the thin resin portion adjacent to the upper end or the lower end of the electronic component, cracks and the like hardly occur. For this reason, it is possible to reliably manufacture a wiring board in which electronic components are built in a core board. In the present specification, “embed” means, for example, embedding with the resin and fixing the position. Further, "flattening" means, for example, making the surface of the resin substantially flat.

[0014] In addition, the manufacturing method is incorporated in a core substrate having a front surface and a rear surface, and in a through hole penetrating the front surface and the rear surface or in a concave portion opened on the front surface or the rear surface via a resin. A method of manufacturing a wiring board comprising: an electronic component having electrodes protruding on at least one of an upper end and a lower end of the electrode; A step of embedding the electronic component in a through hole or a concave portion by using a resin containing an inorganic filler that is not more than one-fifth, and exposing an end face of the electrode by polishing and sizing the surface of the resin. And a step.
The particle size of the inorganic filler is preferably one third or less of the height of the electrode. However, the particle size of the inorganic filler is always less than or equal to one-half the height of the polished electrode.

In addition, according to the present invention, a core substrate having a front surface and a rear surface and a resin substrate are incorporated in a through hole penetrating the front surface and the rear surface or a concave portion opened on the front side or the rear side via a resin. A method of manufacturing a wiring board comprising: an electronic component having at least one of an upper end and a lower end having an electrode protruding at a height of 50 μm or more and less than 100 μm into a through hole or a concave portion. A step of embedding the electronic component in a through-hole or a recess with a resin containing an inorganic filler having a particle size of 25 μm or less, and embedding the electronic component in the through-hole or the concave portion, and polishing the surface of the resin to flatten the end surface of the electrode. And exposing the wiring board. In this case, the inorganic filler is also reliably filled in the thin resin portion adjacent to the upper end or lower end of the electronic component,
Cracks and the like are less likely to occur, and a wiring board in which electronic components are incorporated in a core board can be reliably manufactured.

[0016]

Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1A shows a cross section of a main part of a wiring board 1 according to one embodiment of the present invention. As shown in FIG. 1A, the wiring substrate 1 includes a core substrate 2 and wiring layers 14, 20, 2 formed on the upper surface 3 and the lower surface 4 thereof.
6, 15, 21, 27, insulating layers 16, 22, 28, 1
7 is a multilayer substrate having a build-up layer composed of 7, 23, and 29. The core substrate 2 is made of bismaleimide-triazine (BT) resin having a substantially square shape in a plan view and a thickness of about 0.8 mm.
As shown in (A), a plan view is almost square and one side is 12 m.
m through holes 5 are formed. Also, both sides of the through hole 5
(Peripheral) includes a through-hole 6 penetrating between the front and back surfaces 3 and 4, and a through-hole conductor 8 and a filling resin 9 therein.
Is formed.

A plurality of chip capacitors (electronic components) 10 are built in the through holes 5 of the core substrate 2 via an epoxy resin 13. Each chip capacitor 10
Is a ceramic capacitor having a plurality of electrodes 12 projecting from the upper and lower ends thereof, for example, a dielectric layer mainly composed of barium titanate and a Ni layer alternately laminated. Such a chip capacitor 10 is 3.2 mm × 1.
It has a size of 6 mm x 0.7 mm. As shown in FIG. 1B, the resin 13 in which the chip capacitor 10 is embedded has a maximum particle diameter d of about 20 to 25 μm and an average particle diameter of 4 μm.
Of silica filler (inorganic filler) f are substantially uniformly dispersed and contained without contacting each other. The height h of the electrode 12 projecting from the upper (lower) end of the chip capacitor 10 is 75 μm.
m, the surface of which is covered with a copper plating layer by barrel plating. Also, the maximum particle size d of the silica filler f
Is 以下 or less, preferably ３ or less of the height h of the electrode 12.

Therefore, the silica filler f can easily enter the thin resin portion between the upper or lower end of the chip capacitor 10 and the surface of the resin 13. For this reason, the silica filler f does not become too small, and the resin 13 is strengthened as an aggregate, and the coefficient of thermal expansion of the resin 13 can be reduced (the coefficient of thermal expansion is 30 ppm / ° C. or less). Therefore, even in the vicinity of each electrode 12 penetrating the resin 13, cracks are less likely to occur in the thin portion of the resin 13, and the core substrate 2 is kept airtight while insulating the chip capacitor 10.
Can be built in.

As shown in FIG. 1A, a wiring layer 14 made of copper plating and an insulating layer 16 made of epoxy resin are formed on the front surface 3 of the core substrate 2. The wiring layer 14 is also formed on the upper end. A filled via conductor 18 connected to the wiring layer 14 is formed at a predetermined position of the insulating layer 16, and a wiring layer 20 is formed on the upper end thereof and on the insulating layer 16. Similarly, the wiring layer 20
An insulating layer 22 and a filled via conductor 24 are formed thereon, and a wiring layer 26 is formed on the upper end thereof and on the insulating layer 22. On the wiring layer 26, a solder resist layer (insulating layer) 28 is formed, and a plurality of solder bumps (IC connection terminals) 32 penetrating therethrough and protruding higher than the first main surface 30 are formed. Each bump 32 will be
It is individually connected to connection terminals 36 projecting from the bottom surface of the IC chip 34 mounted on the main surface 30. The underside of the IC chip 34 is filled with an underfill material (not shown) around the solder bumps 32 and the connection terminals 36 so as to bury them.

As shown in FIG. 1A, a wiring layer 15 made of copper plating and an insulating layer 17 made of epoxy resin are also formed under the back surface 4 of the core substrate 2. The wiring layer 15 is also formed at the lower end. A filled via conductor 19 connected to the wiring layer 15 is formed at a predetermined position of the insulating layer 17, and a wiring layer 21 is formed at the lower end and below the insulating layer 17. Similarly, the wiring layer 21
An insulating layer 23 and a filled via conductor 25 are formed under the insulating layer 23, and a wiring layer 27 is formed below the insulating layer 23 and under the insulating layer 23. Below the wiring layer 27, a solder resist layer
(Insulating layer) 29 is formed, and the wiring 33 in the wiring layer 27 exposed in the opening 31 is covered with an Au and Ni plating film on the surface, and a printed board (not shown) on which the wiring board 1 itself is mounted. It becomes the connection terminal with the motherboard.

A pin (not shown) made of an iron-based or copper-based alloy may be connected to the surface of the wiring 33 via a Sn-Sb-based solder (low melting point alloy) or the like. In addition, the wiring layers 14, 20, 26, 15, 21, 27, the insulating layers 16, 2
2, 28, 17, 23, 29, and via conductors 18,
24, 19, and 25 are formed by a known build-up technique (semi-additive method, full-additive method, subtractive method, photolithography technique, drilling of a via hole by laser processing, and the like). Still further, FIG.
As shown in (A), a plurality of electrodes 12 projecting at the same height h also penetrate through the resin 13 filled in the through-hole 5 at the lower end of each chip capacitor 10.
The maximum particle size d of the silica filler f contained in No. 3 is not more than half, preferably not more than one third of the height h.

According to the wiring substrate 1 described above, the chip capacitor 10 is built in the through hole 5 of the core substrate 2 via the resin 13 containing the silica filler f, and the maximum particle size d of the silica filler f Is less than half the height h of the electrode 12 of the chip capacitor 10. Therefore, the electrode 1
Cracks in the resin 13 near the area 2 and peeling of the resin 13 itself are less likely to occur. Therefore, since the chip capacitor 10 can be built in with insulation and airtightness, the function of the chip capacitor 10 can be reliably exhibited, and the wiring layers 14 and 15 can be provided via the electrodes 12.
For example, conduction with the IC chip 34 can be stably secured.

In the above embodiment, the core substrate 2
Used a single-layer insulating plate, but is not limited to this.
A form in which a plurality of insulating layers are stacked and a form in which a plurality of insulating layers are stacked and a wiring layer is formed therebetween are also included. In addition, one or more kinds of materials may be used for the above-described plurality of insulating layers. Further, the chip capacitor 10 built in the core substrate 2 may have the electrode 12 protruding only on the upper end side. In this case, each chip capacitor 10 is electrically connected to the wiring layer 15 below the back surface 4 via the through-hole conductor 8 penetrating the core substrate 2.

FIG. 2 relates to main steps of a method for manufacturing the wiring board 1. FIG. 2A shows a state in which the core substrate 2 is punched to form a through hole 5 having a substantially square shape and a side of 12 mm extending through the front and rear surfaces 3 and 4 and having a side of 12 mm. 2 shows a state in which a tape T is stuck over a large number of core substrates 2 in a multi-panel panel including the core substrate 2 on the back surface 4 of FIG. The adhesive surface of the tape T faces the through hole 5 side. Next, FIG.
As shown in (B), a plurality of chip capacitors 10 whose upper and lower electrodes 12 protrude by 75 μm each into the through hole 5 are inserted by a chip mounter (not shown),
In addition, each electrode 12 on the lower end side of each capacitor 10 is bonded to the adhesive surface of the tape T.

Next, as shown in FIG. 2C, the liquid epoxy resin 1 is introduced into the through hole 5 from the front surface 3 side of the core substrate 2.
3a is filled using a dispenser (not shown). As the epoxy resin 13a, for example, a bisphenol type epoxy resin is used. The resin 13a contains the silica filler f having a maximum particle diameter of about 20 to 25 μm and an average particle diameter of 4 μm. In addition, the surface of the silica filler f enhances the wettability with the resin 13a and enhances the fluidity of the resin 13a.
Surface treatment with a coupling agent such as titanate or aluminate is performed. Further, an imidal-based, amine-based, novolak-based, or acid anhydride-based liquid curing agent is added to the liquid epoxy resin 13a to reduce the viscosity of the resin 13a and facilitate the addition of silica filler f. I have to.

The liquid epoxy resin 13 is introduced into the through hole 5.
In order to fill the gap a and fill the gap with the chip capacitor 10, it is possible to use a known injection method such as a screen printing method or a roll coating method, or a coating method, in addition to the injection method using the dispenser. The resin 13a is inserted into the through hole 5
After filling the inside, the core substrate 2 is heated to 80 to 180 ° C. to cure the resin 13a. This curing is 80 ~
A primary heating step of heating to 120 ° C, and 120 to 180 ° C
And a secondary heating step of heating to two stages.
That is, the chip capacitor 10 and the through-hole 5
This is because bubbles formed in the resin 13a between the electrodes 12 and between the electrodes 12 can be effectively defoamed, and the curing treatment can be performed without bubbles by secondary heating.

Further, the raised surface of the cured resin 13 is polished by a belt sander and finish-polished by lap polishing, so that the surface is flattened. As a result, FIG.
As shown in (D), a flat surface 13 is formed on the surface 3 side of the core substrate 2.
The resin 13 is formed, which has a b and exposes the upper end surface of the upper electrode 12 of each chip capacitor 10.
After the tape T has been peeled off, if the resin 13 on the back surface 4 side of the core substrate 2 is also made a flat surface 13c which has been flattened in the same manner as described above, the lower electrode 1
2 can be reliably exposed. The height h of each electrode 12 after polishing is 75 μm. After this,
These electrodes 12 are provided on the front surface 3 and the back surface 4 of the core substrate 2.
Are formed by photolithography technology, and further, wiring layers 20, 26, 21, 27,
Insulating layers 16, 22, 28, 17, 23, 29, and
The filled via conductors 18, 24, 19, and 25 are formed by a known build-up technique (here, a subtractive method or the like). As a result, the wiring board 1 whose main section is shown in FIG. 1A can be obtained.

[0028]

Here, specific examples of the wiring board 1 of the present invention will be described together with comparative examples. As shown in Table 1, the resin 13
A chip capacitor 10 having a maximum particle diameter d of 20 μm and an average particle diameter of 4 μm and containing 73 wt% of silica filler f, and having an electrode height h1 of 75 μm.
Was embedded in the through hole 5 of the core substrate 2, and the front and back surfaces of the resin 13 were polished and leveled to obtain the wiring substrate 1 of Example 1 in which the electrode height h2 was 60 μm. Also,
A wiring board 1 obtained in the same manner as in Example 1 except that the maximum particle size of the silica filler f was 25 μm was used as Example 2. On the other hand, as shown in Table 1, the resin 13 has a maximum particle size d.
Is 35 μm and the average particle diameter is 20 μm.
Is used and the height h1 of the electrode is 75 μm.
m is embedded in the same through hole 5 of the core substrate 2 as described above, and the chip capacitor 10 is leveled, and the electrode height h2 is 60
The wiring board of Comparative Example 1 having a thickness of μm was obtained.

[0029]

[Table 1]

As for the wiring board (1) of each example, as a result of inspecting the resin 13 near the electrode 12 adjacent to the upper and lower ends of the chip capacitor 10, cracks and peeling were not found in Examples 1 and 2, In Comparative Example 1, cracks occurred. According to this result, in Examples 1 and 2, the silica filler f was uniformly distributed even in the resin 13 near the electrode 12, whereas in Comparative Example 1, the distribution of the silica filler f was non-uniform. It is considered that the resin 13 on the side was uneven at the thin portion. Therefore, silica filler f
Of the maximum particle diameter d of the electrode 12 to the height h2 of the electrode 12 after polishing d /
The advantage of setting h2 to a half (0.5) or less was supported. Further, the ratio d / h1 of the maximum particle size d of the silica filler f to the initial height h1 of the electrode 12 is made smaller than 0.466 of Comparative Example 1, that is, the maximum particle size d of the silica filler f 9/20 (0.45) of height h1 of 12
In the following, the silica filler f is applied to the thin portion of the resin 13.
Can easily be secured.

Next, as shown in Table 2, the resin 13 commonly uses a resin containing a silica filler f having a maximum particle size d of 20 μm, and the height h2 of the electrode after polishing is 15 μm, 5 μm.
Using a plurality of chip capacitors 10 of 0 μm, 80 μm, 100 μm, and 120 μm, these were individually incorporated in the through holes 5 of the same core substrate 2 via the resin 13. Thereafter, the front and back surfaces of the resin 13 were polished and leveled to obtain a plurality of wiring boards (1).

[0032]

[Table 2]

As a result of inspection, the wiring boards 1 of Examples 3 to 6 in which the electrode height h2 is 50 to 120 μm are as follows.
In any case, no crack occurs in the resin 13 after the surface preparation,
After the subsequent plating step including surface roughening, the resin 13 did not float or fall off. On the other hand, the height h2 of the electrode is 1
In the case of the wiring board of Comparative Example 2 having a thickness of 5 μm, cracks occurred in the resin 13 after leveling, the main body of the chip capacitor 10 was exposed, and the resin 13 floated or dropped off after the plating step. However, in the wiring board of Example 6 in which the electrode height h was 120 μm, a short circuit occurred between the electrodes 12 after the plating step. Therefore, the ratio d / h2 between the maximum particle size d of the silica filler f and the height h2 of the electrode 12 after polishing is reduced by half.
The superiority of setting to (0.5) or less was supported. According to the wiring boards 1 of Examples 1 to 6 described above, the maximum particle size of the silica filler f is 25 μm or less, and the height h of the electrode 12 of the built-in chip capacitor 10 is 50 μm or more (1
(Preferably 00 μm or less) can be easily understood.

FIG. 3A shows a cross section of a main part of a wiring board 1a in a modified form of the wiring board 1. As shown in FIG. In the following, the same reference numerals are used for the same parts and elements as in the above-described embodiment. The core substrate 2 of the wiring substrate 1a has a concave portion 5 which is open on the front surface 3 side and is approximately square in plan view and 12 mm on a side.
a is formed by router processing. Also, the recess 5a
A through hole 37 is formed between the bottom surface 5b of the core substrate 2 and the back surface 4 of the core substrate 2, and a through hole conductor 38 is formed in the through hole 37.
And a filling resin 39 are formed. A pad 38a is formed on the upper end of the through-hole conductor 38 and on the bottom surface 5b of the recess 5a, and is individually connected to the lower electrode 12 of the chip capacitor 10 via the solder 38b. Note that the lower end of the through-hole conductor 38 and the core substrate 2
The wiring layer 15 similar to the above is located under the back surface 4 of the substrate.

In the recess 5a, a liquid epoxy resin 13a containing the same silica filler f as described above is placed in a state in which the plurality of chip capacitors 10 and the electrodes 12 on the lower end side are connected in advance to the pads 38a via the solders 38b. After being filled and subjected to a curing treatment by heating to obtain a resin 13, the surface is adjusted in the same manner as described above. Thereafter, as shown in FIG. 3A, the same wiring layers 14, 20, 26, 15, 21, 27, insulating layers 16, 22, 28, 17, 23, 29, and filled via conductors 18, 24, 19, and 25 are formed by a known build-up technique, and the wiring board 1a is obtained. As shown in FIG. 3 (B), silica filler f having a maximum particle size d of about 25 μm is substantially uniformly dispersed and contained in resin 13 in which chip capacitor 10 is embedded. Height h of electrode 12 projecting from the upper end of chip capacitor 10
Is 80 μm and the maximum particle size d of the silica filler f
Is less than one third of that.

For this reason, even in the thin resin portion sandwiched between the upper end of the chip capacitor 10 and the surface of the resin 13, the silica filler f does not become too small, strengthening the resin 13 as an aggregate and reducing the coefficient of thermal expansion. It is possible to plan. Accordingly, even in the resin 13 near each of the electrodes 12, cracks are less likely to occur and the resin 13 is less likely to be peeled off, and the chip capacitor 10 can be built in the core substrate 2 while insulating and maintaining airtightness. The lower electrode 12 of the chip capacitor 10 also protrudes at the same height h as described above. Therefore, the lower electrode 12 and the solder 38b provide
The gap between the chip capacitor 10 and the bottom surface 5b of the concave portion 5a becomes sufficient, and the silica filler f easily enters the gap. In FIG. 3A, the lower electrode 12 and the pad 38a are connected via the solder 38b, but this is not a limitation. For example, the lower electrode 12
And the pad 38a may be connected so as to be in direct contact with each other.

FIG. 4A shows a cross section of a main part of a wiring board 1b in a modified form of the wiring board 1a. The core substrate 2 of the wiring substrate 1b has an opening on the back surface 4 side, and a recess 5c having a substantially square shape in plan view and a side of 12 mm is formed by router processing. A through hole 37 is formed between the bottom surface (ceiling surface) 5d of the concave portion 5c and the front surface 3 of the core substrate 2, and the through hole conductor 38 and the resin 3
9 is formed. A pad 38a is formed at the lower end of the through-hole conductor 38 and on the bottom surface 5d of the recess 5c, and the upper end side of the chip capacitor 10 (IC
It is individually connected to the electrode 12 on the chip 34 side).
The wiring layer 14 similar to the above is formed on the upper end of the through-hole conductor 38 and on the surface 3 of the core substrate 2.

As shown in FIG. 4A, in the recess 5c,
The liquid epoxy resin 13a containing the same silica filler f as described above is filled in a state in which the plurality of chip capacitors 10 are connected in advance to the pads 12a via the solders 38b. Application resin 1
After setting to 3, the surface is flattened as described above. Thereafter, as shown in FIG. 4A, the same wiring layers 14, 2 as described above.
0, 26, 15, 21, 27, insulating layers 16, 22, 2
8, 17, 23, 29 and filled via conductor 1
8, 24, 19, and 25 are formed by a known build-up technique, and a wiring board 1b in which the chip capacitor 10 is built in the core board 2 is obtained. As shown in FIG. 4 (B), silica filler f having a maximum particle size d of about 25 μm is substantially uniformly dispersed and contained in resin 13 in which chip capacitor 10 is embedded. The height h of the electrode 12 projecting from the lower end of the chip capacitor 10 is 50 to 100 μm,
In addition, the maximum particle size d of the silica filler f is not more than half, preferably not more than one third of the height h.

As shown in FIG. 4A, the electrode 12 on the upper end side of the chip capacitor 10 also protrudes at the same height h as described above. For this reason, the upper electrode 12 and the solder 38b
Accordingly, a gap between the chip capacitor 10 and the bottom surface 5d of the concave portion 5c becomes sufficient, and the silica filler f easily enters the gap. In FIG. 4A, the upper electrode 1
2 and the pad 38a are connected via the solder 38b, but the present invention is not limited to this. For example, the upper electrode 1
2 and the pad 38a may be connected so as to be in direct contact with each other. In the wiring board 1b, the chip capacitor 10 built in the core board 2 has an upper end side (the IC chip 34 side).
Only the electrode 12 may be provided protruding therefrom. In this case, each chip capacitor 10 is electrically connected to the wiring layer 14 above the surface 3 via the through-hole conductor 8 penetrating the core substrate 2.

In the above-described embodiments of the wiring substrates 1a and 1b, the core substrate 2 uses a single-layer insulating plate, but the present invention is not limited to this. Are laminated, and a wiring layer is formed between them. Alternatively, through holes may be formed in advance in a part of the plurality of insulating layers, and the concave portions 5a and 5c may be formed when the insulating layers are laminated with another insulating layer. Further, one or more kinds of materials may be used for the plurality of insulating layers. In the wiring board 1b, a build-up layer including insulating layers 17, 23, 29, wiring layers 21, 27, and filled via conductors 19, 25 was formed below the back surface 4 of the core substrate 2. It is not limited to such a form. That is, the insulating layer 29 is provided below the back surface 4 of the core substrate 2.
Like the embodiment in which only the wiring layer 15 (including the wiring 33) is formed, a single-layer wiring board (not shown) in which a buildup layer is formed only above the surface 3 of the core substrate 2 can be used.

FIG. 5 relates to main steps of a method for manufacturing a wiring board 1c having a different configuration. FIG. 5A shows a state in which resin sheets 2a and 2b made of BT resin and containing the silica filler f having a maximum particle size of about 25 μm are arranged above and below a plurality of chip capacitors 10. Electrodes 12 protruding from the upper or lower end of each chip capacitor 10
Is 75 μm, and the maximum particle size of the silica filler f is
It is not more than half, preferably not more than one third of the height h. The resin sheets 2a and 2b have a thickness that is about half the height of the entire chip capacitor 10. As shown by the arrows in FIG. 5A, the resin sheets 2a and 2b are pressed while approaching each other along the vertical direction while being heated. as a result,
As shown in FIG. 5 (B), the resin sheets 2a and 2b are fused with each other, and enter the chip capacitors 10 and 10 to form the integrated core substrate 2.

At this time, as shown in FIGS. 1B and 3B, the thin resin portion sandwiched between the upper and lower ends of the chip capacitor 10 and the front surface 3 and the back surface 4 of the core substrate 2 is also used. The silica filler f does not become too small, and it is possible to strengthen the core substrate 2 as an aggregate and to lower the coefficient of thermal expansion. Therefore, as shown in FIG. 5B, cracks are less likely to occur in the core substrate 2 itself near the electrodes 12 penetrating the thin resin portion of the core substrate 2, thereby insulating the chip capacitor 10 and improving the airtightness. It can be built into the core substrate 2 while maintaining it. Next, as shown in FIG. 5 (C), after drilling through holes 6 and 6 at predetermined positions of the core substrate 2, the through holes 6 and 6 are formed in each hole 6 and on the front surface 3 and the back surface 4 of the core substrate 2.
A copper plating layer is formed below and a photolithography technique is applied. Thereby, as shown in FIG. 5D, a wiring board 1c on which the through-hole conductors 8, 8 and the wiring layers 14, 15 are formed is obtained.

According to the above wiring board 1c, the core board 2
It is not necessary to form the through-holes 5 and the recesses 5a and 5c in these holes or to fill them with the liquid resin 13a. Moreover, the silica filler f is sandwiched between a plurality of chip capacitors 10.
The resin sheets 2a and 2b containing the same are arranged and pressurized while heating them, whereby the chip capacitor 10 can be built in the integrated core substrate 2 itself. Therefore, the chip capacitor 10 can be insulated by the uniform core substrate 2 and can be built in the core substrate 2 while maintaining airtightness. The wiring layers 20, 26, 21, 27, the insulating layer 1
By forming the 6, 22, 28, 17, 23, 29 and filled via conductors 18, 24, 19, 25 by a known build-up technique, the same as the wiring board 1 shown in FIG. It is clear that a wiring board having a simple multilayer structure can be obtained.

The present invention is not limited to the embodiments described above. For example, only one electronic component may be built in the through hole 5 or the recesses 5a and 5c or in the core substrate 2. Conversely, a plurality of through holes 5 and recesses 5a and 5c may be formed in one product unit in a panel including a large number of core substrates 2. The electrode 1 is provided only in the upper end (IC chip 34) side in the through hole 5 of the core substrate 2.
It is also possible to incorporate an electronic component such as the capacitor 10 having two. Further, a unit in which a plurality of chip-shaped electronic components are bonded in advance between their side surfaces may be inserted into the through-hole 5 or the recesses 5a and 5c to be built therein. In addition, the chip-shaped electronic components include, in addition to the chip capacitor 10, passive components such as chip-shaped inductors, resistors, and filters, and active components such as transistors, memories, and low-noise amplifiers (LNA). It is also possible to incorporate different types of electronic components in the same through-hole or concave portion or in a core substrate. In addition, on both front and back surfaces 3 and 4 of the core substrate 2,
In addition to connecting the electrode of the electronic component and the wiring layer, only one of the front surface and the back surface may be connected.

Further, the material of the core substrate 2 may be glass fiber such as glass woven cloth or glass woven cloth having the same heat resistance, mechanical strength, flexibility, and ease of processing, as well as the BT resin, and epoxy resin. Alternatively, a glass fiber-resin composite material which is a composite material with a resin such as polyimide resin, BT resin, or the like may be used. Alternatively, a composite material of an organic fiber such as a polyimide fiber and a resin, or PTFE having continuous pores
It is also possible to use a resin-resin composite material in which a resin such as an epoxy resin is impregnated into a fluorine-based resin having a three-dimensional network structure. The material of the wiring layers 14 and 15 may be Ni, Ni-Au, or the like in addition to the copper plating, or may be formed by applying a conductive resin without using metal plating. It is also possible. Further, the via conductor 18 and the like are not limited to the form of the filled via filling up the inside of the via hole, and may have a conical form following the shape of the via hole.

The materials of the insulating layers 16 and 17 are
The same heat resistance other than the epoxy resin as the main component
Resin, BT which has properties and pattern moldability
Resin, PPE resin, or PTF having continuous pores
Epoxy resin to fluororesin with 3D network structure such as E
Resin-resin composite material impregnated with resin such as
It can also be used. In addition, liquid resin is used for forming the insulating layer.
In addition to applying a
It is also possible to use a method of thermocompression bonding of the lum. Furthermore, before
The chip capacitor 10 includes BaTiO₃Etc.
High dielectric ceramic was used, but PbTi
O₃, PbZrO₃, TiO₂, SrTiO₃, CaT
iO₃, MgTiO₃, KNbO₃, NaTiO₃, K
TaO₃, PbTaO₃, (Na_1/2Bi_1/2) Ti
O₃, Pb (Mg_1/2W_1/2) O ₃, (K_1/2Bi
_1/2) TiO₃It is also possible to use a material whose main component is
No.

Although the material of the electrode 12 of the capacitor 10 is mainly composed of Cu, Pt, Ag, Ag-Pt, Ag-Pd, Pd, A
u, Ni, etc. can be used. In addition, the capacitor 10 of the electronic component includes a dielectric layer mainly composed of a high dielectric ceramic, an electrode layer made of Ag-Pd, and a via conductor or a wiring layer made of resin, Cu plating, Ni plating, or the like. May be combined as a capacitor. Incidentally, it is also possible to form a plurality of mounting areas on the first main surface 30 of the wiring boards 1, 1a, 1b, and to mount a plurality of IC chips 34 individually in each area.

[0048]

The wiring board of the present invention described above.
According to the first and second aspects, cracks do not occur in the resin in which the electronic component is embedded. In particular, cracks and peeling are less likely to occur in the thin resin portion adjacent to the upper and lower ends of the electronic component from which the electrodes protrude. Therefore, the electronic component can be incorporated in the through hole or the concave portion of the core substrate with insulation and airtightness, so that the function of the electronic component can be surely exhibited, and conduction with the wiring layer inside the substrate via the electrode can be achieved. Can be secured stably. According to the third aspect of the present invention, since the core substrate itself containing the electronic component is reinforced by containing the inorganic filler, cracks are less likely to occur around the electronic component, and particularly, the electrodes protrude. The thin part of the core board adjacent to the upper and lower ends of the electronic components
Cracks are less likely to occur. For this reason, the electronic component can be built in the core substrate itself with insulation and airtightness, and the function of the electronic component can be reliably exhibited, and the conduction with the wiring layer inside the substrate via the above-mentioned electrodes is also stably secured. it can.

Furthermore, according to the wiring substrate of the fourth or fifth aspect, the thin resin portion adjacent to the upper end or the lower end of the electronic component from which the electrode protrudes or the thin portion of the core substrate is strengthened, so that thermal expansion is achieved. And cracks due to thermal shrinkage can be reliably prevented. On the other hand, according to the method of manufacturing a wiring board of the present invention (claim 6), the thin resin portion adjacent to the upper end or lower end of the electronic component from which the electrode protrudes or the thin portion of the core substrate is strengthened, so that cracks and the like are reduced. It is possible to reliably provide a wiring board that is unlikely to occur.

[Brief description of the drawings]

1A is a cross-sectional view of a main part of a wiring board according to one embodiment of the present invention, and FIG. 1B is an enlarged view of a dashed-dotted line portion B in FIG.

FIGS. 2A to 2D are schematic diagrams showing main steps for manufacturing the wiring board of FIG. 1A.

3A is a cross-sectional view of a main part in a modified example of the wiring board of FIG. 1A, and FIG. 3B is an enlarged view of a dashed-dotted line portion B in FIG.

4A is a cross-sectional view of a main part in a modification of the wiring board of FIG. 3A, and FIG. 4B is an enlarged view of a dashed-dotted line portion B in FIG.

FIGS. 5A to 5D are schematic diagrams showing main steps for manufacturing a wiring board of a different form.

FIG. 6 is a sectional view showing a conventional wiring board.

[Explanation of symbols]

 1, 1a to 1c Wiring board 2 Core substrate 3 Front surface 4 Back surface 5 Back hole 5a, 5c ... Recess 10 chip capacitor (electronic part) 12 electrode 13 resin f silica filler (inorganic filler) d. ... Maximum particle size (particle size) of silica filler h (h1, h2) ... Height of electrode

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yuki Ogawa 14-18 Takatsuji-cho, Mizuho-ku, Nagoya-shi, Aichi F-term in Japan Special Ceramics Co., Ltd. 5E314 AA24 AA42 BB06 BB13 CC01 FF08 GG09 5E336 AA07 AA16 BB03 BB15 BC02 BC31 CC32 CC51 GG12 GG16 5E346 AA02 AA05 AA06 AA12 AA15 AA41 AA60 BB01 CC08 CC16 CC31 DD01 DD31 EE31 FF45 GG01 GG15 GG28 GG40 HH08 HH11

Claims (6)

[Claims] A core substrate having a front surface and a back surface; and an electronic component embedded in a through-hole penetrating the front surface and the back surface via a resin, wherein the electronic component is provided on at least one of an upper end and a lower end. A wiring board having a protruding electrode, wherein the resin contains an inorganic filler. 2. A semiconductor device comprising: a core substrate having a front surface and a back surface; and an electronic component embedded via a resin in a concave portion opened to the front surface or the back surface, wherein the electronic component is at least one of an upper end and a lower end. A wiring board, wherein the resin contains an inorganic filler. 3. A core substrate having a front surface and a back surface, and an electronic component built in the core substrate, wherein the electronic component has electrodes protruding on at least one of an upper end and a lower end. A wiring substrate comprising an inorganic filler. 4. The wiring board according to claim 1, wherein a particle size of the inorganic filler is equal to or less than a half of a height of the electrode. 5. The wiring board according to claim 1, wherein the particle size of the inorganic filler is 25 μm or less, and the height of the electrode is 50 μm or more. 6. A wiring comprising: a core substrate having a front surface and a back surface; and an electronic component incorporated via a resin in a through hole penetrating the front surface and the back surface or in a concave portion opened on the front side or the back side. A method of manufacturing a substrate, comprising: a step of inserting an electronic component having an electrode protruding at least at one of an upper end and a lower end into a through hole or a concave portion; and embedding the electronic component in the through hole or the concave portion with a resin containing an inorganic filler. And embedding the resin, and polishing the surface of the resin to adjust the surface to expose the end face of the electrode.