JP3199637B2 - Method for manufacturing multilayer wiring board - Google Patents

Method for manufacturing multilayer wiring board

Info

Publication number
JP3199637B2
JP3199637B2 JP18192596A JP18192596A JP3199637B2 JP 3199637 B2 JP3199637 B2 JP 3199637B2 JP 18192596 A JP18192596 A JP 18192596A JP 18192596 A JP18192596 A JP 18192596A JP 3199637 B2 JP3199637 B2 JP 3199637B2
Authority
JP
Japan
Prior art keywords
circuit
insulating layer
wiring board
conductor circuit
conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP18192596A
Other languages
Japanese (ja)
Other versions
JPH1027959A (en
Inventor
昭彦 西本
桂 林
幸洋 平松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=16109308&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JP3199637(B2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP18192596A priority Critical patent/JP3199637B2/en
Publication of JPH1027959A publication Critical patent/JPH1027959A/en
Application granted granted Critical
Publication of JP3199637B2 publication Critical patent/JP3199637B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、例えば、多層配線
基板及び半導体素子収納用パッケージなどに適した多層
配線基板の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring board suitable for, for example, a multilayer wiring board and a package for accommodating a semiconductor element.

【0002】[0002]

【従来の技術】従来より、配線基板、例えば、半導体素
子を収納するパッケージに使用される多層配線基板とし
て、比較的高密度の配線が可能な多層セラミック配線基
板が多用されている。この多層セラミック配線基板は、
アルミナなどの絶縁基板と、その表面に形成されたWや
Mo等の高融点金属からなる配線導体とから構成される
もので、この絶縁基板の一部にキャビティが形成され、
このキャビティ内に半導体素子が収納され、蓋体によっ
てキャビティを気密に封止されるものである。
2. Description of the Related Art Conventionally, a multilayer ceramic wiring board capable of relatively high-density wiring has been frequently used as a wiring board, for example, a multilayer wiring board used for a package for housing a semiconductor element. This multilayer ceramic wiring board
It is composed of an insulating substrate such as alumina and a wiring conductor made of a high melting point metal such as W or Mo formed on the surface thereof. A cavity is formed in a part of the insulating substrate,
The semiconductor element is accommodated in the cavity, and the cavity is hermetically sealed by the lid.

【0003】ところが、このようなセラミック多層配線
基板を構成するセラミックスは、硬くて脆い性質を有す
ることから、製造工程または搬送工程において、セラミ
ックスの欠けや割れ等が発生しやすく、半導体素子の気
密封止性が損なわれることがあるために歩留りが低い等
の問題があった。また、焼結前のグリーンシートにメタ
ライズインクを印刷して、印刷後のシートを積層して焼
結させて製造されるが、その製造工程において、高温で
の焼成により焼成収縮が生じるために、得られる基板に
反り等の変形や寸法のばらつき等が発生しやすいという
問題があり、回路基板の超高密度化やフリップチップ等
のような基板の平坦度の厳しい要求に対して、十分に対
応できないという問題があった。
However, the ceramics constituting such a ceramic multilayer wiring board are hard and brittle, so that chipping or cracking of the ceramics is liable to occur in a manufacturing process or a transporting process. There is a problem that yield is low because stopping performance may be impaired. In addition, the metallized ink is printed on the green sheet before sintering, and the printed sheet is laminated and sintered.In the manufacturing process, firing at a high temperature causes firing shrinkage. There is a problem that deformation such as warpage and dimensional variation are likely to occur in the obtained substrate, and it sufficiently responds to strict requirements for ultra-high density circuit boards and flatness of substrates such as flip chips etc. There was a problem that it was not possible.

【0004】そこで、最近では、有機樹脂を含む絶縁性
基板表面に銅箔を接着した後、これをエッチングして微
細な導体回路を形成し、しかる後、この基板を複数枚積
層圧着して多層化した多層プリント配線基板が提案され
ている。また、このような多層配線プリント基板におい
ては、その強度を高めるために、有機樹脂に対して、球
状あるいは繊維状の無機質フィラーを分散させた基板も
提案されており、これらの複合材料からなる絶縁基板上
に多数の半導体素子を搭載したマルチチップモジュール
(MCM)等への適用も検討されている。
Therefore, recently, a copper foil is adhered to the surface of an insulating substrate containing an organic resin, and is then etched to form a fine conductor circuit. Multilayer printed wiring boards have been proposed. In addition, in order to increase the strength of such a multilayer wiring printed board, a board in which a spherical or fibrous inorganic filler is dispersed in an organic resin has been proposed. Application to a multi-chip module (MCM) in which a large number of semiconductor elements are mounted on a substrate is also being studied.

【0005】上記多層プリント配線基板の製造方法によ
れば、有機樹脂を含む絶縁性基板の表面には、銅箔の厚
みに相当する厚みの導体回路が形成されるために、この
絶縁性基板を複数枚積層して多層プリント配線基板とな
した場合、該多層プリント回路基板は、導体回路形成部
と非形成部とで厚みが異なるものとなりその表面は凹凸
な状態となる。そこで、前記有機樹脂を含む絶縁性基板
自体に若干の可塑性を持たせ、複数の絶縁性基板を積層
圧着して多層プリント配線基板とする際に、絶縁性基板
の導体回路に当接する部位を該導体回路の厚みに対応し
て塑性変形させることにより導体回路を絶縁性基板中に
埋入させ、多層プリント配線基板の表面に凹凸が形成さ
れないようにしている。
According to the method for manufacturing a multilayer printed wiring board, a conductor circuit having a thickness corresponding to the thickness of a copper foil is formed on the surface of an insulating substrate containing an organic resin. When a multilayer printed circuit board is formed by laminating a plurality of printed circuit boards, the multilayer printed circuit board has different thicknesses between the conductor circuit forming portion and the non-forming portion, and the surface thereof is uneven. Therefore, when the insulating substrate containing the organic resin itself is given some plasticity, and when a plurality of insulating substrates are laminated and pressed to form a multilayer printed wiring board, a portion of the insulating substrate that comes into contact with a conductor circuit is formed. The conductor circuit is buried in the insulating substrate by plastically deforming according to the thickness of the conductor circuit, so that no irregularities are formed on the surface of the multilayer printed wiring board.

【0006】[0006]

【発明が解決しようとする課題】最近では従来よりも更
に精細な導体回路を有する多層配線基板が求められるよ
うになっているが、このような超精細回路導体を有する
配線基板を上記のような従来法で作製すると、図2に示
すように、絶縁性基板11の表面に形成された所定厚み
の導体回路12の回路間に存在する凹部は、その上に積
層された若干の可塑性を有する絶縁性基板11の積層圧
着時の塑性変形のみでは完全に埋めることができず、最
終的に得られる多層プリント配線基板において導体回路
12の周辺で空隙13が形成され、該空隙13に水分等
が浸入すると、導体回路22間の絶縁性が劣化して回路
に短絡が発生したり、導体回路12が腐食してしまった
りする。しかも、絶縁性基板が積層圧着時に導体回路の
厚みに対応して十分に塑性変形できない場合、上層に形
成された回路も変形するために、下層の導体回路と上層
の導体回路が平面的にみて交差するような場合には、上
層の導体回路の変形が大きくなり、回路の断線を引き起
こすこともある。
Recently, there has been a demand for a multilayer wiring board having a finer conductive circuit than in the prior art. When manufactured by the conventional method, as shown in FIG. 2, the concave portion existing between the circuits of the conductor circuit 12 having a predetermined thickness formed on the surface of the insulating substrate 11 has a slightly plastic insulating layer laminated thereon. The plastic substrate 11 cannot be completely filled only by plastic deformation at the time of lamination and pressure bonding, and a void 13 is formed around the conductor circuit 12 in the finally obtained multilayer printed wiring board, and moisture and the like enter the void 13. Then, the insulation between the conductor circuits 22 deteriorates, and a short circuit occurs in the circuit, or the conductor circuit 12 is corroded. Moreover, if the insulating substrate cannot be sufficiently plastically deformed in accordance with the thickness of the conductor circuit during lamination and compression, the circuit formed in the upper layer is also deformed. In the case of crossing, the deformation of the upper-layer conductor circuit becomes large, and the circuit may be disconnected.

【0007】そのために、多層プリント配線基板を作製
する時に、各絶縁性基板の厚みを十分に大きくして下層
の導体回路による影響が上層の導体回路に及ばないよう
にするか、または導体回路が交差しないようにするなど
の対策が講じられているが、導体回路の配線密度が低下
し、多層プリント配線基板全体の容積が増える等の問題
が生じている。
For this reason, when manufacturing a multilayer printed wiring board, the thickness of each insulating substrate is made sufficiently large so that the influence of the lower conductive circuit does not affect the upper conductive circuit, or Although measures have been taken to avoid crossover, the wiring density of the conductor circuit has been reduced, and problems have arisen, such as an increase in the volume of the entire multilayer printed wiring board.

【0008】また、各絶縁性基板の可塑性を極めて大き
なものとなし、これにより各絶縁性基板を加圧積層する
際に各絶縁性基板を導体回路の厚みに対して十分に塑性
変形可能とし、各絶縁性基板間に空隙が形成されること
を防止するとともに多層プリント配線基板の表面が凹凸
となることを防止することも考えられるが、この場合、
可塑性を大きなものとすると絶縁性基板を形成する有機
樹脂同士の結合が極めて弱いものとなり、該絶縁性基板
に接着させた銅箔をエッチングして導体回路を形成する
際に、エッチング液により絶縁性基板が大きく侵されて
しまい、所定の多層プリント配線基板を得ることができ
ないという不都合が誘発される。
Further, the plasticity of each insulating substrate is made extremely large, whereby each insulating substrate can be sufficiently plastically deformed with respect to the thickness of the conductor circuit when each insulating substrate is laminated under pressure. It is possible to prevent the formation of voids between the insulating substrates and to prevent the surface of the multilayer printed wiring board from becoming uneven, but in this case,
When the plasticity is large, the bonding between the organic resins forming the insulating substrate becomes extremely weak, and when the copper foil adhered to the insulating substrate is etched to form a conductor circuit, the insulating property is increased by an etchant. The substrate is greatly eroded, causing a disadvantage that a predetermined multilayer printed wiring board cannot be obtained.

【0009】尚、シリコンチップの配線基板への実装方
法がワイヤーボンディング法からフリップチップ法に変
わってくるにつれ基板表面の平坦度の要求値が厳しくな
っている。この場合、導体回路による凹凸は時に致命的
な欠陥となり、シリコンチップの実装さえ不可能になる
場合がある。このような回路の超精細はさらに進むと考
えられ、それらの要求に応えうる超精細の多層配線基板
の製造技術の完成が待たれている。
As the method of mounting a silicon chip on a wiring substrate changes from the wire bonding method to the flip chip method, the required value of the flatness of the substrate surface is becoming stricter. In this case, unevenness due to the conductor circuit sometimes becomes a fatal defect, and even mounting of a silicon chip may not be possible. It is considered that the ultra-fineness of such a circuit will be further advanced, and there is a need for the completion of a technology for manufacturing an ultra-fine multilayer wiring board that can meet those requirements.

【0010】従って、本発明は、叙上のような回路の超
精細化の要求に対応してなされたもので、多層配線基板
を構成するの各基板に形成された導体回路によって生じ
る凹凸をなくすとともに各基板間に空隙の発生すること
のない多層配線基板の製造方法を提供するものである。
SUMMARY OF THE INVENTION Accordingly, the present invention has been made in response to the above-mentioned demand for ultra-fine circuits, and eliminates unevenness caused by conductor circuits formed on each substrate of a multilayer wiring board. It is another object of the present invention to provide a method for manufacturing a multilayer wiring board in which no gap is generated between the substrates.

【0011】[0011]

【課題を解決するための手段】本発明の配線基板の製造
方法は、表面に金属から成る導体回路が形成された転写
シートと、少なくとも熱硬化性有機樹脂を含み、先端が
半球状で直径300μmの針を100gfの力で侵入さ
せたときの針侵入深さが室温で30μm以上である半硬
化状態の絶縁層とを準備する工程と、前記転写シートに
形成された導体回路と半硬化状態の絶縁層とを30〜1
30℃の温度にて、10kgf/cm2以上で圧接して
導体回路を絶縁層に転写埋入させる工程と、前記導体回
路が転写埋入された絶縁層から転写シートを除去し絶縁
層の表面に導体回路が埋入された回路基板を得る工程
と、前記回路基板を複数枚積層した後、加熱して完全に
硬化する工程とを具備することを特徴とするものであ
り、転写シート上に形成された導体回路を半硬化状態の
絶縁層に圧接することにより絶縁層の表面に導体回路が
形成されることから、導体回路を半硬化状態の絶縁層上
でエッチングにより形成する必要はなく、また、半硬化
状態の絶縁層を極めて可塑性の大きなものとして、導体
回路を絶縁層中に容易、且つ十分に埋入させることがで
きる。
According to a method of manufacturing a wiring board of the present invention, a transfer sheet having a conductive circuit made of metal on a surface thereof, at least a thermosetting organic resin, a hemispherical tip and a diameter of 300 μm are provided. A step of preparing a semi-cured insulating layer having a needle penetration depth of 30 μm or more at room temperature when the needle is penetrated by a force of 100 gf, and a step of preparing a semi-cured state with the conductor circuit formed on the transfer sheet. 30-1 with insulating layer
A step of press-contacting the conductor circuit into the insulating layer at a temperature of 30 ° C. at a pressure of 10 kgf / cm 2 or more, and removing the transfer sheet from the insulating layer in which the conductor circuit is transferred and embedded; A step of obtaining a circuit board in which a conductor circuit is embedded, and a step of laminating a plurality of the circuit boards, and then heating and completely curing the circuit board. Since the conductive circuit is formed on the surface of the insulating layer by pressing the formed conductive circuit against the semi-cured insulating layer, it is not necessary to form the conductive circuit by etching on the semi-cured insulating layer, In addition, the semi-cured insulating layer is made to have extremely high plasticity, so that the conductor circuit can be easily and sufficiently embedded in the insulating layer.

【0012】[0012]

【発明の実施の形態】以下、本発明を図1をもとに説明
する。図1は、本発明の多層配線基板の製造方法を説明
するための工程毎の断面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIG. FIG. 1 is a cross-sectional view for explaining a method of manufacturing a multilayer wiring board according to the present invention.

【0013】本発明の多層配線基板の製造方法によれ
ば、図1(a)に示すように、まず、表面に導体回路2
が形成された転写シート1と、少なくとも有機樹脂を含
む半硬化状態の絶縁層3を準備する。
According to the method for manufacturing a multilayer wiring board of the present invention, first, as shown in FIG.
Is prepared, and a semi-cured insulating layer 3 containing at least an organic resin is prepared.

【0014】前記転写シート1表面に形成された導体回
路2は、例えば銅、アルミニウム、金、銀の群から選ば
れる少なくとも1種、または2種以上の合金からなるこ
とが望ましく、特に、銅、または銅を含む合金が最も望
ましい。場合によっては、回路の抵抗調整のためにNi
−Cr合金などの高抵抗の金属を混合または合金化して
もよい。
The conductor circuit 2 formed on the surface of the transfer sheet 1 is preferably made of at least one or two or more alloys selected from the group consisting of copper, aluminum, gold and silver. Or an alloy containing copper is most desirable. In some cases, Ni may be used to adjust the resistance of the circuit.
A high resistance metal such as a Cr alloy may be mixed or alloyed.

【0015】この導体回路2は、所望の金属箔をエッチ
ング法またはレーザー加工して形成したり、メッキ法に
よっても形成できる。例えば、エッチング法では、前記
転写シート1の表面に上記導体回路形成金属からなる金
属箔を一面に接着した後、前記金属箔上にフォトレジス
ト、スクリーン印刷等の方法で導体回路状にレジストを
形成し、不要な部分をエッチング除去することで所望の
導体回路2を得る。
The conductive circuit 2 can be formed by etching or laser processing a desired metal foil, or by plating. For example, in the etching method, after a metal foil made of the above-described conductor circuit forming metal is adhered to the entire surface of the transfer sheet 1, a photoresist is formed on the metal foil by a method such as screen printing to form a resist in a conductor circuit shape. Then, unnecessary conductor portions 2 are obtained by removing unnecessary portions by etching.

【0016】この時、上記レジストは、一般には、金属
箔の不要部分をエッチング除去した後にレジスト除去液
等により取り除き、洗浄する工程が必要であるが、上記
レジストを後述する絶縁層3と同一材料で、有機樹脂を
含む、例えば有機樹脂と無機質フィラーからなる絶縁性
材料から構成すれば、レジストの除去等を行う必要がな
いため、工程の簡略化を図ることができる上で有利であ
る。
At this time, the resist generally requires a step of removing unnecessary portions of the metal foil by etching and then removing the resist with a resist removing solution or the like, and washing the resist. The resist is made of the same material as the insulating layer 3 described later. If an insulating material containing an organic resin, for example, an organic resin and an inorganic filler is used, there is no need to remove the resist, which is advantageous in that the process can be simplified.

【0017】一方、前記絶縁層3は、少なくとも有機樹
脂を含む絶縁材料からなるもので、半硬化状態のもので
あり、有機樹脂としては例えば、PPE(ポリフェニレ
ンエーテル)、BTレジン(ビスマレイミドトリアジ
ン)、エポキシ樹脂、ポリイミド樹脂、フッ素樹脂、フ
ェノール樹脂等の樹脂が望ましく、とりわけ原料として
室温で液体の熱硬化性樹脂であることが望ましい。
On the other hand, the insulating layer 3 is made of an insulating material containing at least an organic resin and is in a semi-cured state. Examples of the organic resin include PPE (polyphenylene ether) and BT resin (bismaleimide triazine). , An epoxy resin, a polyimide resin, a fluororesin, a phenolic resin, and the like are desirable, and a thermosetting resin that is liquid at room temperature as a raw material is particularly desirable.

【0018】また、絶縁層3中には、絶縁層3あるいは
配線基板全体としての強度を高めるために、有機樹脂に
対して無機質フィラーを複合化させることが望ましい。
有機樹脂と複合化される無機質フィラーとしては、Si
2 、Al2 3 、ZrO2、TiO2 、AlN、Si
C、BaTiO3 、SrTiO3 、ゼオライト、CaT
iO3 、ほう酸アルミニウム等の公知の材料が使用でき
る。フィラーの形状は平均粒径が20μm以下、特に1
0μm以下、最適には7μm以下の略球形状の粉末の
他、平均アスペクト比が2以上、特に5以上の繊維状の
ものや、織布物も使用できる。
In the insulating layer 3, it is desirable to compound an inorganic filler with an organic resin in order to increase the strength of the insulating layer 3 or the entire wiring board.
As the inorganic filler compounded with the organic resin, Si
O 2 , Al 2 O 3 , ZrO 2 , TiO 2 , AlN, Si
C, BaTiO 3 , SrTiO 3 , zeolite, CaT
Known materials such as iO 3 and aluminum borate can be used. The filler has an average particle size of 20 μm or less, particularly 1 μm.
In addition to substantially spherical powder having a particle size of 0 μm or less, optimally 7 μm or less, a fibrous material having an average aspect ratio of 2 or more, particularly 5 or more, or a woven fabric can be used.

【0019】なお、有機樹脂と無機質フィラーとの複合
材料においては、有機樹脂:無機質フィラーとは、体積
比率で15:85〜50:50の比率で複合化されるの
が適当である。
In the composite material of an organic resin and an inorganic filler, it is appropriate that the organic resin and the inorganic filler are compounded in a volume ratio of 15:85 to 50:50.

【0020】次に、図1(b)に示すように、前記上面
に導体回路2が形成された転写シート1と絶縁層3とを
重ねるとともにこれらを従来周知のプレス装置を用いて
上下から圧接し、導体回路2を絶縁層3中に転写埋入さ
せる。
Next, as shown in FIG. 1 (b), the transfer sheet 1 having the conductor circuit 2 formed on the upper surface and the insulating layer 3 are overlapped, and these are pressed from above and below using a conventionally known press device. Then, the conductor circuit 2 is transferred and embedded in the insulating layer 3.

【0021】このとき、絶縁層3は、先端が半球状で直
径300μmの針を100gfの力で侵入させたときの
針侵入深さが10μm以上、好ましくは30μm以上、
最適には50μm以上の柔らかさを有するものであっ
て、前記針浸入深さが10μm未満であると導体回路2
を絶縁層3中に十分に埋入させることが困難となる。
At this time, the insulation layer 3 has a needle penetration depth of 10 μm or more, preferably 30 μm or more when a needle having a hemispherical tip and a diameter of 300 μm is penetrated by a force of 100 gf.
Optimally, it has a softness of 50 μm or more, and if the needle penetration depth is less than 10 μm, the conductor circuit 2
In the insulating layer 3 becomes difficult.

【0022】尚、前記絶縁層3を前記針侵入深さが10
μm以上の柔らかさとするには、絶縁層3中に溶剤や可
塑剤を適量含有させる方法や、絶縁層3を加熱軟化させ
る方法が採用され得る。
The insulating layer 3 has a needle penetration depth of 10
In order to achieve the softness of not less than μm, a method of including an appropriate amount of a solvent or a plasticizer in the insulating layer 3 or a method of heating and softening the insulating layer 3 can be adopted.

【0023】更にこのときの圧接圧力は10kgf/c
2以上であることが必要である。前記圧接圧力が10
kgf/cm2未満の場合には、回路導体2を絶縁層3
中に十分に埋入させることが困難となる。また、圧接す
る時の温度は30〜130℃が良い。この温度が30℃
より低いと絶縁層3の硬度が高く、導体回路2が十分に
埋入できない場合があり、130℃より高いと絶縁層3
の変形が大きくなり、導体回路2上を樹脂が被覆し、後
述する回路基板に設けたバイアホール内に充填される導
電性インクとの接続信頼性が低下する場合がある。
The pressing pressure at this time is 10 kgf / c
m 2 or more. When the pressing pressure is 10
In the case of less than kgf / cm 2 , the circuit conductor 2 is
It is difficult to bury them sufficiently. The temperature at the time of pressure contact is preferably 30 to 130 ° C. This temperature is 30 ° C
If it is lower, the hardness of the insulating layer 3 is high and the conductor circuit 2 may not be sufficiently embedded.
Of the conductive circuit 2 may be covered with a resin, and the reliability of connection with the conductive ink filled in via holes provided in a circuit board, which will be described later, may be reduced.

【0024】上記のようにして絶縁層3中に導体回路2
を埋め込んだ後に、絶縁層3から転写シート1を剥がす
ことにより、図1(c)に示すように、導体回路2の表
面と絶縁層3の表面とが同一平面上に存在する平滑性に
優れた単層の回路基板4を作製することができる。
As described above, the conductor circuit 2 is provided in the insulating layer 3.
After embedding, the transfer sheet 1 is peeled from the insulating layer 3 so that the surface of the conductor circuit 2 and the surface of the insulating layer 3 are excellent in smoothness as shown in FIG. Thus, a single-layer circuit board 4 can be manufactured.

【0025】そして、図1(a)〜(c)のようにして
複数の回路基板を作製し、所望により打ち抜き法やレー
ザーを用いた方法でバイアホールを形成し、導電性樹脂
や金属フィラーを含有する導電性インク等をバイアホー
ル内に充填する。そして、得られた回路基板4を図1
(d)に示すように、所望の枚数を所定位置に積層し加
圧もしくは加熱して密着し一体化して多層配線基板を作
製することができる。
Then, a plurality of circuit boards are manufactured as shown in FIGS. 1A to 1C, and via holes are formed by a punching method or a method using a laser if desired, and a conductive resin or a metal filler is added. The via holes are filled with conductive ink or the like. Then, the obtained circuit board 4 is shown in FIG.
As shown in (d), a desired number of sheets can be laminated at a predetermined position, closely adhered by pressing or heating, and integrated to produce a multilayer wiring board.

【0026】かかる態様においては、転写シート1表面
に形成された導体回路2の表面は、絶縁層3との界面と
なるもので、導体回路2の絶縁層3への密着性を決定す
る要因である。かかる観点から、導体回路2の絶縁層3
との密着強度を高める上で、転写シート1表面に形成さ
れる金属箔、言い換えれば導体回路2の表面粗さは、
0.1μm以上、特に0.3μm〜3μm、最適には
0.3〜1.5μmであるのがよい。
In such an embodiment, the surface of the conductor circuit 2 formed on the surface of the transfer sheet 1 serves as an interface with the insulating layer 3, and is a factor that determines the adhesion of the conductor circuit 2 to the insulating layer 3. is there. From this point of view, the insulating layer 3 of the conductor circuit 2
The metal foil formed on the surface of the transfer sheet 1, in other words, the surface roughness of the conductive circuit 2 is
The thickness is preferably 0.1 μm or more, particularly 0.3 μm to 3 μm, and most preferably 0.3 to 1.5 μm.

【0027】このように、本発明の多層配線基板の製造
方法によれば、1層毎の回路基板において導体回路の表
面と絶縁層との表面が同一平面に存在するか、または導
体回路が絶縁性基板内に何ら空隙の発生なく完全に埋め
込まれているために、従来のような導体回路による凹凸
の発生がなく、従来、回路基板の積層時に生じていた空
隙による回路の断線や変形による精度の劣化を防止する
ことができる。これにより、今後の半導体の主要な実装
形式と考えられているフリップチップ方式の実装に適し
た高精度な表面平坦度を有する高密度多層配線基板が得
られる。
As described above, according to the method for manufacturing a multilayer wiring board of the present invention, the surface of the conductive circuit and the surface of the insulating layer are present on the same plane in each circuit board of each layer, or the conductive circuit is insulated. Since it is completely buried without any voids in the flexible substrate, there is no unevenness due to the conductive circuit as in the past, and the accuracy due to the disconnection and deformation of the circuit due to the voids that occurred in the past when laminating circuit boards Degradation can be prevented. As a result, a high-density multilayer wiring board having high-precision surface flatness suitable for flip-chip mounting, which is considered to be the main mounting format of semiconductors in the future, can be obtained.

【0028】[0028]

【実施例】ポリエチレンテレフタレート(PET)樹脂
からなる転写シートの表面に接着剤を塗布して粘着性を
もたせ、厚さ12μm、表面粗さ0.8μmの銅箔を一
面に接着した。その後、該導体箔上面に後述する絶縁層
と同一組成のスラリーからなるレジストを導体回路に対
応したパターンに形成した後、これを塩化第二鉄溶液中
に浸漬して導体箔の非パターン部をエッチング除去して
導体配線を有する転写シートを得た。なお、作製した回
路は、導体回路の線幅が100μm、配線と配線との間
隔が100μm以下の微細なパターンである。
EXAMPLE An adhesive was applied to the surface of a transfer sheet made of polyethylene terephthalate (PET) resin to impart tackiness, and a copper foil having a thickness of 12 μm and a surface roughness of 0.8 μm was adhered to one surface. Thereafter, a resist made of a slurry having the same composition as the insulating layer described later is formed on the upper surface of the conductor foil in a pattern corresponding to the conductor circuit, and this is immersed in a ferric chloride solution to remove the non-pattern portion of the conductor foil. After the removal by etching, a transfer sheet having conductor wiring was obtained. The manufactured circuit is a fine pattern in which the line width of the conductor circuit is 100 μm and the distance between the wirings is 100 μm or less.

【0029】一方、絶縁性スラリーとして、ポリイミド
樹脂35体積%と、無機質フィラーとして球状シリカを
65体積%の割合で混合し、この混合物にメチルエチル
ケトンからなる溶媒を加えてミキサーによって十分に混
合して粘度2000ポイズのスラリーを調製した。
On the other hand, 35% by volume of a polyimide resin as an insulating slurry and 65% by volume of spherical silica as an inorganic filler are mixed, a solvent composed of methyl ethyl ketone is added to this mixture, and the mixture is sufficiently mixed by a mixer to obtain a viscosity. A 2000 poise slurry was prepared.

【0030】そして、このスラリーをキャリアシート上
に、ドクターブレード法により125μmの厚みで流し
込んだ後、110℃−10分加熱処理してスラリー中の
溶媒を一部除去して半硬化させ、しかる後、これをキャ
リアシートから剥離して半硬化状態の絶縁層を得た。こ
のとき、絶縁層は、先端が半球状で直径300μmの針
を100gfの力で侵入させたときの針侵入深さが50
μmであり、またこれに含有される溶媒の量は、1.8
重量%であった。
Then, the slurry is poured into a carrier sheet at a thickness of 125 μm by a doctor blade method, and then subjected to a heat treatment at 110 ° C. for 10 minutes to partially remove the solvent in the slurry and semi-cured. This was peeled from the carrier sheet to obtain a semi-cured insulating layer. At this time, the insulating layer has a needle penetration depth of 50 μm when a needle having a hemispherical tip and a diameter of 300 μm is penetrated by a force of 100 gf.
μm, and the amount of solvent contained therein is 1.8 μm.
% By weight.

【0031】次に前記半硬化状態の絶縁層を導体回路が
形成された転写シート上に重ね、これを真空積層装置に
より30kgf/cm2 の圧力、50℃の温度で転写シ
ート上の導体回路を半硬化状態の絶縁層中に転写埋入さ
せ、しかる後、前記絶縁層から転写シートを剥離して表
面に導体回路を有する絶縁基板を得た。このとき、導体
回路は絶縁層中にほぼ完全に埋入され、導体回路の表面
と絶縁層の表面とは実質的に同一平面上となった。
Next, the semi-cured insulating layer is superimposed on the transfer sheet on which the conductor circuit is formed, and the conductor circuit on the transfer sheet is pressed by a vacuum laminator at a pressure of 30 kgf / cm 2 and a temperature of 50 ° C. The transfer sheet was transferred and embedded in the semi-cured insulating layer, and then the transfer sheet was peeled off from the insulating layer to obtain an insulating substrate having a conductor circuit on the surface. At this time, the conductor circuit was almost completely buried in the insulating layer, and the surface of the conductor circuit and the surface of the insulating layer were substantially coplanar.

【0032】同様にして厚さ125μmの8枚の配線基
板を作製した後、レーザーによりバイアホールを形成し
そのホール内にCu−Ag合金粉末を含む銅ペーストを
充填し、そしてこれらを位置合わせして積層し50kg
/cm2 程度の圧力、50℃の温度で圧着して200℃
−5時間加熱処理して完全硬化させて多層配線基板を作
製した。
Similarly, after eight wiring boards having a thickness of 125 μm were formed, via holes were formed by laser, and the holes were filled with a copper paste containing a Cu—Ag alloy powder, and these were aligned. 50kg
/ Cm 2 at a pressure of 50 ℃
Heat treatment was carried out for -5 hours to completely cure, thereby producing a multilayer wiring board.

【0033】得られた多層配線基板に対して、断面にお
ける配線回路形成付近を観察した結果、空隙は全く認め
られず、また、各配線の導通テストを行った結果、何ら
配線の断線は認められなかった。
As a result of observing the vicinity of the formation of the wiring circuit in the cross section of the obtained multilayer wiring board, no void was recognized, and as a result of conducting a continuity test of each wiring, no disconnection of the wiring was recognized. Did not.

【0034】[0034]

【発明の効果】以上詳述したとおり、本発明の多層配線
基板の製造方法によれば、一層の回路基板において導体
回路による凹凸が全くないために、従来、回路基板の積
層時に生じていた空隙による回路の断線や変形による精
度の劣化を防止することができる。これにより、今後の
半導体の主要な実装形式と考えられているフリップチッ
プ方式の実装に適した高精度な表面平坦度を有する高密
度多層配線基板が得られる。
As described above in detail, according to the method for manufacturing a multilayer wiring board of the present invention, since there is no unevenness due to the conductor circuit in one layer of the circuit board, the gap which has conventionally been generated when the circuit boards are laminated is obtained. This can prevent the accuracy from deteriorating due to disconnection or deformation of the circuit due to the above. As a result, a high-density multilayer wiring board having high-precision surface flatness suitable for flip-chip mounting, which is considered to be the main mounting format of semiconductors in the future, can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の製造方法の第1の態様の工程を説明す
るための図である。
FIG. 1 is a view for explaining steps of a first embodiment of the manufacturing method of the present invention.

【図2】従来の方法による多層配線基板の構造を説明す
るための図である。
FIG. 2 is a diagram for explaining a structure of a multilayer wiring board according to a conventional method.

【符号の説明】[Explanation of symbols]

1・・転写シート 2・・導体回路 3・・絶縁層 4・・回路基板 1. Transfer sheet 2. Conductor circuit 3. Insulating layer 4. Circuit board

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平3−270094(JP,A) 特開 平5−90763(JP,A) 特開 平7−297522(JP,A) (58)調査した分野(Int.Cl.7,DB名) H05K 3/46 H05K 3/20 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-3-27094 (JP, A) JP-A-5-90763 (JP, A) JP-A-7-297522 (JP, A) (58) Field (Int.Cl. 7 , DB name) H05K 3/46 H05K 3/20

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】表面に金属から成る導体回路が形成された
転写シートと、少なくとも熱硬化性有機樹脂を含み、先
端が半球状で直径300μmの針を100gfの力で侵
入させたときの針侵入深さが室温で30μm以上である
半硬化状態の絶縁層とを準備する工程と、前記転写シー
トに形成された導体回路と半硬化状態の絶縁層とを30
〜130℃の温度にて、10kgf/cm2以上で圧接
して導体回路を絶縁層に転写埋入させる工程と、前記導
体回路が転写埋入された絶縁層から転写シートを除去し
絶縁層の表面に導体回路が埋入された回路基板を得る工
程と、前記回路基板を複数枚積層した後、加熱して完全
に硬化する工程とを具備することを特徴とする多層配線
基板の製造方法。
1. A transfer sheet having a conductive circuit made of metal formed on a surface thereof, and a needle penetrating when a needle having a hemispherical tip and a diameter of 300 μm and having a diameter of 300 μm is penetrated by a force of 100 gf and containing at least a thermosetting organic resin. Preparing a semi-cured insulating layer having a depth of not less than 30 μm at room temperature, and contacting the conductive circuit formed on the transfer sheet with the semi-cured insulating layer by 30 minutes.
A step of pressing and embedding a conductor circuit in an insulating layer at a temperature of about 130 ° C. at a pressure of 10 kgf / cm 2 or more; and removing a transfer sheet from the insulating layer in which the conductor circuit is transferred and embedded to form an insulating layer. A method for manufacturing a multilayer wiring board, comprising: a step of obtaining a circuit board having a conductor circuit embedded in a surface thereof; and a step of heating and completely curing the circuit board after laminating a plurality of the circuit boards.
【請求項2】前記絶縁層が無機質フィラーを含有するこ
とを特徴とする請求項1記載の多層配線基板の製造方
法。
2. The method according to claim 1, wherein the insulating layer contains an inorganic filler.
【請求項3】前記導体回路が、銅、アルミニウム、金、
銀のうちから選ばれる少なくとも1種以上からなる請求
項1に記載の多層配線基板の製造方法。
3. The conductive circuit according to claim 1, wherein said conductive circuit is made of copper, aluminum, gold,
2. The method for manufacturing a multilayer wiring board according to claim 1, comprising at least one kind selected from silver.
JP18192596A 1996-07-11 1996-07-11 Method for manufacturing multilayer wiring board Expired - Fee Related JP3199637B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18192596A JP3199637B2 (en) 1996-07-11 1996-07-11 Method for manufacturing multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18192596A JP3199637B2 (en) 1996-07-11 1996-07-11 Method for manufacturing multilayer wiring board

Publications (2)

Publication Number Publication Date
JPH1027959A JPH1027959A (en) 1998-01-27
JP3199637B2 true JP3199637B2 (en) 2001-08-20

Family

ID=16109308

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18192596A Expired - Fee Related JP3199637B2 (en) 1996-07-11 1996-07-11 Method for manufacturing multilayer wiring board

Country Status (1)

Country Link
JP (1) JP3199637B2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6374733B1 (en) 1998-12-07 2002-04-23 Matsushita Electric Industrial Co., Ltd. Method of manufacturing ceramic substrate
JP4587576B2 (en) * 2001-01-30 2010-11-24 京セラ株式会社 Multilayer wiring board
KR100671541B1 (en) * 2001-06-21 2007-01-18 (주)글로벌써키트 A manufacturing method of printed circuit embedded board
JP4547876B2 (en) * 2003-07-25 2010-09-22 株式会社村田製作所 Manufacturing method of multilayer ceramic electronic component
US7893359B2 (en) 2005-09-19 2011-02-22 Industrial Technology Research Institute Embedded capacitor core having a multiple-layer structure
KR100771470B1 (en) 2006-09-29 2007-10-30 삼성전기주식회사 Stamper and pcb manufacturing method using it
KR100836653B1 (en) 2006-10-25 2008-06-10 삼성전기주식회사 Circuit board and method for manufacturing thereof

Also Published As

Publication number Publication date
JPH1027959A (en) 1998-01-27

Similar Documents

Publication Publication Date Title
KR100478984B1 (en) Insulation sheet and multi-layer wiring substrate and production processes thereof
EP1804562B1 (en) Composite multilayer substrate and its manufacturing method
US6939738B2 (en) Component built-in module and method for producing the same
EP1250033B1 (en) Printed circuit board and electronic component
US20070117338A1 (en) Via array capacitor, wiring board incorporating a via array capacitor, and method of manufacturing the same
JP2002043468A (en) Obverse and reverse conduction board and its manufacturing method
JP2005072328A (en) Multilayer wiring board
JP3441368B2 (en) Multilayer wiring board and manufacturing method thereof
JP3037662B2 (en) Multilayer wiring board and method of manufacturing the same
JP3199637B2 (en) Method for manufacturing multilayer wiring board
JP3085658B2 (en) Wiring board and manufacturing method thereof
JP3071764B2 (en) Film with metal foil and method of manufacturing wiring board using the same
JP3085649B2 (en) Transfer sheet and method of manufacturing wiring board using the same
JPH09293968A (en) Method of manufacturing multilayer wiring substrate
JP2001015872A (en) Wiring board insulating sheet and manufacture of wiring board using the same
JPH10107445A (en) Multi-layered wiring board and manufacture thereof
JPH11103165A (en) Multilayered wiring board and its manufacture
JP4632514B2 (en) Wiring board and manufacturing method thereof
JP4841234B2 (en) Manufacturing method of wiring substrate with built-in via array capacitor
JP3758811B2 (en) Transfer sheet and wiring board manufacturing method using the same
JP3610156B2 (en) Manufacturing method of multilayer wiring board
JP2004095753A (en) Method for manufacturing multi-layer ceramic substrate
JP3232002B2 (en) Wiring board
JP4974421B2 (en) Manufacturing method of multilayer wiring board
JPH1174641A (en) Multilayer wiring board

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090615

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090615

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100615

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110615

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120615

Year of fee payment: 11

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130615

Year of fee payment: 12

LAPS Cancellation because of no payment of annual fees