JP2002100636A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of conventional high speed switching transistors to which Pt is introduced from the rear plane of a substrate due to the fact that Pt is easily gettered by the N+ type region in a semiconductor element region and the problem of low productivity compared with that of a general transistor, due to the Pt introduction process and a pretreatment for the introduction from the rear plane. SOLUTION: In this invention, Pt as well as an impurity for forming N+ regions in the semiconductor element region are diffused simultaneously from the front surface of the substrate, and by controlling subsequent baking conditions, Pt gettered by N+ regions can be emitted. Hereby, the process of diffusing Pt from the rear plane can be eliminated, which can cut down nearly one fourth of a manufacturing process of the semiconductor device, and additionally, since the emitted quantity of Pt into the substrate can be controlled by the baking conditions, it can considerably contribute to the productivity improvement.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device capable of improving productivity by reducing the number of manufacturing steps for a small-signal high-speed switching transistor.

[0002]

Conventionally, in a high-speed switching circuit to deal with GH _Z band it was using the compound semiconductor device. However, since compound semiconductor elements have different manufacturing processes and technologies and are expensive, development of silicon semiconductor elements that are highly mass-producible and can be manufactured on existing manufacturing lines is desired.

In particular, in a small signal high-speed switching transistor, platinum (Pt) serving as a lifetime killer is introduced from the back surface of a semiconductor substrate after a semiconductor element region is formed to control the switching time.

FIGS. 9 to 15 show a method of manufacturing a conventional small signal NPN type high speed switching transistor in detail.

The NPN high-speed switching transistor forms a semiconductor region by forming a reverse conductivity type base region on the surface of a semiconductor substrate of one conductivity type and forming an emitter region of one conductivity type on the surface of the base region. The method includes a process, a process of introducing a lifetime killer from the back surface of the semiconductor substrate, and a process of forming an electrode.

FIG. 9 shows a process of forming a reverse conductivity type base region on the surface of a semiconductor substrate of one conductivity type. An N-type epitaxial layer is stacked on an N ⁺ -type silicon semiconductor substrate to form a collector region 21, and the semiconductor substrate is exposed to a steam atmosphere to form an oxide film 22. The oxide film 22 on the planned base region is removed by etching to expose the semiconductor substrate, and P-type impurities (boron) are ion-implanted.

[0007] A CVD oxide film 23 is deposited on the entire surface by a CVD method, and boron is diffused to form a base region 24.

FIGS. 10 and 11 show a process of forming a semiconductor element region by forming an emitter region on the surface of a base region.

FIG. 10 shows that the oxide film 22 on the surface of the semiconductor substrate is removed by etching to form a predetermined emitter region and a predetermined annular ring, thereby exposing a part of the outermost surfaces of the base region 24 and the collector region 21. Then, impurities of one conductivity type (phosphorus oxychloride) are attached.

FIG. 11 is a view showing a state in which the ring lath layer on the surface is removed and C
A CVD oxide film 23 is formed by the VD method, and phosphorus oxychloride is diffused into the base region 24 to form an emitter region 26, and simultaneously diffused into the collector region 21 to form an annular ring 27.

FIGS. 12 and 13 show a process of introducing a lifetime killer from the back surface of the semiconductor substrate.

FIG. 12 shows that the back surface of the semiconductor substrate is back-ground-ground to reduce the thickness of the semiconductor substrate to approximately half, and then a resin-based protective film 28 for protection is applied to the front surface of the semiconductor substrate to chemically etch the back surface of the semiconductor substrate. Flattening.

FIG. 13 shows a resin-based protective film 2 on the surface of a semiconductor substrate.
8 is removed, and the oxide film on the back surface formed at that time is removed by plasma etching. A liquid dopant source containing Pt that becomes a lifetime killer (trade name: Pt
-OCD, manufactured by Tokyo Ohka Kogyo Co., Ltd.) 29 is applied to the back surface of the semiconductor substrate by spin-on, and heat-treated. This thermal oxidation causes Pt to diffuse throughout the semiconductor substrate.

FIG. 14 shows a baking process. A resist film 30 is applied on the surface of the semiconductor substrate for protection, and the Pt glass layer on the back surface of the semiconductor substrate is removed. Thereafter, the resist film 30 on the surface of the semiconductor substrate is removed, and the oxide film 22 is lightly etched by flash etching to expose a clean oxide film 22 surface. After that, moisture is completely removed by flash etching by baking to improve the resist adhesion in the next step.

FIG. 15 shows the formation of the electrodes. Base area 2
Part 4 of the oxide film 22 on the surface of the semiconductor substrate is removed to make contact between the semiconductor substrate 4 and the emitter region. After a wiring metal such as Al (1.1 μm) is sequentially deposited on the entire surface by vacuum evaporation, etching is performed to obtain a desired wiring electrode shape, thereby forming a base electrode 33 and an emitter electrode 32.

Further, after back grinding the semiconductor substrate to a desired finished thickness, NiCr / AuSb is deposited on the back surface of the semiconductor substrate in order to obtain ohmic properties of the collector,
Heat treatment is performed to provide a collector electrode 34.

FIG. 16 shows a method of manufacturing a conventional small-signal PNP-type high-speed switching transistor, focusing on the formation of a semiconductor element region. The same components as those of the NPN transistor have the same reference numerals.

A P-type epitaxial layer is stacked on a P ⁺ -type silicon semiconductor substrate to form a collector region 21. An oxide film 22 on a predetermined base region is removed by etching to expose the semiconductor substrate, and an N-type impurity (phosphorus) is formed. 2), a CVD oxide film 23 is deposited on the entire surface by a CVD method, and phosphorus is diffused to form a base region 24.

The oxide film 22 on the surface of the semiconductor substrate is removed by etching to remove the base region 24 and the collector region 21.
Part of the surface is exposed, and impurities of one conductivity type (trade name:
PBF, manufactured by Tokyo Ohka Kogyo Co., Ltd.). The ring oxide layer on the surface is removed, and the CVD oxide film 2 is formed by the CVD method.
3 is formed, and PBF is diffused into the base region 24 to form the emitter region 26, and simultaneously diffused into the collector region 21 to form the annular ring 27.

Further, a part of the surface of the base region 24 is exposed, phosphorus oxychloride is adhered and diffused, and a base contact region 30 for reducing contact resistance is provided to form a semiconductor element region.

After the formation of the semiconductor element region, the back surface of the semiconductor substrate is back-ground-ground to prepare the back surface of the semiconductor substrate in the same manner as in the case of the NPN type transistor. And heat-treated. This thermal oxidation causes Pt to diffuse throughout the semiconductor substrate.

Thereafter, the Pt glass layer on the back surface is removed, contact holes are provided in the emitter region 26 and the base contact region 30, and the emitter electrode 32 and the base electrode 33 are formed on the front surface. After back grinding the back surface of the semiconductor substrate to a desired finished thickness, a collector electrode 34 is formed by vacuum evaporation.

The lifetime killer Pt is a base-
Controls the movement of electrons between collectors. Transistor is O
Pt captures a small amount of electrons that move immediately after switching from N to OFF, so that ON / OFF is sharpened and control is performed to enable high-speed switching.

Further, the reason why Pt is introduced from the back surface of the semiconductor substrate after the formation of the semiconductor element region is that Pt is easily gettered to the N-type region, and N ⁺
The emitter region and annular ring that are the mold regions
This is because a base contact region is provided in a P-type transistor, and when introduced from the surface of a semiconductor substrate, it is gettered in an N ⁺ -type region before diffusing into the entire substrate.

[0025]

In a high-speed switching transistor, a liquid dopant source containing Pt is applied to the back surface of a semiconductor substrate by spin-on, and heat treatment is performed to diffuse Pt into the semiconductor substrate to control the switching time.

Pt captures a small amount of electrons moving between the base and the collector during switching of the transistor, so that ON / OFF is sharpened and the switching time can be controlled.

The reason for introducing Pt from the back surface of the semiconductor substrate is that Pt is easily gettered in the N-type region and Nt is
This is because an emitter region or an annular ring which is an N ⁺ type region is provided in a PN type transistor, and a base contact region is provided in a PNP type transistor.

As described above, the small-signal high-speed switching transistor has a lower productivity than a general transistor because a Pt introduction step needs to be separately added. In addition, since introduction from the back surface of the silicon semiconductor substrate requires protection of the front surface of the substrate and pretreatment of the back surface of the substrate, the productivity is further reduced.

[0029]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is characterized in that a lifetime killer is introduced simultaneously with the step of diffusing a semiconductor element region on the surface of a semiconductor substrate.

By applying a liquid dopant source containing phosphorus and Pt to the surface of a semiconductor substrate, in an NPN transistor, Pt is introduced from the substrate surface simultaneously with the introduction of phosphorus diffused into an emitter region, and in a PNP transistor, a base contact region is introduced. Pt is introduced from the substrate surface at the same time as phosphorus is diffused into the substrate. Pt is gettered in the N ⁺ -type region, but can be released from the N ⁺ -type region by subsequently performing a heat treatment at a temperature at which gettering efficiency is poor. Thus, the switching time is controlled by diffusing Pt into the semiconductor substrate.

This eliminates the step of introducing Pt from the back surface of the conventional NPN or PNP type high-speed switching transistor.
The number of steps can be reduced, which can contribute to a significant improvement in productivity.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to FIGS. 1 to 5, taking a small-signal NPN-type high-speed switching transistor as an example.

The NPN type high-speed switching transistor is a process of diffusing a base region of the opposite conductivity type on the surface of the semiconductor substrate of one conductivity type, and a lifetime killer is diffused on the semiconductor substrate simultaneously with the diffusion of the emitter region on the surface of the base region. Baking the semiconductor substrate at a temperature equal to or lower than the diffusion temperature of the region, and forming a metal electrode.

FIG. 1 shows a first step of the present invention in which a base region of the opposite conductivity type is diffused into the surface of a semiconductor substrate of one conductivity type.

An N type epitaxial layer is stacked on an N ⁺ type silicon semiconductor substrate to form a collector region 1, and the semiconductor substrate is exposed to a steam atmosphere (about 1000 ° C. for about 100 minutes) to form an oxide film 2.

The oxide film 2 on the intended base region is removed by etching to expose the semiconductor substrate, and P-type impurities (boron) are ion-implanted. The implantation conditions at this time are a dose of 6 to 7 × 10 ¹⁴ cm ⁻² and an implantation energy of about 50 KeV.

A CVD oxide film 3 is deposited on the entire surface by a CVD method (about 400 ° C. for about 60 minutes), and boron is diffused (about 1150 ° C. for about 60 minutes) to form a base region 4.

FIGS. 2 to 4 show the features of the present invention, and FIG.
In this step, the lifetime killer is diffused into the semiconductor substrate simultaneously with the diffusion of the emitter region on the surface of the base region, and baking is performed at a temperature equal to or lower than the diffusion temperature of the emitter region.

FIG. 2 shows that the oxide film 2 on the surface of the semiconductor substrate is removed by etching for the emitter region to be diffused to the surface of the base region 4 and the annular ring to be diffused to the outermost periphery of the collector region. A part of the surface of the collector region 1 is exposed. A liquid dopant source containing phosphorus and Pt (trade name: P-Pt-OCD, manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied to the surface of a semiconductor substrate in order to simultaneously adhere one conductivity type impurity (phosphorus) and Pt which is a lifetime killer. 5) Apply 5 and bake.

FIG. 3 shows a CV after removing the ring lath layer on the surface.
A CVD oxide film 3 is formed by the D method (about 400 ° C. for about 60 minutes), and phosphorus is diffused into the base region 4 (about 100 ° C. at about 1000 ° C.).
To form an emitter region 6 and simultaneously diffuse into the collector region 1 to form an annular ring 7.

At this time, Pt, which is a lifetime killer, is simultaneously gettered partially into the emitter region 6 and the annular ring 7, which are N ⁺ -type regions, and the rest is diffused throughout the semiconductor substrate.

FIG. 4 shows a step of baking. The semiconductor substrate is baked at 700 ° C. for about 1 hour. Pt introduced from the surface of the semiconductor substrate is easily gettered to the N ⁺ type region which is the emitter region 6 or the annular ring 7, but after the phosphorus forming the N ⁺ type region is thermally diffused to a desired depth, the gettering occurs. At low efficiency temperature and N ⁺
By performing heat treatment again at a temperature lower than the diffusion temperature of the mold region, for example, 700 ° C. for 1 hour, Pt is converted into N ⁺ of the getter site.
It can be detached from the mold region. This allows Pt introduced from the surface of the semiconductor substrate to efficiently contribute to the switching time.

Here, the temperature at which gettering efficiency is high is 80.
The temperature is 0 to 900 ° C., and Pt can be separated from the getter site at any other temperature. However, by setting the temperature lower than the diffusion temperature of the N ⁺ type region, the influence of heat on the emitter region 6 and the annular ring 7 is reduced. Pt can be released without any effect.

Since the amount of Pt released can be adjusted by the baking temperature, the switching time can be controlled.

FIG. 5 shows a step of forming a metal electrode, which is the third step of the present invention. The oxide film 2 on the surface of the semiconductor substrate is removed to make contact with the base region 4 and the emitter region 6. Al (1.1μ
m) and the like are sequentially deposited by vacuum evaporation, and then subjected to etching to obtain a desired wiring electrode shape, thereby forming a base electrode 13 and an emitter electrode 12. The semiconductor substrate, which is still thick at the time of wafer loading, is ground to the desired finished thickness (for example, 200 μm) by back grinding, and NiCr / AuS
b is vacuum-deposited and heat-treated to provide a collector electrode 14.

FIGS. 6 to 8 show a method of manufacturing a small-signal PNP-type high-speed switching transistor with a focus on a semiconductor element formation region. The same components as those of the NPN transistor have the same reference numerals.

The PNP-type high-speed switching transistor diffuses a lifetime killer into the semiconductor substrate simultaneously with the diffusion of the base contact region, and bake the semiconductor substrate at a temperature equal to or lower than the diffusion temperature of the emitter region and the base contact region.

FIG. 6 shows steps of diffusion of the base region and the emitter region. A P-type epitaxial layer is stacked on a P ⁺ type silicon semiconductor substrate to form a collector region 1, and the semiconductor substrate is exposed to a steam atmosphere (about 1000 ° C. for about 80 minutes) to form an oxide film 2.

The oxide film 2 on the intended base region is removed by etching to expose the semiconductor substrate, and N-type impurities (phosphorus) are ion-implanted. The implantation conditions at this time are a dose of 6 to 7 × 10 ¹³ cm ⁻² and an implantation energy of about 100 KeV.

A CVD oxide film 3 is deposited on the entire surface by a CVD method (about 400 ° C. for about 60 minutes), and phosphorus is diffused (about 1200 ° C. for about 130 minutes) to form a base region 4.

The oxide film 2 on the predetermined emitter ring on the base region 4 and the predetermined annular ring on the outermost periphery of the collector region 1 is removed by etching to expose the semiconductor substrate, and PBF is applied and baked (1100). ℃, about
Half an hour). After removing the glass layer on the surface, CV
A D oxide film 3 is deposited to diffuse boron, and an emitter region 6 is provided on the surface of the base region 4 and an annular ring 7 is provided on the outermost periphery of the collector region 1 to form a semiconductor element region.

FIG. 7 shows the step of applying a liquid dopant source. In order to form a base contact region for reducing the contact resistance, a part of the oxide film 2 on the surface of the base region 4 is removed to expose the semiconductor substrate. Thereafter, a liquid dopant source containing phosphorus and Pt (P-Pt-
OCD) 5 is applied and baked (1000 ° C., about 60 minutes).

FIG. 8 shows a step of introducing Pt simultaneously with the diffusion of the base contact region. The glass layer on the surface is removed to form a CVD oxide film 3 by the CVD method, and phosphorus is diffused into the base contact region 10. At this time, at the same time, part of Pt, which is a lifetime killer, is gettered in the base contact region 10 which is an N ⁺ type region, and the rest is diffused throughout the semiconductor substrate.

Thereafter, the semiconductor substrate is baked at 700 ° C. for about 1 hour. Pt introduced from the surface of the semiconductor substrate is easily gettered into the N ⁺ -type region, which is the base contact region 10. However, after the phosphorus forming the N ⁺ -type region is thermally diffused to a desired depth, the temperature at which the gettering efficiency is low is low. And a temperature lower than the diffusion temperature of the N ⁺ type region, for example, 7
By performing the heat treatment again at 00 ° C. for 1 hour, Pt can be released from the N ⁺ type region of the gettersite.

By baking at a temperature lower than the diffusion temperature of the base contact region 10 which is an N ⁺ type region, the Pt introduced from the surface of the semiconductor substrate can be efficiently used without affecting the base contact region 10 due to heat. It can well contribute to the switching time.

A feature of the present invention is that a liquid dopant source containing phosphorus and a liquid dopant source containing Pt are contained.
A liquid dopant source containing phosphorus and Pt is applied to the surface of the semiconductor substrate. Pt is diffused into the semiconductor substrate simultaneously with the diffusion of the emitter region and the annular ring in the NPN transistor, and simultaneously with the diffusion of the base contact region in the PNP transistor. It is characterized in that Pt gettered in the N ⁺ -type region by the baking treatment is released into the semiconductor substrate.

[0057] Pt introduced from the substrate surface in the emitter region or annular ring is a N ⁺ type region in the NPN transistor, Although likely to be gettered in the base contact region in the PNP transistor, N ⁺
After thermally diffusing phosphorus forming the mold region to a desired depth, heat treatment is performed again at a temperature with low gettering efficiency and lower than the diffusion temperature of the N ⁺ type region (for example, at 700 ° C. for 1 hour). Pt can be released from the N ⁺ -type region of gettersite. Thus, Pt introduced from the surface of the semiconductor substrate can efficiently contribute to the switching time without affecting the N ⁺ type region of the semiconductor element region due to heat.

Accordingly, since the introduction can be carried out from the front surface and at the same time as the diffusion of the semiconductor element region, the pretreatment of the back surface of the semiconductor substrate for introduction from the back surface of the substrate, which is conventionally required, becomes unnecessary. About 1/4 of the process
The number of steps can be reduced, and the productivity can be greatly improved.

The switching time can be controlled because the degree of Pt can be adjusted by the baking temperature.

[0060]

According to the manufacturing method of the present invention, Pt introduced from the substrate surface is transferred to the emitter region or N ⁺ type region which is an annular ring in an NPN type transistor.
In an NP-type transistor, the base contact region N
^{Although the} gettering is likely to occur in the ⁺ type region, after the phosphorus forming the N ⁺ type region is thermally diffused to a desired depth, the temperature at which the gettering efficiency is low and lower than the diffusion temperature of the N ⁺ type region (for example, 700 Pt can be released from the N ⁺ -type region of the gettersite by performing the heat treatment again (at 1 ° C. for 1 hour). Thus, the introduced Pt can efficiently contribute to the switching time without affecting the N ⁺ type region of the semiconductor element region due to heat.

Therefore, the introduction can be performed from the front surface of the semiconductor substrate and simultaneously with the formation of the N ⁺ -type region in the semiconductor element region. Therefore, about one-fourth of the semiconductor element manufacturing steps can be reduced, and the productivity can be greatly improved.

The switching time can be controlled because the degree of Pt can be adjusted by the baking temperature.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a sectional view illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a sectional view illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a sectional view illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a sectional view illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a sectional view illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is a sectional view illustrating the method for manufacturing the semiconductor device according to the present invention.

FIG. 8 is a sectional view illustrating the method for manufacturing the semiconductor device according to the present invention.

FIG. 9 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 10 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 11 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 12 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 13 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 14 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 15 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 16 is a cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

Claims (4)

[Claims] 1. A method for manufacturing a semiconductor device, comprising introducing a lifetime killer simultaneously with a step of diffusing a semiconductor element region on a surface of a semiconductor substrate. 2. The method according to claim 1, wherein a liquid dopant source containing impurities and platinum in the semiconductor element region is used. 3. The NPN transistor includes a step of diffusing a lifetime killer into the semiconductor substrate simultaneously with the diffusion of the emitter region, and baking the semiconductor substrate at a temperature equal to or lower than a diffusion temperature of the emitter region. Item 2. A method for manufacturing a semiconductor device according to item 1. 4. A PNP transistor comprising: a step of diffusing a lifetime killer into a semiconductor substrate simultaneously with a step of diffusing a base contact region, and baking the semiconductor substrate at a temperature equal to or lower than a diffusion temperature of the emitter region and the base contact region. The method for manufacturing a semiconductor device according to claim 1, wherein: