JP2002076136A5 - - Google Patents
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- Publication number
- JP2002076136A5 JP2002076136A5 JP2000265567A JP2000265567A JP2002076136A5 JP 2002076136 A5 JP2002076136 A5 JP 2002076136A5 JP 2000265567 A JP2000265567 A JP 2000265567A JP 2000265567 A JP2000265567 A JP 2000265567A JP 2002076136 A5 JP2002076136 A5 JP 2002076136A5
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000265567A JP4818499B2 (ja) | 2000-09-01 | 2000-09-01 | 半導体装置の製造方法 |
US09/796,597 US6667206B2 (en) | 2000-09-01 | 2001-03-02 | Method of manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000265567A JP4818499B2 (ja) | 2000-09-01 | 2000-09-01 | 半導体装置の製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2010099097A Division JP2010187013A (ja) | 2010-04-22 | 2010-04-22 | 半導体装置の製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2002076136A JP2002076136A (ja) | 2002-03-15 |
JP2002076136A5 true JP2002076136A5 (ja) | 2007-10-18 |
JP4818499B2 JP4818499B2 (ja) | 2011-11-16 |
Family
ID=18752812
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2000265567A Expired - Fee Related JP4818499B2 (ja) | 2000-09-01 | 2000-09-01 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US6667206B2 (ja) |
JP (1) | JP4818499B2 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1253929C (zh) | 2003-03-04 | 2006-04-26 | 松下电器产业株式会社 | 半导体装置及其制造方法 |
US7135373B2 (en) * | 2003-09-23 | 2006-11-14 | Texas Instruments Incorporated | Reduction of channel hot carrier effects in transistor devices |
US6927137B2 (en) * | 2003-12-01 | 2005-08-09 | Texas Instruments Incorporated | Forming a retrograde well in a transistor to enhance performance of the transistor |
JP2005209836A (ja) * | 2004-01-22 | 2005-08-04 | Toshiba Corp | 半導体装置の製造方法 |
WO2007045658A1 (en) * | 2005-10-18 | 2007-04-26 | Stmicroelectronics Crolles 2 Sas | Selective removal of a silicon oxide layer |
JP5283827B2 (ja) * | 2006-03-30 | 2013-09-04 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
JP2006339670A (ja) * | 2006-08-21 | 2006-12-14 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US7629655B2 (en) * | 2007-03-20 | 2009-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with multiple silicide regions |
KR101095679B1 (ko) * | 2008-12-26 | 2011-12-19 | 주식회사 하이닉스반도체 | Pmos 트랜지스터의 제조방법 |
US8592264B2 (en) * | 2011-12-21 | 2013-11-26 | International Business Machines Corporation | Source-drain extension formation in replacement metal gate transistor device |
CN103151388B (zh) * | 2013-03-05 | 2015-11-11 | 京东方科技集团股份有限公司 | 一种多晶硅薄膜晶体管及其制备方法、阵列基板 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5712548A (en) | 1980-06-27 | 1982-01-22 | Oki Electric Ind Co Ltd | Manufacture of complementary type mos semiconductor device |
US5153144A (en) * | 1988-05-10 | 1992-10-06 | Hitachi, Ltd. | Method of making tunnel EEPROM |
JPH04170067A (ja) | 1990-11-01 | 1992-06-17 | Nippon Sheet Glass Co Ltd | Cmosトランジスタの製造方法 |
US5532176A (en) * | 1992-04-17 | 1996-07-02 | Nippondenso Co., Ltd. | Process for fabricating a complementary MIS transistor |
JPH0669231A (ja) | 1992-08-12 | 1994-03-11 | Yamaha Corp | Mos型トランジスタの製法 |
US5405791A (en) * | 1994-10-04 | 1995-04-11 | Micron Semiconductor, Inc. | Process for fabricating ULSI CMOS circuits using a single polysilicon gate layer and disposable spacers |
JP3381110B2 (ja) | 1995-01-20 | 2003-02-24 | ソニー株式会社 | 半導体装置の製造方法 |
JPH08321557A (ja) | 1995-05-24 | 1996-12-03 | Nec Corp | Cmos半導体装置の製造方法 |
US6221709B1 (en) * | 1997-06-30 | 2001-04-24 | Stmicroelectronics, Inc. | Method of fabricating a CMOS integrated circuit device with LDD N-channel transistor and non-LDD P-channel transistor |
US6137144A (en) * | 1998-04-08 | 2000-10-24 | Texas Instruments Incorporated | On-chip ESD protection in dual voltage CMOS |
JP3293567B2 (ja) * | 1998-09-30 | 2002-06-17 | 日本電気株式会社 | 半導体装置の製造方法 |
US6235568B1 (en) * | 1999-01-22 | 2001-05-22 | Intel Corporation | Semiconductor device having deposited silicon regions and a method of fabrication |
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2000
- 2000-09-01 JP JP2000265567A patent/JP4818499B2/ja not_active Expired - Fee Related
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2001
- 2001-03-02 US US09/796,597 patent/US6667206B2/en not_active Expired - Lifetime