JP2002043478A - Ceramic circuit board - Google Patents

Ceramic circuit board

Info

Publication number
JP2002043478A
JP2002043478A JP2000223791A JP2000223791A JP2002043478A JP 2002043478 A JP2002043478 A JP 2002043478A JP 2000223791 A JP2000223791 A JP 2000223791A JP 2000223791 A JP2000223791 A JP 2000223791A JP 2002043478 A JP2002043478 A JP 2002043478A
Authority
JP
Japan
Prior art keywords
circuit board
semiconductor element
metal circuit
metal
convex portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000223791A
Other languages
Japanese (ja)
Other versions
JP4471470B2 (en
Inventor
Kouichiro Sugai
広一朗 菅井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2000223791A priority Critical patent/JP4471470B2/en
Publication of JP2002043478A publication Critical patent/JP2002043478A/en
Application granted granted Critical
Publication of JP4471470B2 publication Critical patent/JP4471470B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385Shape, e.g. interlocking features
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a semiconductor element is peeled from a metal circuit board and cannot be operated normally. SOLUTION: The metal circuit board 3 is attached to the upper face of a ceramic board 1, a projection part 3a mounting a semiconductor element 5 is formed on the upper face of the metal circuit board 3, and the projection part 3a satisfies the following equation. 200 μm>=H>=50 μm, L>=100 μm, S>=40%, H: height of the projection part, L: (the outer periphery of the semiconductor element)-(the outer periphery of the projection part) and S: a ratio of the area of the upper face of the projection part to the area of the lower face of the semiconductor element).

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、セラミック基板に
金属回路板をロウ付けにより接合させて成るセラミック
回路基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic circuit board formed by joining a metal circuit board to a ceramic substrate by brazing.

【0002】[0002]

【従来の技術】近年、パワーモジュール用基板やスイッ
チングモジュール用基板等の回路基板として、セラミッ
ク基板上に被着させたメタライズ金属層に銀−銅合金等
のロウ材を介して銅等から成る金属回路板を接合させた
セラミック回路基板、あるいはセラミック基板上に銀−
銅共晶合金にチタン、ジルコニウム、ハフニウムまたは
その水素化物を添加した活性金属ロウ材を介して銅等か
ら成る金属回路板を直接接合させたセラミック回路基板
が用いられている。
2. Description of the Related Art In recent years, as a circuit board such as a power module board or a switching module board, a metallized metal layer adhered on a ceramic substrate is formed of a metal made of copper or the like via a brazing material such as a silver-copper alloy. A ceramic circuit board with a circuit board bonded, or silver
A ceramic circuit board is used in which a metal circuit board made of copper or the like is directly joined to a copper eutectic alloy via an active metal brazing material obtained by adding titanium, zirconium, hafnium or a hydride thereof.

【0003】かかるセラミック回路基板、例えば、セラ
ミック基板上に被着させたメタライズ金属層にロウ材を
介して銅等から成る金属回路板を接合させたセラミック
回路基板は、一般に酸化アルミニウム質焼結体、窒化ア
ルミニウム質焼結体、窒化珪素質焼結体、ムライト質焼
結体等の電気絶縁性のセラミックス材料から成るセラミ
ック基板の表面にメタライズ金属層を被着させておき、
該メタライズ金属層に銅等の金属材料から成る金属回路
板を銀ロウ等のロウ材を介しロウ付けすることによって
形成されており、具体的には、例えば、セラミック基板
が酸化アルミニウム質焼結体から成る場合には、酸化ア
ルミニウム、酸化珪素、酸化マグネシウム、酸化カルシ
ウム等の原料粉末に適当な有機バインダー、可塑剤、溶
剤等を添加混合して泥漿状と成すとともにこれを従来周
知のドクターブレード法やカレンダーロール法等のテー
プ成形技術を採用して複数のセラミックグリーンシート
を得、次に前記セラミックグリーンシート上にタングス
テンやモリブデン等の高融点金属粉末に適当な有機バイ
ンダー、可塑剤、溶剤を添加混合して得た金属ペースト
をスクリーン印刷法等の厚膜形成技術を採用することに
よって所定パターンに印刷塗布し、次に前記金属ペース
トが所定パターンに印刷塗布されたセラミックグリーン
シートを必要に応じて上下に積層するとともに還元雰囲
気中、約1600℃の温度で焼成し、セラミックグリー
ンシートと金属ペーストを焼結一体化させて表面にメタ
ライズ金属層を有する酸化アルミニウム質焼結体から成
るセラミック基板を形成し、最後に前記セラミック基板
表面のメタライズ金属層上に銅等から成る所定パターン
の金属回路板を間に銀ロウ等のロウ材を挟んで載置させ
るとともにこれを還元雰囲気中、約900℃の温度に加
熱してロウ材を溶融させ、該溶融したロウ材でメタライ
ズ金属層と金属回路板とを接合することによって製作さ
れる。
[0003] Such a ceramic circuit board, for example, a ceramic circuit board in which a metal circuit board made of copper or the like is joined to a metallized metal layer adhered on the ceramic board via a brazing material, is generally made of an aluminum oxide sintered body. A metallized metal layer is applied to the surface of a ceramic substrate made of an electrically insulating ceramic material such as an aluminum nitride sintered body, a silicon nitride sintered body, a mullite sintered body, etc.
The metallized metal layer is formed by brazing a metal circuit board made of a metal material such as copper via a brazing material such as silver brazing. Specifically, for example, a ceramic substrate is made of an aluminum oxide sintered body. In the case of consisting of, raw material powders such as aluminum oxide, silicon oxide, magnesium oxide and calcium oxide are mixed with an appropriate organic binder, a plasticizer, a solvent and the like to form a slurry, which is then mixed with a conventionally known doctor blade method. A plurality of ceramic green sheets are obtained by adopting a tape forming technique such as or a calender roll method, and then an appropriate organic binder, a plasticizer, and a solvent are added to the high melting point metal powder such as tungsten or molybdenum on the ceramic green sheets. The metal paste obtained by mixing is subjected to a predetermined pattern by employing a thick film forming technology such as screen printing. Then, the ceramic green sheets, on which the metal paste is printed and applied in a predetermined pattern, are laminated one on top of the other as necessary and fired at a temperature of about 1600 ° C. in a reducing atmosphere. To form a ceramic substrate made of an aluminum oxide sintered body having a metallized metal layer on the surface, and finally a metal circuit board of a predetermined pattern made of copper or the like on the metallized metal layer on the surface of the ceramic substrate. And a brazing material such as a silver brazing material is interposed therebetween and heated in a reducing atmosphere at a temperature of about 900 ° C. to melt the brazing material, and the metallized metal layer and the metal circuit board are melted with the molten brazing material. It is produced by joining

【0004】なお、前記メタライズ金属層及び金属回路
板の露出表面には酸化腐蝕を有効に防止するとともに金
属回路板に半導体素子を半田等の接着材を介して強固に
接続させるために、ニッケル等の耐蝕性に優れ、かつ半
田等の接着材に対し濡れ性が良い金属がメッキ法等の技
術を用いることによって所定厚みに被着されている。
In order to effectively prevent oxidative corrosion on the exposed surface of the metallized metal layer and the metal circuit board and to firmly connect the semiconductor element to the metal circuit board via an adhesive such as solder, nickel or the like is used. A metal having excellent corrosion resistance and good wettability to an adhesive such as solder is applied to a predetermined thickness by using a technique such as a plating method.

【0005】また前記金属回路板への半導体素子の接合
は、まず金属回路板上に半田粉末に有機溶剤、溶媒を添
加混合して形成した半田ペーストを従来周知のスクリー
ン印刷法等の印刷技術を用いることによって所定パター
ンに印刷塗布し、次にこの印刷塗布した半田ペースト上
に半導体素子を載置当接させ、しかる後、これを所定温
度(約180℃)に加熱し、半田ペーストの有機溶剤、
溶媒等を輝散させるとともに半田を溶融させ、該溶融し
た半田により金属回路板と半導体素子とを接合させるこ
とによって行われている。
[0005] The bonding of the semiconductor element to the metal circuit board is performed by printing a solder paste formed by adding an organic solvent and a solvent to the solder powder on the metal circuit board, and using a printing technique such as screen printing. By using the solder paste, the semiconductor element is placed on the solder paste on which the solder paste has been printed and applied, and then the semiconductor element is heated to a predetermined temperature (about 180 ° C.). ,
This is performed by causing a solvent or the like to scatter and melting the solder, and joining the metal circuit board and the semiconductor element with the melted solder.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、この従
来のセラミック回路基板においては、半田等の接着材を
介して金属回路板上面に半導体素子を接合させる際、半
田が金属回路板の表面に大きく溶け広がって厚みが50
μm未満の薄いものとなり、その結果、金属回路板に半
導体素子を強固に被着させるのが困難で、金属回路板と
半導体素子に熱が作用した場合、金属回路板と半導体素
子との間に両者の熱膨張係数の相違(例えば、銅:18
ppm/℃、シリコン:4ppm/℃)に起因する大き
な熱応力が発生し、該熱応力によって半導体素子が金属
回路板より剥離してしまうという欠点を有していた。
However, in this conventional ceramic circuit board, when the semiconductor element is bonded to the upper surface of the metal circuit board via an adhesive such as solder, the solder is largely melted on the surface of the metal circuit board. Spread and thickness is 50
μm, and as a result, it is difficult to firmly attach the semiconductor element to the metal circuit board, and when heat acts on the metal circuit board and the semiconductor element, The difference between the two thermal expansion coefficients (for example, copper: 18
(ppm / ° C., silicon: 4 ppm / ° C.), which has a disadvantage that a large thermal stress is generated and the semiconductor element is separated from the metal circuit board by the thermal stress.

【0007】また、接着材としての半田の厚みを予め厚
く(例えば250μm)しておき、金属回路板と半導体
素子との間に介在する半田の量を適量として金属回路板
に対する半導体素子の接合強度を強いものとすることが
考えられる。
Further, the thickness of the solder as an adhesive is increased in advance (for example, 250 μm), and the bonding strength of the semiconductor element to the metal circuit board is determined by setting an appropriate amount of solder interposed between the metal circuit board and the semiconductor element. May be strengthened.

【0008】しかしながら、接着材としての半田の厚み
を厚くしておくと半田を溶融させて半導体素子を金属回
路板に接合する際、熔けた半田が金属回路板上からセラ
ミック基板上に流れ出て隣接する金属回路板間を短絡さ
せてしまったり、半導体素子と金属回路板との間に熱伝
導率の低い半田からなる接着材が厚く介在し、半導体素
子の作動時に発生する熱を金属回路板及びセラミック基
板に効率良く伝達させることができず、半導体素子を高
温とし半導体素子に熱破壊や特性に熱劣化を招来させて
しまうという欠点を有していた。
However, if the thickness of the solder as the adhesive is increased, when the solder is melted and the semiconductor element is joined to the metal circuit board, the molten solder flows out from the metal circuit board onto the ceramic substrate and is adjacent thereto. Or short circuit between the metal circuit boards, or a thick adhesive made of solder having a low thermal conductivity is interposed between the semiconductor element and the metal circuit board, and the heat generated during operation of the semiconductor element is generated by the metal circuit board and It cannot be efficiently transmitted to the ceramic substrate, and has a drawback that the semiconductor element is heated to a high temperature to cause thermal destruction and thermal degradation of the semiconductor element.

【0009】本発明は上記欠点に鑑み案出されたもの
で、その目的は金属回路板に半導体素子を強固に接合さ
せるとともに金属回路板に接合された半導体素子を常に
適温とし半導体素子を長期間にわたり正常、かつ安定に
作動させることができるセラミック回路基板を提供する
ことにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and has as its object to firmly join a semiconductor element to a metal circuit board and to keep the semiconductor element joined to the metal circuit board at an appropriate temperature for a long time. An object of the present invention is to provide a ceramic circuit board that can be normally and stably operated over a long period of time.

【0010】[0010]

【課題を解決するための手段】本発明は、セラミック基
板の上面に金属回路板を取着するとともに該金属回路板
の上面に半導体素子が載置される凸部を形成して成り、
前記凸部が下記式を満足することを特徴とするものであ
る。
According to the present invention, a metal circuit board is attached to an upper surface of a ceramic substrate, and a convex portion on which a semiconductor element is mounted is formed on the upper surface of the metal circuit plate.
The convex portion satisfies the following expression.

【0011】200μm≧H≧50μm L≧100μm S≧40% H:凸部の高さ L:(半導体素子の外周)−(凸部の外周) S:半導体素子の下面面積に対する凸部の上面面積の比
率 本発明のセラミック回路基板によれば、金属回路板の上
面に半導体素子が載置される凸部を形成するとともに該
凸部の高さを50μm乃至200μmとし、かつ凸部の
外周と半導体素子の外周との間に100μm以上の差が
形成されるよう凸部の外形寸法を半導体素子の外形寸法
より小さくしつつ半導体素子の下面面積に対する凸部の
上面面積の比率を40%以上としたことから金属回路板
に設けた凸部に半導体素子を載置させるとともに接着材
としての半田を介して接合させた場合、半導体素子の下
面と凸部側面と凸部周囲の金属回路板上面との間に適度
な容積の空間が形成されるとともに該空間内及び半導体
素子の下面と凸部上面との間に半田が充填介在されるこ
ととなり、その結果、金属回路板に設けた凸部への半導
体素子の半田を介しての接合が三次元的となって接合強
度を極めて強いものとし、半導体素子を凸部上面に確
実、強固に接合させることができる。
200 μm ≧ H ≧ 50 μm L ≧ 100 μm S ≧ 40% H: Height of convex portion L: (periphery of semiconductor device) − (periphery of convex portion) S: Upper surface area of convex portion relative to lower surface area of semiconductor device According to the ceramic circuit board of the present invention, the convex portion on which the semiconductor element is mounted is formed on the upper surface of the metal circuit board, the height of the convex portion is 50 μm to 200 μm, and the outer periphery of the convex portion is The ratio of the upper surface area of the convex portion to the lower surface area of the semiconductor device was set to 40% or more while the external size of the convex portion was made smaller than the external size of the semiconductor device so that a difference of 100 μm or more was formed between the semiconductor device and the outer periphery of the device. Therefore, when the semiconductor element is mounted on the convex portion provided on the metal circuit board and is bonded via solder as an adhesive, the lower surface of the semiconductor element, the side surface of the convex portion, and the upper surface of the metal circuit board around the convex portion are formed. Moderately in between A space having a volume is formed, and solder is filled and interposed in the space and between the lower surface of the semiconductor element and the upper surface of the convex portion. As a result, soldering of the semiconductor element to the convex portion provided on the metal circuit board is performed. The three-dimensional bonding can be made extremely strong, and the semiconductor element can be securely and firmly bonded to the upper surface of the projection.

【0012】また同時に金属回路板に設けた凸部に半導
体素子を接着材としての半田を介して接合させた場合、
半導体素子と凸部とは適度な面積で当接して半導体素子
の作動時に発生する熱は金属回路板及びセラミック基板
に効率良く伝達されることとなり、その結果、半導体素
子は常に適温となり、半導体素子を長期間にわたり正
常、かつ安定に作動させることが可能となる。
When a semiconductor element is simultaneously joined to a convex portion provided on a metal circuit board via solder as an adhesive,
The semiconductor element and the protrusion come into contact with an appropriate area, and the heat generated during operation of the semiconductor element is efficiently transmitted to the metal circuit board and the ceramic substrate. As a result, the semiconductor element always has an appropriate temperature, and Can operate normally and stably over a long period of time.

【0013】[0013]

【発明の実施の形態】次に、本発明を添付図面に示す実
施例に基づき詳細に説明する。図1は、本発明のセラミ
ック回路基板の一実施例を示し、1はセラミック基板、
2はメタライズ金属層、3は金属回路板である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on embodiments shown in the accompanying drawings. FIG. 1 shows an embodiment of the ceramic circuit board of the present invention, wherein 1 is a ceramic board,
2 is a metallized metal layer and 3 is a metal circuit board.

【0014】前記セラミック基板1は四角形状をなし、
その上面にメタライズ金属層2が被着されており、該メ
タライズ金属層2には金属回路板3がロウ付けされてい
る。
The ceramic substrate 1 has a square shape,
A metallized metal layer 2 is adhered on the upper surface, and a metal circuit board 3 is brazed to the metallized metal layer 2.

【0015】前記セラミック基板1は金属回路板3を支
持する支持部材として作用し、酸化アルミニウム質焼結
体、窒化珪素質焼結体、窒化アルミニウム質焼結体、炭
化珪素質焼結体、ムライト質焼結体等の電気絶縁材料で
形成されている。
The ceramic substrate 1 functions as a support member for supporting the metal circuit board 3, and is made of aluminum oxide sintered body, silicon nitride sintered body, aluminum nitride sintered body, silicon carbide sintered body, mullite. It is formed of an electrically insulating material such as a porous sintered body.

【0016】前記セラミック基板1は、例えば、酸化ア
ルミニウム質焼結体で形成されている場合は、酸化アル
ミニウム、酸化珪素、酸化マグネシウム、酸化カルシウ
ム等の原料粉末に適当な有機バインダー、可塑剤、溶剤
を添加混合して泥漿状となすとともに該泥漿物を従来周
知のドクターブレード法やカレンダーロール法を採用す
ることによってセラミックグリーンシート(セラミック
生シート)を形成し、次に前記セラミックグリーンシー
トに適当な打ち抜き加工を施し、所定形状となすととも
に必要に応じて複数枚を積層して成形体となし、しかる
後、これを約1600℃の高温で焼成することによっ
て、あるいは酸化アルミニウム等の原料粉末に適当な有
機溶剤、溶媒を添加混合して原料粉末を調整するととも
に該原料粉末をプレス成形技術によって所定形状に成形
し、しかる後、前記成形体を約1600℃の温度で焼成
することによって製作される。
When the ceramic substrate 1 is formed of, for example, an aluminum oxide sintered body, an organic binder, a plasticizer, and a solvent suitable for a raw material powder such as aluminum oxide, silicon oxide, magnesium oxide, and calcium oxide are used. Is mixed and formed into a slurry, and the slurry is formed into a ceramic green sheet (green ceramic sheet) by employing a conventionally known doctor blade method or calender roll method. A punching process is performed, a predetermined shape is formed, and a plurality of sheets are laminated as necessary to form a molded body. Thereafter, the molded body is fired at a high temperature of about 1600 ° C., or is applied to a raw material powder such as aluminum oxide. The raw material powder is prepared by adding and mixing an organic solvent and a solvent. By molding techniques and molded into a predetermined shape, and thereafter, is manufactured by firing the molded body at a temperature of about 1600 ° C..

【0017】また前記セラミック基板1はその表面にメ
タライズ金属層2が被着されており、該メタライズ金属
層2は金属回路板3をセラミック基板1にロウ付けする
際の下地金属層として作用する。
A metallized metal layer 2 is adhered to the surface of the ceramic substrate 1, and the metallized metal layer 2 acts as a base metal layer when the metal circuit board 3 is brazed to the ceramic substrate 1.

【0018】前記メタライズ金属層2は、タングステ
ン、モリブデン、マンガン等の高融点金属材料より成
り、例えば、タングステン粉末に適当な有機バインダ
ー、可塑材、溶剤を添加混合して得た金属ペーストを焼
成によってセラミック基板1となるセラミックグリーン
シート(セラミック生シート)の表面に予め従来周知の
スクリーン印刷法により所定パターンに印刷塗布してお
くことによってセラミック基板1の上面に所定パター
ン、所定厚み(10〜50μm)に被着される。
The metallized metal layer 2 is made of a high melting point metal material such as tungsten, molybdenum, manganese or the like. For example, a metal paste obtained by adding a suitable organic binder, a plasticizer and a solvent to tungsten powder and mixing the resultant is fired. A predetermined pattern and a predetermined thickness (10 to 50 μm) are formed on the upper surface of the ceramic substrate 1 by printing and applying a predetermined pattern on a surface of a ceramic green sheet (ceramic raw sheet) serving as the ceramic substrate 1 in advance by a conventionally known screen printing method. Is adhered to.

【0019】なお、前記メタライズ金属層2はその表面
にニッケル、金等の良導電性で、耐蝕性及びロウ材との
濡れ性が良好な金属をメッキ法により被着させておく
と、メタライズ金属層2の酸化腐食を有効に防止するこ
とができるとともにメタライズ金属層2と金属回路板3
とのロウ付けを極めて強固になすことができる。従っ
て、前記メタライズ金属層2の酸化腐蝕を有効に防止
し、メタライズ金属層2と金属回路板3とのロウ付けを
強固となすにはメタライズ金属層2の表面にニッケル、
金等の良導電性で、耐蝕性及びロウ材との濡れ性が良好
な金属を1乃至20μmの厚みに被着させておくことが
好ましい。
If the metallized metal layer 2 is coated with a metal such as nickel or gold having good conductivity, good corrosion resistance and good wettability with the brazing material by plating, the metallized metal layer 2 is formed. The oxidation corrosion of the layer 2 can be effectively prevented, and the metallized metal layer 2 and the metal circuit board 3 can be effectively prevented.
Can be extremely firmly brazed. Accordingly, in order to effectively prevent the metallized metal layer 2 from being oxidized and corroded and to firmly braze the metallized metal layer 2 and the metal circuit board 3, nickel,
It is preferable that a metal such as gold having good conductivity, good corrosion resistance and good wettability with the brazing material is applied to a thickness of 1 to 20 μm.

【0020】また前記メタライズ金属層2はその上面に
金属回路板3がロウ材4を介して取着されている。
The metallized metal layer 2 has a metal circuit board 3 attached to the upper surface thereof with a brazing material 4 interposed therebetween.

【0021】前記金属回路板3は銅やアルミニウム等の
金属材料から成り、セラミック基板1の表面に形成され
たメタライズ金属層2上に金属回路板3を、例えば、銀
ロウ材(銀:72重量%、銅:28重量%)やアルミニ
ウムロウ材(アルミニウム:88重量%、シリコン:1
2重量%)等から成るロウ材4を挟んで載置させ、しか
る後、これを真空中もしくは中性、還元雰囲気中、所定
温度(銀ロウ材の場合は約900℃、アルミニウムロウ
材の場合は約600℃)で加熱処理し、ロウ材4を溶融
せしめるとともにメタライズ金属層2の上面と金属回路
板3の下面とに接合させることによってセラミック基板
1の表面に取着されることとなる。
The metal circuit board 3 is made of a metal material such as copper or aluminum. The metal circuit board 3 is formed on a metallized metal layer 2 formed on the surface of the ceramic substrate 1 by, for example, a silver brazing material (silver: 72 wt. %, Copper: 28% by weight) and aluminum brazing material (aluminum: 88% by weight, silicon: 1)
2% by weight) and then placed in a vacuum or in a neutral or reducing atmosphere at a predetermined temperature (about 900 ° C. for silver brazing, about 900 ° C. for aluminum brazing) Is heated at about 600 ° C.) to melt the brazing material 4 and join the upper surface of the metallized metal layer 2 and the lower surface of the metal circuit board 3 to be attached to the surface of the ceramic substrate 1.

【0022】前記銅やアルミニウム等から成る金属回路
板3は、銅やアルミニウム等のインゴット(塊)に圧延
加工方や打ち抜き加工法等、従来周知の金属加工法を施
すことによって、例えば、厚さが500μmで、メタラ
イズ金属層2のパターン形状に対応する所定パターン形
状に製作される。
The metal circuit board 3 made of copper, aluminum, or the like has a thickness, for example, by subjecting an ingot of copper, aluminum, or the like to a conventionally known metal working method such as a rolling method or a punching method. Is 500 μm, and is manufactured in a predetermined pattern shape corresponding to the pattern shape of the metallized metal layer 2.

【0023】前記金属回路板3はまた銅から成る場合、
金属回路板3を無酸素銅で形成しておくと、該無酸素銅
はロウ付けの際に銅の表面が銅中に存在する酸素により
酸化されることなくロウ材4との濡れ性が良好となり、
メタライズ金属層2へのロウ材4を介しての接合が強固
となる。従って、前記金属回路板3はこれを無酸素銅で
形成しておくことが好ましい。
When the metal circuit board 3 is also made of copper,
When the metal circuit board 3 is formed of oxygen-free copper, the oxygen-free copper has good wettability with the brazing material 4 without being oxidized by the oxygen existing in the copper surface during brazing. Becomes
Bonding to the metallized metal layer 2 via the brazing material 4 is strengthened. Therefore, it is preferable that the metal circuit board 3 is formed of oxygen-free copper.

【0024】更に前記金属回路板3はその上面に半導体
素子5の載置される凸部3aが形成されており、該凸部
3aは半導体素子を支持する作用をなすとともに、半導
体素子5の作動時に発生する熱を金属回路板3を介して
伝達・放散する作用を成す。
Further, the metal circuit board 3 has a convex portion 3a on which the semiconductor element 5 is mounted on its upper surface. The convex portion 3a functions to support the semiconductor element and to operate the semiconductor element 5. The heat generated at this time is transmitted and dissipated through the metal circuit board 3.

【0025】前記凸部3aは銅やアルミニウム等のイン
ゴット(塊)に圧延加工法や打ち抜き加工法等、従来周
知の金属加工法を施して金属回路板3を形成する際に同
時に形成される、あるいは金属回路板3にプレス加工法
やエッチング加工法等を施すことによって金属回路板3
上面の所定位置に所定形状に形成される。
The convex portion 3a is formed at the same time when the metal circuit board 3 is formed by applying a conventionally known metal working method such as a rolling method or a punching method to an ingot (lumps) of copper, aluminum, or the like. Alternatively, the metal circuit board 3 is subjected to a pressing method, an etching method, or the like, so that the metal circuit board 3
It is formed in a predetermined shape at a predetermined position on the upper surface.

【0026】前記凸部3aは、その高さ(H)が50μ
m乃至200μm、凸部3aの外周と半導体素子5の外
周との差(L)が100μm以上、半導体素子5の下面
面積に対する凸部3aの上面面積の比率が40%以上と
なっている。
The height (H) of the projection 3a is 50 μm.
m to 200 μm, the difference (L) between the outer circumference of the projection 3 a and the outer circumference of the semiconductor element 5 is 100 μm or more, and the ratio of the area of the upper surface of the projection 3 a to the area of the lower surface of the semiconductor element 5 is 40% or more.

【0027】前記凸部3aの高さを50μm乃至200
μmとし、かつ凸部3aの外周と半導体素子5の外周と
の間に100μm以上の差が形成されるよう凸部3aの
外形寸法を半導体素子5の外形寸法より小さくしつつ半
導体素子5の下面面積に対する凸部3aの上面面積の比
率を40%以上とした場合、金属回路板3に設けた凸部
3aに半導体素子5を載置させるとともに接着材として
の半田6を介して接合させた際、半導体素子5の下面と
凸部3a側面と凸部3a周囲の金属回路板3上面との間
に適度な容積の空間が形成されるとともに該空間内及び
半導体素子5の下面と凸部3a上面との間に半田6が充
填介在されることとなり、その結果、金属回路板3に設
けた凸部3aへの半導体素子5の半田6を介しての接合
が三次元的となって接合強度は極めて強いものとなり、
半導体素子5を凸部3a上面に確実、強固に接合させる
ことができる。
The height of the projection 3a is set to 50 μm to 200 μm.
μm, and the lower surface of the semiconductor element 5 while the outer dimension of the convex part 3a is smaller than the outer dimension of the semiconductor element 5 so that a difference of 100 μm or more is formed between the outer circumference of the convex part 3a and the outer circumference of the semiconductor element 5. When the ratio of the upper surface area of the protrusion 3a to the area is 40% or more, when the semiconductor element 5 is mounted on the protrusion 3a provided on the metal circuit board 3 and joined via the solder 6 as an adhesive. A space having an appropriate volume is formed between the lower surface of the semiconductor element 5, the side surface of the convex portion 3a, and the upper surface of the metal circuit board 3 around the convex portion 3a, and within the space and the lower surface of the semiconductor element 5 and the upper surface of the convex portion 3a. And the solder 6 is interposed between them, and as a result, the bonding of the semiconductor element 5 to the convex portion 3a provided on the metal circuit board 3 via the solder 6 becomes three-dimensional, and the bonding strength is reduced. Very strong,
The semiconductor element 5 can be securely and firmly joined to the upper surface of the projection 3a.

【0028】また同時に金属回路板3に設けた凸部3a
に半導体素子5を接着材としての半田6を介して接合さ
せた場合、半導体素子5と凸部3aとは適度な面積で当
接して半導体素子5の作動時に発生する熱は金属回路板
3及びセラミック基板1に効率良く伝達されることとな
り、その結果、半導体素子5は常に適温となり、半導体
素子5を長期間にわたり正常、かつ安定に作動させるこ
とが可能となる。
At the same time, the projection 3a provided on the metal circuit board 3
When the semiconductor element 5 is joined to the semiconductor element 5 via a solder 6 as an adhesive, the semiconductor element 5 and the projection 3a come into contact with an appropriate area, and the heat generated when the semiconductor element 5 is operated causes the metal circuit board 3 and The power is efficiently transmitted to the ceramic substrate 1, and as a result, the semiconductor element 5 always has an appropriate temperature, and the semiconductor element 5 can operate normally and stably for a long period of time.

【0029】なお、前記凸部3aはその高さが50μm
未満となると半導体素子5の下面と凸部3a側面と凸部
3a周囲の金属回路板3上面との間に形成される空間の
容積が狭くなって半導体素子5を凸部3a上面に強固に
接合させることができず、また200μmを超えると半
導体素子5の下面と凸部3a側面と凸部3a周囲の金属
回路板3上面との間に形成される空間の容積が大きくな
り過ぎ空間内に半田6を完全に充填させることができな
くなって半導体素子5を凸部3a上面に強固に接合させ
ることができない。従って、前記凸部3aはその高さが
50μm乃至200μmの範囲に特定される。
The height of the projection 3a is 50 μm.
When the value is less than the predetermined value, the volume of the space formed between the lower surface of the semiconductor element 5, the side surface of the projection 3a, and the upper surface of the metal circuit board 3 around the projection 3a becomes narrower, and the semiconductor element 5 is firmly joined to the upper surface of the projection 3a. If the thickness exceeds 200 μm, the volume of the space formed between the lower surface of the semiconductor element 5, the side surface of the protrusion 3 a, and the upper surface of the metal circuit board 3 around the protrusion 3 a becomes too large, and the solder is formed in the space. 6 cannot be completely filled, and the semiconductor element 5 cannot be firmly joined to the upper surface of the projection 3a. Therefore, the height of the projection 3a is specified in the range of 50 μm to 200 μm.

【0030】また前記凸部3aはその外周と半導体素子
5の外周との差(L)が100μm未満であると半導体
素子5の下面と凸部3a側面と凸部3a周囲の金属回路
板3上面との間に形成される空間の容積が狭くなって半
導体素子5を凸部3a上面に強固に接合させることがで
きない。従って、前記凸部3aはその外周と半導体素子
5の外周との差(L)が100μm以上に特定される。
When the difference (L) between the outer periphery of the convex portion 3a and the outer periphery of the semiconductor element 5 is less than 100 μm, the lower surface of the semiconductor element 5, the side surface of the convex portion 3a, and the upper surface of the metal circuit board 3 around the convex portion 3a. And the volume of the space formed between the semiconductor element 5 and the semiconductor element 5 cannot be firmly joined to the upper surface of the projection 3a. Therefore, the difference (L) between the outer periphery of the protrusion 3a and the outer periphery of the semiconductor element 5 is specified to be 100 μm or more.

【0031】更に、前記凸部3aの上面面積は半導体素
子5の下面面積の40%未満となると半導体素子5が発
生する熱を金属回路板3及びセラミック基板1に効率よ
く伝達させることができず、半導体素子5を高温とし半
導体素子5に熱破壊や特性に熱劣化を招来させてしま
う。従って、前記凸部3aの上面面積は半導体素子5の
下面面積に対して40%以上のものに特定される。
Further, if the area of the upper surface of the projection 3a is less than 40% of the area of the lower surface of the semiconductor element 5, the heat generated by the semiconductor element 5 cannot be efficiently transmitted to the metal circuit board 3 and the ceramic substrate 1. In addition, the temperature of the semiconductor element 5 becomes high, causing the semiconductor element 5 to undergo thermal destruction and thermal degradation in characteristics. Therefore, the area of the upper surface of the projection 3a is specified to be 40% or more of the area of the lower surface of the semiconductor element 5.

【0032】また更に前記凸部3aを有する金属回路板
3はその表面にニッケルから成る良導電性で、かつ耐蝕
性及びロウ材との濡れ性が良好な金属をメッキ法により
被着させておくと、金属回路板3と外部電気回路とを電
気的に接続する際、その電気的接続を良好と成すととも
に金属回路板3に半導体素子5を半田6を介して接合さ
せる際、その接合を強固とすることができる。従って、
前記凸部3aを有する金属回路板3はその表面にニッケ
ルから成る良導電性で、かつ耐蝕性及びロウ材との濡れ
性が良好な金属をメッキ法により被着させておくことが
好ましい。
Further, the metal circuit board 3 having the projections 3a is coated on its surface with a metal made of nickel and having good conductivity, good corrosion resistance and good wettability with the brazing material by plating. When the metal circuit board 3 is electrically connected to an external electric circuit, the electrical connection is good, and when the semiconductor element 5 is joined to the metal circuit board 3 via the solder 6, the joining is firmly performed. It can be. Therefore,
It is preferable that the metal circuit board 3 having the protrusions 3a is coated with a metal having good conductivity and good corrosion resistance and good wettability with the brazing material by a plating method.

【0033】前記金属回路板3はその表面にニッケルか
ら成るメッキ層を被着させる場合、内部に燐を8〜15
重量%含有させてニッケル−燐のアモルファス合金とし
ておくとニッケルから成るメッキ層の表面酸化を良好に
防止してロウ材との濡れ性等を長く維持することができ
る。従って、前記金属回路板3の表面にニッケルから成
るメッキ層を被着させる場合、内部に燐を8〜15重量
%含有させてニッケル−燐のアモルファス合金としてお
くことが好ましい。
In the case where a plating layer made of nickel is applied to the surface of the metal circuit board 3, the metal circuit board 3 contains 8 to 15 phosphorus therein.
When the amorphous alloy of nickel-phosphorus is contained in an amount of 0.5% by weight, the oxidation of the surface of the plating layer made of nickel can be prevented well, and the wettability with the brazing material can be maintained for a long time. Therefore, when a plating layer made of nickel is applied to the surface of the metal circuit board 3, it is preferable to contain 8 to 15% by weight of phosphorus therein to form a nickel-phosphorus amorphous alloy.

【0034】なお、前記金属回路板3の表面にニッケル
−燐のアモルファス合金からなるメッキ層を被着させる
場合、ニッケルに対する燐の含有量が8重量%未満、あ
るいは15重量%を超えたときニッケル−燐のアモルフ
ァス合金を形成するのが困難となってメッキ層に半田を
強固に接着させることができなくなる危険性がある。従
って、前記金属回路板3の表面にニッケル−燐のアモル
ファス合金からなるメッキ層を被着させる場合いはニッ
ケルに対する燐の含有量を8〜15重量%の範囲として
おくことが好ましく、好適には10〜15重量%の範囲
がよい。
When a plating layer made of a nickel-phosphorus amorphous alloy is applied to the surface of the metal circuit board 3, if the content of phosphorus with respect to nickel is less than 8% by weight or more than 15% by weight, nickel is added. There is a danger that it becomes difficult to form an amorphous alloy of phosphorus and the solder cannot be firmly bonded to the plating layer. Therefore, when a plating layer made of a nickel-phosphorus amorphous alloy is applied to the surface of the metal circuit board 3, the content of phosphorus with respect to nickel is preferably set in the range of 8 to 15% by weight, and more preferably. The range of 10 to 15% by weight is good.

【0035】また、前記金属回路板3の表面に被着され
るニッケルから成るメッキ層は、その厚みが1.5μm
未満の場合、金属回路板3の表面をニッケルから成るメ
ッキ層で完全に被覆することができず、金属回路板3の
酸化腐蝕を有効に防止することができなくなる危険性が
あり、また3μmを超えるとニッケルから成るメッキ層
の内部に内在する内在応力が大きくなってセラミック基
板1に反りや割れ等が発生してしまう。特にセラミック
基板1の厚さが700μm以下の薄いものになった場合
にはこのセラミック基板1の反りや割れ等が顕著となっ
てしまう。従って、前記金属回路板3の表面に被着され
るニッケルから成るメッキ層はその厚みを1.5μm〜
3μmの範囲としておくことが好ましい。
The nickel plating layer deposited on the surface of the metal circuit board 3 has a thickness of 1.5 μm.
If it is less than 3, the surface of the metal circuit board 3 cannot be completely covered with the plating layer made of nickel, and there is a risk that oxidation corrosion of the metal circuit board 3 cannot be effectively prevented. If it exceeds, the intrinsic stress existing inside the plating layer made of nickel becomes large, and the ceramic substrate 1 will be warped or cracked. In particular, when the thickness of the ceramic substrate 1 is as thin as 700 μm or less, warpage or cracking of the ceramic substrate 1 becomes remarkable. Therefore, the thickness of the plating layer made of nickel deposited on the surface of the metal circuit board 3 is 1.5 μm to
It is preferable to set the range to 3 μm.

【0036】前記金属回路板3の凸部3aには半導体素
子5が半田6を介して接合されており、該半田6として
は錫−鉛共晶合金、錫−鉛合金、金−錫合金、金−ゲル
マニウム合金等の金属材料が好適に使用される。
A semiconductor element 5 is joined to the convex portion 3a of the metal circuit board 3 via a solder 6. The solder 6 includes a tin-lead eutectic alloy, a tin-lead alloy, a gold-tin alloy, A metal material such as a gold-germanium alloy is preferably used.

【0037】前記半田6を介しての凸部3aへの半導体
素子5の接合は、半田6が、例えば、錫−鉛共晶合金
(錫:60重量%、鉛:40重量%)からなる場合に
は、錫−鉛共晶合金の粉末に有機溶剤、溶媒を添加混合
して半田ペーストを作製するとともにこれを従来周知の
スクリーン印刷等の印刷技法を用いて凸部3aの上面に
所定パターン、所定厚みに被着させ、次に被着させた半
田ペースト上に半導体素子5を載置させるとともに約1
80℃に加熱し、半田を溶融させることによって行なわ
れる。
The bonding of the semiconductor element 5 to the projection 3a via the solder 6 is performed when the solder 6 is made of, for example, a tin-lead eutectic alloy (tin: 60% by weight, lead: 40% by weight). An organic solvent and a solvent are added to and mixed with a tin-lead eutectic alloy powder to prepare a solder paste, and the solder paste is formed on the upper surface of the convex portion 3a using a conventionally known printing technique such as screen printing. Then, the semiconductor element 5 is placed on the solder paste that has been deposited to a predetermined thickness,
This is performed by heating to 80 ° C. and melting the solder.

【0038】なお、本発明は上述の実施例に限定される
ものではなく、本発明の趣旨を逸脱しない範囲であれば
種々の変更は可能であり、例えば、上述の実施例ではセ
ラミック基板1が酸化アルミニウム質焼結体で形成され
た例を示したが、半導体素子5が多量の熱を発し、この
熱を効率良く除去したい場合にはセラミック基板1を熱
伝達率の高い窒化アルミニウム質焼結体や窒化珪素質焼
結体で形成すれば良く、金属回路板3に高速で電気信号
を伝播させたい場合にはセラミック基板1を誘電率の低
いムライト質焼結体で形成すれば良い。
It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. Although an example in which the semiconductor element 5 is formed of an aluminum oxide sintered body is shown, when the semiconductor element 5 generates a large amount of heat and the heat is to be efficiently removed, the ceramic substrate 1 is sintered with an aluminum nitride based material having a high heat transfer coefficient. The ceramic substrate 1 may be formed of a mullite sintered body having a low dielectric constant when it is desired to transmit an electric signal to the metal circuit board 3 at high speed.

【0039】また上述の実施例ではセラミック基板1の
表面に予めメタライズ金属2を被着させておき、該メタ
ライズ金属層2に金属回路板3をロウ付けしてセラミッ
ク回路基板となしたが、これをセラミック基板1の表面
に、例えば、銀−銅共晶合金にチタンもしくは水素化チ
タンを2〜5重量%添加した活性金属ロウ材を介して直
接金属回路板3を取着させてセラミック回路基板を形成
してもよい。
In the above-described embodiment, the metallized metal 2 is previously applied to the surface of the ceramic substrate 1 and the metal circuit board 3 is brazed to the metallized metal layer 2 to form a ceramic circuit board. Is attached directly to the surface of the ceramic substrate 1 via an active metal brazing material obtained by adding titanium or titanium hydride to a silver-copper eutectic alloy in an amount of 2 to 5% by weight, for example. May be formed.

【0040】さらに上述の実施例では金属回路板3の上
面に形成される凸部3aは金属回路板3と一体に形成し
たが、凸部3aを金属回路板3と同様の材料、方法で別
体に形成しておき、ロウ材等の接着材を介して金属回路
板3の上面に凸部3aを接着固定してもよい。
Further, in the above-described embodiment, the projection 3a formed on the upper surface of the metal circuit board 3 is formed integrally with the metal circuit board 3. However, the projection 3a is formed separately by the same material and method as the metal circuit board 3. The protrusions 3a may be formed on the body, and the protrusions 3a may be bonded and fixed to the upper surface of the metal circuit board 3 via an adhesive such as brazing material.

【0041】[0041]

【発明の効果】本発明のセラミック回路基板によれば、
金属回路板の上面に半導体素子が載置される凸部を形成
するとともに該凸部の高さを50μm乃至200μmと
し、かつ凸部の外周と半導体素子の外周との間に100
μm以上の差が形成されるよう凸部の外形寸法を半導体
素子の外形寸法より小さくしつつ半導体素子の下面面積
に対する凸部の上面面積の比率を40%以上としたこと
から金属回路板に設けた凸部に半導体素子を載置させる
とともに接着材としての半田を介して接合させた場合、
半導体素子の下面と凸部側面と凸部周囲の金属回路板上
面との間に適度な容積の空間が形成されるとともに該空
間内及び半導体素子の下面と凸部上面との間に半田が充
填介在されることとなり、その結果、金属回路板に設け
た凸部への半導体素子の半田を介しての接合が三次元的
となって接合強度を極めて強いものとし、半導体素子を
凸部上面に確実、強固に接合させることができる。
According to the ceramic circuit board of the present invention,
A convex portion on which the semiconductor element is mounted is formed on the upper surface of the metal circuit board, the height of the convex portion is set to 50 μm to 200 μm, and 100 μm is provided between the outer periphery of the convex portion and the outer periphery of the semiconductor element.
Since the ratio of the upper surface area of the convex portion to the lower surface area of the semiconductor device is set to 40% or more while the external size of the convex portion is made smaller than the external size of the semiconductor device so that a difference of not less than μm is formed, the convex portion is provided on the metal circuit board. When the semiconductor element is mounted on the convex part and joined via solder as an adhesive,
A space having an appropriate volume is formed between the lower surface of the semiconductor element, the side surface of the convex portion, and the upper surface of the metal circuit board around the convex portion, and solder is filled in the space and between the lower surface of the semiconductor device and the upper surface of the convex portion. As a result, the bonding of the semiconductor element to the protrusion provided on the metal circuit board via solder becomes three-dimensional, and the bonding strength becomes extremely strong. It can be securely and firmly joined.

【0042】また同時に金属回路板に設けた凸部に半導
体素子を接着材としての半田を介して接合させた場合、
半導体素子と凸部とは適度な面積で当接して半導体素子
の作動時に発生する熱は金属回路板及びセラミック基板
に効率良く伝達されることとなり、その結果、半導体素
子は常に適温となり、半導体素子を長期間にわたり正
常、かつ安定に作動させることが可能となる。
At the same time, when the semiconductor element is bonded to the projection provided on the metal circuit board via solder as an adhesive,
The semiconductor element and the protrusion come into contact with an appropriate area, and the heat generated during operation of the semiconductor element is efficiently transmitted to the metal circuit board and the ceramic substrate. As a result, the semiconductor element always has an appropriate temperature, and Can operate normally and stably over a long period of time.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のセラミック回路基板の一実施例を示す
断面図である。
FIG. 1 is a sectional view showing one embodiment of a ceramic circuit board of the present invention.

【符号の説明】[Explanation of symbols]

1・・・・セラミック基板 2・・・・メタライズ金属層 3・・・・金属回路板 3a・・・凸部 5・・・・半導体素子 6・・・・半田 DESCRIPTION OF SYMBOLS 1 ... Ceramic substrate 2 ... Metallized metal layer 3 ... Metal circuit board 3a ... Convex part 5 ... Semiconductor element 6 ... Solder

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】セラミック基板の上面に金属回路板を取着
するとともに該金属回路板の上面に半導体素子が載置さ
れる凸部を形成して成り、前記凸部が下記式を満足する
ことを特徴とするセラミック回路基板。 200μm≧H≧50μm L≧100μm S≧40% H:凸部の高さ L:(半導体素子の外周)−(凸部の外周) S:半導体素子の下面面積に対する凸部の上面面積の比
1. A metal circuit board is mounted on an upper surface of a ceramic substrate, and a convex portion on which a semiconductor element is mounted is formed on the upper surface of the metal circuit plate, wherein the convex portion satisfies the following expression. A ceramic circuit board characterized by the above-mentioned. 200 μm ≧ H ≧ 50 μm L ≧ 100 μm S ≧ 40% H: Height of convex portion L: (periphery of semiconductor device) − (periphery of convex portion) S: Ratio of upper surface area of convex portion to lower surface area of semiconductor device
JP2000223791A 2000-07-25 2000-07-25 Semiconductor device Expired - Fee Related JP4471470B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000223791A JP4471470B2 (en) 2000-07-25 2000-07-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000223791A JP4471470B2 (en) 2000-07-25 2000-07-25 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2002043478A true JP2002043478A (en) 2002-02-08
JP4471470B2 JP4471470B2 (en) 2010-06-02

Family

ID=18717836

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP4471470B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007110001A (en) * 2005-10-17 2007-04-26 Fuji Electric Holdings Co Ltd Semiconductor device
JP2011054732A (en) * 2009-09-01 2011-03-17 Toyota Motor Corp Semiconductor module
JP2011159994A (en) * 2011-04-12 2011-08-18 Fuji Electric Co Ltd Semiconductor device
JP2012059876A (en) * 2010-09-08 2012-03-22 Sanken Electric Co Ltd Semiconductor module and manufacturing method of the same
JP2013219194A (en) * 2012-04-09 2013-10-24 Sansha Electric Mfg Co Ltd Semiconductor device
JP2014154571A (en) * 2013-02-05 2014-08-25 Nippon Steel & Sumikin Electronics Devices Inc Power module substrate

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007110001A (en) * 2005-10-17 2007-04-26 Fuji Electric Holdings Co Ltd Semiconductor device
JP2011054732A (en) * 2009-09-01 2011-03-17 Toyota Motor Corp Semiconductor module
JP2012059876A (en) * 2010-09-08 2012-03-22 Sanken Electric Co Ltd Semiconductor module and manufacturing method of the same
JP2011159994A (en) * 2011-04-12 2011-08-18 Fuji Electric Co Ltd Semiconductor device
JP2013219194A (en) * 2012-04-09 2013-10-24 Sansha Electric Mfg Co Ltd Semiconductor device
JP2014154571A (en) * 2013-02-05 2014-08-25 Nippon Steel & Sumikin Electronics Devices Inc Power module substrate

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