JP2002027284A - Clamping circuit for analog video signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve long holding performance and short converging performance in the clamping circuit of an analog video signal. SOLUTION: In the clamping circuit of the analog video signal, a first capacitor C1 holds the signal of a difference between the level of an optical black signal included in the analog video signal SIG1 and a reference level Vc as a correction signal SIG2, a subtracter SUB connected to the first capacitor C, subtracts the correction signal SIG2 from the analog video signal SIG1, and the DC component of the analog video signal SIG1 is reproduced. The series circuit of a first switch SW3 and a second capacitor C2 is connected to both ends of the first capacitor C1 in parallel. The series circuit of a buffer amplifier AMP1 and a second switch SW2 is connected from the connection point of the first capacitor C1 and the subtracter SUB to the connection point of the first switch SW3 and the second capacitor C2. In a period when the optical black signal appears in the analog video signal SIG1, the first switch SW3 is opened and the second switch SW2 is closed. In a period except for the optical black signal period, the first switch SW3 is closed and the second switch SW2 is opened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clamp circuit for reproducing a DC component of an analog video signal.

[0002]

2. Description of the Related Art An optical black signal (hereinafter referred to as an optical black signal or simply an OB signal) included in an analog video signal is sampled, and the OB signal level is clamped to a reference level to correct the analog video signal. A clamp circuit for reproducing a DC component of an analog video signal is known (for example, see Japanese Patent Application Laid-Open No. 05-153429).

FIG. 1 shows a conventional analog video signal clamping circuit. The capacitor C1 clamps the OB signal level to a predetermined DC reference level Vc and
Holds a correction signal SIG2 for correcting IG1. Subtractor S
The UB reproduces the DC component of the analog video signal SIG1 by subtracting the correction signal SIG2 from the analog video signal SIG1. A / D
The converter A / D converts the video signal SIG3 obtained by reproducing the DC component into a digital signal and outputs the digital signal.

As shown in FIG. 2A, an OB signal is inserted at the end of the video signal SIG1 every horizontal scanning period.
This OB signal level is clamped to the reference level Vc.
Specifically, during the OB period, the OB signal SI is output from the comparator COMP.
The level of G3 is compared with the reference level Vc, and the difference is expressed as D
The signal is converted into an analog signal by the / A converter D / A. Switch SW1
Is an electronic switch driven by a clamp pulse signal (see FIG. 2B) which becomes high only during the OB period.
The contacts are closed during the OB period, and are opened during periods other than the OB period. As a result, the signal of the difference between the OB signal level and the reference level Vc is charged in the capacitor C1 during the OB period, and the correction signal SIG2 is generated.

[0005] The signal SIG2 held in the capacitor C1 is
OB signal level and reference level V included in video signal SIG1
This is a voltage signal corresponding to the difference from c, which is a correction signal for correcting the video signal SIG1 by clamping the OB signal level to the reference level Vc and reproducing the DC component of the analog video signal SIG1.

[0006]

The conventional analog video signal clamping circuit is implemented as an IC in order to reduce the size and cost, and the difference signal between the OB signal level and the reference level Vc is converted to a capacitor C1. D / to charge
The output stage of the A converter D / A is constituted by a low current output buffer amplifier. Therefore, the difference signal between the OB signal level and the reference level Vc is charged into the capacitor C1 and the correction signal S
When IG2 is generated, there is a problem that charging time is long and short convergence performance, which is one of the important performances of the clamp circuit, cannot be improved.

[0007] If the capacitance of the capacitor C1 is reduced, the charging time is shortened and the short convergence performance can be improved. However, in this case, the long retention performance, which is another important performance of the clamp circuit, is reduced. Clamp capacitor C1
The correction signal SIG2 held in at least the video signal SIG1
Must be maintained within the allowable variation rate during one horizontal scanning period, it is necessary to increase the capacitance of the capacitor C1 in order to improve the long holding performance of the clamp circuit.

An object of the present invention is to improve both the long holding performance and the short convergence performance of an analog video signal clamping circuit.

[0009]

The present invention will be described with reference to FIG. 3 showing a circuit according to one embodiment. (1) The invention of claim 1 provides an optical black signal contained in an analog video signal SIG1. Is held as a correction signal SIG2 by the first capacitor C1, and a subtractor SUB connected to the first capacitor C1 subtracts the correction signal SIG2 from the analog video signal SIG1 to obtain an analog video signal. It is applied to an analog video signal clamp circuit for reproducing the DC component of the signal SIG1. A series circuit of a first switch SW3 and a second capacitor C2 is connected in parallel to both ends of the first capacitor C1, and a first switch SW3 and a second capacitor C2 are connected from a connection point between the first capacitor C1 and the subtractor SUB. To the connection point with the buffer amplifier AMP1
And the series circuit of the second switch SW2, and the first switch SW is connected during the period when the optical black signal appears in the analog video signal SIG1.
3 is opened to close the second switch SW2, and during periods other than the optical black signal period, the first switch SW3 is closed and the second switch SW2 is opened to achieve the above object. (2) According to the invention of claim 2, a signal of a difference between the level of the optical black signal included in the analog video signal SIG1 and the reference level Vc is held by the first capacitor C1 as a correction signal SIG2, and is stored in the first capacitor C1. This is applied to an analog video signal clamping circuit that reproduces the DC component of the analog video signal SIG1 by subtracting the correction signal SIG2 from the analog video signal SIG1 by the connected subtractor SUB. Then, instead of the first capacitor C1, a series circuit of the first switch SW3 and the second capacitor C2 is connected to the subtractor SUB, and a connection point between the series circuit of the first switch SW3 and the second capacitor C2 and the subtractor SUB. From the buffer amplifier AMP1 to the connection point between the first switch SW3 and the second capacitor C2
The series circuit of SW2 is connected, the first switch SW3 is opened and the second switch SW2 is closed during the period when the optical black signal appears in the analog video signal SIG1, and the first switch SW3 is closed during periods other than the optical black signal period. Is closed and the second switch SW3 is opened to achieve the above object. (3) In the analog video signal clamping circuit according to claim 3, the capacity of the second capacitor C2 is larger than the capacity of the first capacitor C1.

In the section of the means for solving the above-mentioned problem, a diagram of one embodiment is used for easy understanding of the description, but the present invention is not limited to this embodiment. .

[0011]

FIG. 3 shows the configuration of one embodiment. Note that the same reference numerals are given to the same devices as the circuit devices shown in FIG. 1, and the description will focus on the differences.

In this embodiment, a buffer amplifier AMP1 and an electronic switch SW are added to the conventional clamp circuit shown in FIG.
2. Add a circuit consisting of SW3 and capacitor C2. Specifically, the switch SW is connected to both ends of the capacitor C1.
A series circuit of 3 and a capacitor C2 is connected, and a series circuit of a buffer amplifier AMP1 and a switch SW2 is connected from a connection point between a capacitor C1 and a subtractor SUB to a connection point between a switch SW3 and a capacitor C2.

The buffer amplifier AMP1 has a D / A converter D / A
This is a large current amplifier that amplifies a signal having a difference between the OB signal level output from A and the reference level Vc. Switch SW2
Is an electronic switch driven by a pulse signal (see FIG. 2B) which becomes high only during the OB period. The contact is closed during the OB period, and the contact is open during periods other than the OB period.
The switch SW3 is an electronic switch that is driven by a pulse signal (see FIG. 2C) that goes low only during the OB period. The contact is open during the OB period, and the contact is closed during periods other than the OB period.

The capacitor C2 is connected in parallel with the capacitor C1 by closing the switch SW3 during a period other than the OB period, and holds the correction signal SIG2 together with the capacitor C1. Note that the capacity of the capacitor C2 is made larger than the capacity of the capacitor C1.

During the OB period, the switches SW1 and SW2 are both closed and the switch SW3 is open, so that the D / A converter D / A
The signal of the difference between the OB signal level and the reference level Vc output from the controller C1 is charged not only to the capacitor C1 but also to the capacitor C2 via the buffer amplifier AMP1.

Generally, the charging time Tc of the capacitor is expressed by the following equation.

Tc = (CV) / I where C is the capacitance of the capacitor, V is the charging voltage of the capacitor, and I is the charging current. As is apparent from Equation 1, the time Tc for charging the terminal voltage of the capacitor to the voltage V decreases as the charging current I increases and the capacitance C decreases.

As described above, since the output buffer of the D / A converter D / A is of a low current type, the charging current I of the capacitor C1 cannot be increased. However, the charging time Tc can be reduced by reducing the capacitance C of the capacitor C1.
Can be shortened. On the other hand, since the capacitor C2 is charged by the large current buffer amplifier AMP1, the charging current I can be increased, and the charging can be performed in a short time even if the capacitance C is large.

During periods other than the OB period, the switches SW1 and SW2
Are both opened, and the switch SW3 is closed instead. Therefore, the capacitors C1 and C2 are connected in parallel, and the correction signal SIG2 is held by both the capacitors C1 and C2.

Generally, the voltage holding time Th of the capacitor
Is represented by the following equation.

Th = (C · V) / i where C is the capacity of the capacitor, V is the holding voltage of the capacitor, and i is the leakage current such as the input bias current of the subtractor SUB. As is apparent from Expression 2, the holding time Th of the voltage V of the capacitor becomes longer as the capacitance C is larger and the leakage current i is smaller.

Although it is difficult to reduce the leakage current i, the voltage holding time Th can be lengthened by making the capacity of the capacitor C2 sufficiently larger than C1. As a result, the correction signal SIG2 can be held within the allowable variation rate during one horizontal scanning period of the video signal SIG1, and the long holding performance of the clamp circuit can be improved.

Since the long holding performance of the clamp circuit can be improved by the large current buffer amplifier AMP1 and the large capacity capacitor C2, conversely, the capacity of the capacitor C1 is made smaller than before and the battery is charged with the low current buffer. Even in this case, charging can be performed in a short time, and the short convergence performance of the clamp circuit can be improved.

That is, according to the clamp circuit of this embodiment, it is possible to improve both the short convergence performance and the long holding performance, which are two important performances of the clamp circuit.

<< Modification of One Embodiment of the Invention >> In the clamp circuit of one embodiment shown in FIG.
C1 may be deleted. In this case, the capacity of the capacitor C2 is set to a capacity capable of improving the long holding performance of the clamp circuit, and the current capacity of the buffer amplifier AMP1 is set to a capacity capable of improving the short convergence performance of the clamp circuit. Thereby, a clamp circuit can be configured only by the capacitor C2, and in addition to the effects of the above-described embodiment,
Cost reduction and size reduction can be achieved.

<< Another Modification of One Embodiment of the Invention >> In the above-described embodiment, an example is shown in which the OB signal is converted into a digital signal and then compared with the reference level Vc, as shown in FIG. The same applies to the clamp circuit that compares the analog OB signal with the analog reference level Vc by the comparator CMP and outputs the difference signal between the two from the comparator CMP by adding the circuit of the above-described embodiment. Effects can be obtained. In FIG. 4, the same reference numerals are given to devices similar to the circuit devices shown in FIG.

According to the present invention, in addition to the clamp circuit described above, the difference between the OB signal level included in the analog video signal and the reference level is held as a correction signal by a capacitor, and the correction signal is subtracted from the analog video signal. As a result, the present invention can be applied to all clamp circuits for reproducing the DC component of the analog video signal, and both the short convergence performance and the long hold performance of the clamp circuit can be improved.

[0026]

(1) As described above, according to the first aspect of the invention, the first capacitor and the second capacitor are connected in parallel during a period other than the optical black signal period, and the correction signal is supplied to both capacitors. Therefore, the long holding performance of the clamp circuit can be improved. Also, during the optical black signal period, the first capacitor is charged by the signal of the difference between the optical black signal level and the reference level as in the related art, but the second capacitor receives the difference signal via the buffer amplifier. Since the battery is charged, the short convergence performance of the clamp circuit can be improved even if the second capacitor is added. (2) According to the second aspect of the present invention, the difference signal is charged in a short time to the second capacitor via the buffer amplifier while increasing the capacity of the second capacitor to improve the long holding performance of the clamp circuit. Also, the short convergence performance of the clamp circuit can be improved. Furthermore, the cost can be reduced and the size can be reduced by removing the first condenser. (3) According to the third aspect of the invention, the long holding performance and the short convergence performance of the clamp circuit can be further improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a conventional analog video signal clamping circuit.

FIG. 2 is a diagram showing a video signal, an OB signal, and a clamp pulse signal.

FIG. 3 is a diagram illustrating a clamp circuit for an analog video signal according to an embodiment;

FIG. 4 is a diagram illustrating a clamp circuit for an analog video signal according to a modified example.

[Explanation of symbols]

 C1, C2 Capacitor SUB Subtractor A / D A / D converter COMP comparator D / A D / A converter SW1, SW2, SW3 Switch AMP1 Buffer amplifier CMP comparator

Claims (3)

[Claims] 1. A first capacitor that holds a signal of a difference between a level of an optical black signal included in an analog video signal and a reference level as a correction signal, and that is output by a subtractor connected to the first capacitor. An analog video signal clamping circuit for reproducing the DC component of the analog video signal by subtracting the correction signal from the analog video signal, wherein a series circuit of a first switch and a second capacitor is connected in parallel to both ends of the first capacitor; A period in which a series circuit of a buffer amplifier and a second switch is connected from a connection point between a first capacitor and the subtractor to a connection point between the first switch and the second capacitor, and an optical black signal appears in an analog video signal. Opens the first switch and closes the second switch. During periods other than the optical black signal period, A clamp circuit for an analog video signal, wherein one switch is closed and the second switch is opened. 2. The method according to claim 1, wherein a signal of a difference between the level of the optical black signal included in the analog video signal and a reference level is held as a correction signal by a first capacitor, and the analog video signal is output by a subtractor connected to the first capacitor. In the analog video signal clamp circuit for reproducing the DC component of the analog video signal by subtracting the correction signal from the analog signal, a series circuit of a first switch and a second capacitor is connected to the subtractor instead of the first capacitor. A buffer amplifier and a second switch from a connection point between the series circuit of the first switch and the second capacitor and the subtractor to a connection point between the first switch and the second capacitor.
A series circuit of switches is connected, the first switch is opened and the second switch is closed during a period when an optical black signal appears in the analog video signal, and the first switch is closed during a period other than the optical black signal period. Wherein the second switch is opened by closing the circuit. 3. The analog video signal clamping circuit according to claim 1, wherein a capacitance of said second capacitor is larger than a capacitance of said first capacitor. circuit.