JPH0660540A - Signal correction circuit - Google Patents

Abstract

PURPOSE:To correct a bit fault by comparing a difference between signals before and after a present video signal so that an abnormal pulse for the flow of the signal may be detected and removed. CONSTITUTION:Whether the data of a register 2 is updated or held is selected by a changeover switch 9. A difference detection circuit 3 detects and outputs the difference between the data quantity of a register 1 and the data quantity of a video signal 10. Then, a difference detection circuit 4 detects and outputs the difference between the data quantities of the registers 1 and 2. A comparator circuit 5 compares the data quantity obtained by the circuit 3 with the data quantity of a reference level signal 7, a comparator circuit 6 compares the data quantity obtained by the circuit 4 with the data quantity of the signal 7, and they respectively output compared results, which is larger or smaller. In the case the output from the circuits 5 and 6 shows that both the data quantities obtained by the circuits 3 and 4 exceed the data quantity of the signal 7, a decision circuit 8 outputs a control signal so as to allow the switch 9 to change over to the output side of the register 2 so that the data may be held. In the case one or either of the data quantities does not exceed, the data of the register 2 is updated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal correction circuit, and more particularly to a video signal correction circuit in a VTR.

[0002]

2. Description of the Related Art Conventionally, a field or frame correlation is used in a circuit very close to a video signal correction circuit, and FIG. 3 is a block diagram showing an example thereof.
It uses field correlation.

In FIG. 3, the video signal input 10 is connected to the plus side input of the subtraction circuit 12 and the plus side input of the subtraction circuit 13, and the output of the subtraction circuit 12 is connected to the storage circuit 15 and the output of the storage circuit 15. Is connected to the minus side input of the subtraction circuit 13, the output of the subtraction circuit 13 is connected to the amplification circuit 14, the output of the amplification circuit 14 is connected to the minus side input of the subtraction circuit 12, and the output of the subtraction circuit 12 is the video signal. The output is 11.

Next, the operation of this conventional example will be described. The subtraction circuit 13 inputs the video signal 10 to the plus side input.
And a video signal obtained by delaying the output of the subtraction circuit 12 by one field by the storage circuit 15 is input to the minus side input. The subtraction circuit 12 inputs the video signal 10 to the plus side input.
And the video signal obtained by multiplying the output of the subtraction circuit 13 by K times by the amplification circuit 14 is input to the negative side input. The video signal output 11 is obtained from the subtraction circuit 12. From this, the following relational expression is obtained.

Output 11 = input 10- (input 10-output 11 ') K = input 10 (1-K) + output 11'K However, input 11' is a value delayed by one field. Since the input 10 is the current video signal and the output 11 'is the video signal one field before, the signal component having the correlation between the video signal one field before and the current is emphasized and the video signal having no correlation is attenuated. To be done.

[0006]

In the signal correction circuit according to the conventional example, when storage media such as a video tape and a storage circuit made of a semiconductor are connected and a bit failure occurs in these media, they are placed at the same position on the screen. An abnormal 1-bit signal may be generated. However, the conventional signal correction circuit that uses the correlation of the previous video signal due to the field correlation and the frame correlation has the drawback that it cannot be corrected because it is at the same position.

An object of the present invention is to provide a signal correction circuit which solves the above-mentioned drawbacks and can correct a bit failure.

[0008]

According to the structure of the signal correction circuit of the present invention, when the signal input is at N + 1 time point, the first holding circuit for holding the signal at N time point and the signal at N-1 time point are stored. A second holding circuit for detecting the difference between the signal at the N time point and the signal at the N-1 time point, and a second difference detecting circuit for detecting the difference between the N time signal and the N + 1 time signal. Difference detection circuit, a first comparison circuit that compares the output of the first difference detection circuit and a reference level input, and a second comparison circuit that compares the output of the second difference detection circuit and the reference level input. Inputting the output of the first comparison circuit and the output of the second comparison circuit, and outputs a signal for switching the N time point to the N-1 time point when they are separated by a reference level or more. A determination circuit, an output of the first holding circuit and an output of the second holding circuit Input and a changeover switch to control an output of the decision circuit, characterized in that as the signal output inputs the output of the switch to the second holding circuit.

[0009]

1 is a block diagram showing a signal correction circuit according to an embodiment of the present invention. In FIG. 1, in this embodiment, the video signal input 10 is connected to the register 1, the output of the register 1 is connected to one of the changeover switches 9, the output of the changeover switch 9 is connected to the register 2, and the output of the register 2 is shown. Is connected to the other of the changeover switch 9, one of the inputs of the difference detection circuit 3 is connected to the output of the register 1 to the other, and one of the inputs of the difference detection circuit 4 is connected to the output of the register 2 to the other. The output of the register 1 is connected, the output of the difference detection circuit 3 is connected to one side of the comparison circuit 5, the reference level signal 7 is connected to the other side, and the output of the difference detection circuit 4 is connected to one side of the comparison circuit 6 and the reference level signal 7 is connected to the other side. The output of the comparison circuit 5 and the output of the comparison circuit 6 are connected to the determination circuit 8, the output of the determination circuit 8 is connected to the control input of the changeover switch 9, and the output of the register 2 is the video signal output 11. .

Next, the operation of the embodiment shown in FIG. 1 will be described. The register 1 inputs the video signal input 10 and inputs the output of the register 1 to one of the changeover switches 9. The register 2 receives the output of the changeover switch 9 and outputs it to the other input of the same changeover switch 9. Changeover switch 9
Selects whether to update or hold the data of the register 2 by this. The difference detection circuit 3 inputs the output of the register 1 to one side and the video signal input 10 to the other side, detects the difference between the data amount of the register 1 and the data amount of the video signal input 10, and outputs the difference. The difference detection circuit 4 inputs the output of the register 2 to one side and the output of the register 1 to the other side, detects the difference between the data amount of the register 2 and the data amount of the register 1, and outputs it.

The comparison circuit 5 compares and outputs whether the amount of data obtained by the difference detection circuit 3 is larger or smaller than the amount of data of the reference level signal 7. Further, the comparison circuit 6 compares and outputs whether the data amount obtained by the difference detection circuit 4 is larger or smaller than the data amount of the reference level signal 7.

The determination circuit 8 outputs a control signal when the outputs of the comparison circuits 5 and 6 both exceed the data amount of the reference level signal 7 obtained by the difference detection circuit 3 and the difference detection circuit 4. Output and register 2 by changeover switch 9
Switch to the output side of and hold the data. If one or both of the data amounts obtained by the difference detection circuit 3 and the difference detection circuit 4 do not exceed the data amount of the reference level signal 7, a control signal is output and the output of the register 1 is output by the changeover switch 9. The data of the register 2 is updated by switching to the side.

This embodiment will be described in detail with reference to FIG. When the reference level signal 7 is VR and the points A, B, and C in the video signal input 10 of the waveform j in the figure have the following relationship with VR, the level at point B-the level at point A | <VR, | level at point C-level at point B | <VR.

In both cases, the amount of data exceeds the reference level signal 7, the output of the decision circuit 8 is a high level as shown by the waveform m in the figure, and the changeover switch 9 is switched to the register 2 side in the figure. For the output of the register 1 of the waveform k, the data of the point A held in the register 2 is output to the register 2 again, so that the register 2 of the waveform 1 in the figure
The output of point A is repeated twice like the output of. Therefore, the video signal output 11 has a waveform without point B like the waveform n in the figure.

Next, when the points D, E, and F have the following relationship, the level at the point B-the level at the point A <VR, |
Level at point C-Level at point B> VR.

This is because the data amount obtained by the difference detection circuit 4 only exceeds the data amount of the reference level signal 7, so the output of the decision circuit 8 remains at the low level of the waveform m in the figure, and the register 2 The output of the register 1 is the same as the output of the input register 2, and the output of the input register 2 is continuous with D, E, and F as shown by the waveform 1 in the figure. The video signal output 11 at this time becomes D, E, and F of the waveform n in the figure, which is the same output as the input.

In the embodiment of the present invention, if the data is taken into the register by 4 fsc (four times the subcarrier), the signal can be corrected by the correlation with the horizontal direction of the screen. With this, it becomes possible to correct the signal in correlation with the vertical direction of the screen.

Another embodiment of the present invention is also possible in that signal correction in correlation with the horizontal direction of the screen is made by inputting an analog video signal, which is shown in FIG. In FIG. 4, this embodiment can be realized by using sample-hold circuits 16 and 17 as holding circuits, operational amplifiers in the difference detection circuits 3 and 4, and comparators in the comparison circuits 5 and 6 to input the reference level signal. Also becomes an analog input. Other parts are the same as in FIG.

[0019]

As described above, the present invention is designed to detect and remove an abnormal pulse with respect to a signal flow by comparing the difference between the preceding and following signals with respect to the current video signal. Therefore, there is an effect that the abnormal signal can be completely removed, the visual image quality is improved and it is easy to see, and the data other than the abnormal signal is output as it is, so that the image reproducibility is good.

Since the reference level signal 7 shown in FIGS. 1 and 4 can be used to set the level at which the signal can be corrected from the outside, there is also an advantage that an effect corresponding to the system to be incorporated can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a signal correction circuit according to an embodiment of the present invention.

FIG. 2 is a timing diagram showing the signal correction circuit of FIG.

FIG. 3 is a block diagram showing a conventional signal correction circuit.

FIG. 4 is a block diagram showing a signal correction circuit according to another embodiment of the present invention.

[Explanation of symbols]

 1, 2 Shift register 3, 4 Difference detection circuit 5, 6 Comparison circuit 7 Reference level signal 8 Judgment circuit 9 Changeover switch 10 Video signal input 11 Video signal output 12, 13 Subtraction circuit 14 Amplification circuit 15 Storage circuit 16, 17 Sample hold circuit

Claims (3)

[Claims] 1. An input terminal for receiving or inputting a signal at N + 1 time point, a first holding circuit connected to the input terminal for holding a signal at N time point, and a second holding circuit for storing a signal at N-1 time point.
Holding circuit, a first difference detection circuit for detecting a difference between the signal at the N time point and a signal at the N-1 time point, and a first difference detection circuit for detecting a difference between the signal at the N time point and the signal at the N + 1 time point. A second difference detection circuit, a first comparison circuit that compares the output of the first difference detection circuit and a reference level input, and a first comparison circuit that compares the output of the second difference detection circuit and the reference level input. A signal for switching the N time point to the N-1 time point when the output of the first comparison circuit and the output of the second comparison circuit are input to each of the two comparison circuits and the outputs are apart from each other by a reference level or more. A determination circuit for outputting the output of the first holding circuit and an output of the second holding circuit; and a switch for inputting the output of the determination circuit as a control input. Input to the holding circuit of 2 and output as signal Signal correction circuit, characterized in that. 2. The signal correction circuit according to claim 1, wherein each of the first and second holding circuits comprises a register. 3. The first and second holding circuits are both sample and hold circuits, the first and second difference detection circuits are both operation amplifiers, and the first and second comparison circuits are both The signal correction circuit according to claim 1, wherein is also a comparator.