JPH05316393A - Contour correction device - Google Patents

Abstract

PURPOSE:To emphasize contour with a large edge angle of inclination and small overshoot by such a way that an edge period of an input signal is detected for which period a switching means is turned on and the input signal and a contour emphasis signal are added. CONSTITUTION:A switch 26 and an edge detection correction circuit 20 controlling the switch 26 are provided between a sharpness variable resistor 12 and an adder 14. The edge detection correction circuit 20 detects an edge period of a Y signal input to turned on a switch 26 for the period. An output signal of an AND gate 25 is set to a 1st state (H) for a period almost the same as the edge period of an input A of the Y signal. When the signal K is in the 1st state (H), the switch 26 is turned on to allow the adder 14 to add an output signal of a delay line 2 and the contour emphasis signal. When the signal K is in the 2nd state (L) (that is, the Y signal input A is existed in a period other than the edge period), the switch 26 is turned off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a contour correction circuit for a video signal display device such as a television receiver.

[0002]

2. Description of the Related Art Generally, a video signal display device is shown in FIG.
The configuration is as follows. Y / C separation circuit 102
Receives the video signal, separates the luminance signal Y and the color signal C, supplies the luminance signal Y to the contour correction circuit 104, and supplies the color signal C to the decoding circuit 108. Contour correction circuit 1
04 outputs the luminance signal Y whose contour has been corrected. The decoding circuit 108 outputs the color difference signals (RY) and (BY). The matrix circuit 106 includes the contour correction circuit 10
4, the contour-corrected luminance signal Y is received, and the color difference signals (RY) and (B-
Y) to receive the red, blue and green signals R, G and B,
Output to CRT, LCD or other display device.

FIG. 13 shows an example of a conventional contour correction circuit. 14 shows the signal waveform of each part of the contour correction circuit of FIG. In the contour correction circuit I of FIG. 13, the delay line 2 outputs a signal B obtained by delaying the Y signal input A for a predetermined time. The delay line 4 outputs a signal C obtained by delaying the output signal B of the delay line 2 by a predetermined time. The subtractor 6 outputs the difference signal D between the input signal A and the output signal B of the delay line 2. The subtractor 8 outputs a difference signal E between the input signal B and the output signal C of the delay line 4. The adder 14 adds the output signals D and E of the subtracters 6 and 8. Sharpness volume 1
2 adjusts the level of the output signal F of the adder 10 and outputs it as the contour emphasis signal L. The adder 14 adds the output signal of the volume 12, that is, the contour emphasis signal L and the output signal B of the delay line 2 to generate a contour-corrected Y signal output M.

[0004]

Originally, the outline correction is
The purpose is to increase the slope of the signal (dv / dt in FIG. 15), and the overshoot is not ideal per se.
Since the video signal has a large amount of information in the low frequency component, the contour correction should also be performed from the low frequency component. However, in the conventional contour correction circuit of FIG. 13, the contour correction circuit shown in FIG. As described above, a wide overshoot occurs and the image quality deteriorates.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a contour correction circuit capable of enhancing a contour with a large edge inclination angle (that is, an inclination) and a small overshoot. To aim.

[0006]

A contour correction circuit according to a first aspect of the present invention is a contour enhancement signal generating means for generating a contour enhancement signal from an input signal (for example, delay lines 2 and 4 of the embodiment,
Subtractors 6 and 8, an adder 10, and a sharpness volume 12), and a first addition means (for example, the adder 14 of the embodiment) for adding the input signal and the contour emphasis signal.
And a switching means (for example, the switch 2 of the embodiment) arranged between the contour emphasis signal generating means and the first adding means.
6) and edge detection correction means (for example, the edge detection correction circuit 20 or 20C of the embodiment) that detects the edge period of the input signal and turns on the switching means during this period. And

In the contour correction circuit according to a second aspect of the present invention, the contour emphasis signal generating means (1) delays the input signal for a predetermined time and outputs the delayed signal (for example, the delay line 2 of the embodiment). (2) The second delay means (for example, the delay line 4 of the embodiment) that delays the output signal of the first delay means for a predetermined time and outputs the delayed signal, and (3) the input signal and the output signal of the first delay means. First subtraction means (for example, subtractor 6 of the embodiment) that outputs a difference signal, and (4) Second subtraction means (for example, the embodiment of the present invention) that outputs a difference signal between the input signal and the output signal of the second delay means. 8) and (5) second adding means for adding the output signals of the first and second subtracting means (for example, the adder 1 of the embodiment).
4), the edge detection correction means outputs the signal in the first state when the output signal of the first subtraction means is equal to or higher than a predetermined level, and the output signal of the first subtraction means is less than the predetermined level. First detection means that outputs a signal in the second state when (for example, the absolute value circuit 21 and the binarization circuit 22 of the embodiment)
And (b) a signal in the first state is output when the output signal of the second subtracting means is equal to or higher than a predetermined level, and a signal in the second state is output when the output signal of the second subtracting means is less than the predetermined level. A first detection means (for example, the absolute value circuit 23 and the binarization circuit 24 of the embodiment), and (c) a first AND for obtaining the logical product of the output signal of the first detection means and the output signal of the second detection means. AND means (for example, AND gate 25 of the embodiment), and controls the switching means by the output of the first AND means, and when the switching means is in the ON state, the first adding means causes the first delay It is characterized in that the output signal of the means and the contour emphasis signal are added.

In the contour correction circuit according to a third aspect of the present invention, the contour emphasizing signal generating means (1) delays the input signal by a predetermined time and outputs the delayed signal (for example, the delay line 2 of the embodiment). (2) The second delay means (for example, the delay line 4 of the embodiment) that delays the output signal of the first delay means for a predetermined time and outputs the delayed signal, and (3) the input signal and the output signal of the first delay means. First subtraction means (for example, subtractor 6 of the embodiment) that outputs a difference signal, and (4) Second subtraction means (for example, the embodiment of the present invention) that outputs a difference signal between the input signal and the output signal of the second delay means. 8) and (5) second adding means for adding the output signals of the first and second subtracting means (for example, the adder 1 of the embodiment).
0), and the edge detection correction means (a) delays the input signal by a predetermined time and outputs the delayed signal (for example, the delay line 2C of the embodiment), and (b) the third delay means. 4 delay means (for example, the delay line 4C of the embodiment) that delays and outputs the output signal of (1), and (c) third subtraction that outputs the difference signal between the input signal and the output signal of the 3rd delay means. Means (for example, the subtracter 6C of the embodiment), and (d) fourth subtraction means (for example, the subtractor 8C of the embodiment) that outputs a difference signal between the input signal and the output signal of the fourth delay means, e) Third detection for outputting a signal in the first state when the output signal of the third subtracting means is equal to or higher than a predetermined level and outputting a signal in the second state when the output signal of the third subtracting means is less than the predetermined level Means (for example, the absolute value circuit 21C and the binarization circuit 22 of the embodiment)
C) and (f) a signal in the first state is output when the output signal of the fourth subtracting means is equal to or higher than a predetermined level, and a signal in the second state is output when the output signal of the fourth subtracting means is less than the predetermined level. Fourth detecting means for outputting (for example, the absolute value circuit 23C of the embodiment
And a binarization circuit 24C), and (g) second AND means for obtaining the AND of the output signal of the third detection means and the output signal of the fourth detection means (for example, AND gate 25 of the embodiment).
C), (h) a predetermined number of serially connected delay units (for example, the minute delay line D of the embodiment) that receives the output signal of the second AND circuit, and (i) a predetermined number of delays. A first OR means (for example, the OR gate 27 of the embodiment) for obtaining the logical sum of the output signals of the first half of the means, and (j) a logical sum of the output signals of the latter half of the predetermined number of delay means 2 OR means (for example, OR gate 28 of the embodiment), and (k)
Third AND means for obtaining the logical product of the output signals of the first and second AND means (for example, AND gate 2 of the embodiment)
9), the switching means is controlled by the output of the third AND circuit, and when the switching means is in the ON state,
The first adding means adds the output signal of the first delay means and the contour emphasis signal.

[0009]

In the contour correction circuit of the first aspect, the edge period of the input signal is detected, the switching means is turned on during this period, and the input signal and the contour emphasis signal are added. Therefore, the inclination angle of the edge is large,
It is possible to perform contour enhancement with a small overshoot.

According to another aspect of the contour correction circuit of the present invention, in the contour emphasizing signal generating means, the first delay means delays and outputs the input signal for a predetermined time, and the second delay means delays the first delay signal. The output signal of the means is output after being delayed by a predetermined time, the first subtraction means outputs the difference signal between the input signal of the first delay means and the output signal, and the second subtraction means is the input signal of the second delay means. The difference signal between the output signal and
The adding means adds the output signals of the first and second subtracting means. Further, in the edge detection / correction means, the first detection means outputs the signal in the first state when the output signal of the first subtraction means is equal to or higher than the predetermined level, and the output signal of the first subtraction means is less than the predetermined level. When outputting the signal of the second state, the second detecting means outputs the signal of the first state when the output signal of the second subtracting means is equal to or higher than a predetermined level, and the output signal of the second subtracting means is the predetermined level. When it is less than the above, the signal of the second state is output, and the first logical product means obtains the logical product of the output signal of the first detection means and the output signal of the second detection means. Then, the switching means is controlled by the output of the first logical product means,
When the switching means is in the ON state, the first adding means adds the output signal of the first delay means and the contour emphasis signal and outputs the result. Therefore, with a simple configuration, it is possible to perform contour enhancement with a large edge inclination angle and a small overshoot.

According to another aspect of the contour correction circuit of the present invention, in the contour emphasizing signal generating means, the first delay means delays the input signal by a predetermined time and outputs the delayed signal, and the second delay means delays the first delay signal. The output signal of the means is output after being delayed by a predetermined time, the first subtraction means outputs the difference signal between the input signal of the first delay means and the output signal, and the second subtraction means is the input signal of the second delay means. The difference signal between the output signal and
The adding means adds the output signals of the first and second subtracting means. Further, in the edge detection / correction means, the third delay means delays the input signal by a predetermined time and outputs it, and the fourth delay means delays the output signal of the third delay means by a predetermined time and outputs it. The third subtraction means outputs a difference signal between the input signal and the output signal of the third delay means, and the fourth subtraction means outputs a difference signal between the input signal and the output signal of the fourth delay means,
The third detecting means outputs the signal in the first state when the output signal of the third subtracting means is equal to or higher than a predetermined level, and outputs the signal in the second state when the output signal of the third subtracting means is less than the predetermined level. The fourth detecting means outputs the signal in the first state when the output signal of the fourth subtracting means is equal to or higher than the predetermined level, and the signal in the second state when the output signal of the fourth subtracting means is less than the predetermined level. And the second AND means obtains the AND of the output signal of the third detecting means and the output signal of the fourth detecting means, and a predetermined number of delay means connected in series form the second AND means. Of the output signals of the first half of the predetermined number of delay means, and the second OR means outputs the second half of the predetermined number of delay means. The logical sum of the signals is obtained, and the third logical product means outputs the output signals of the first and second logical sum means. Seek Riseki. Then, the switching means is controlled by the output of the third AND means, and when the switching means is in the ON state, the first adding means adds the output signal of the first delay means and the contour emphasis signal. Therefore, the two edges that are close to each other are determined to be a series of edges, so that unnatural emphasis is not applied to signals whose edges are close to each other.

[0012]

1 shows an embodiment of a contour correction circuit according to the present invention. In this embodiment, the contour emphasizing signal generating means for generating the contour emphasizing signal from the Y signal input has a delay line 2 for delaying (1) the Y signal input A by a predetermined time and outputting the same as in the conventional example of FIG. , (2) a delay line 4 which delays the output signal B of the delay line 2 for a predetermined time and outputs the delayed signal, and (3) a subtracter 6 which outputs a difference signal D between the input signal A and the output signal B of the delay line 2. , (4) a subtracter 8 that outputs a difference signal between the input signal B and the output signal C of the delay line 4, and (5) an adder 10 that adds the output signals D and E of the subtractors 6 and 8,
(6) The sharpness volume 12 which adjusts the level of the output signal F of the adder 10 and outputs a contour emphasis signal.

The difference between the embodiment of FIG. 1 and the conventional example of FIG. 13 is that a switch 26 is provided between the sharpness volume 12 and the adder 14, and that the switch 2
That is, the edge detection / correction circuit 20 for controlling the opening / closing of No. The edge detection / correction circuit 20 detects the edge period of the Y signal input, and switches 2 during this period.
Turn 6 on

The edge detection / correction circuit 20 includes (a) an absolute value circuit 21 for outputting the absolute value of the output signal D of the subtractor 6,
(B) The signal in the first state (“H”) is output when the output signal G of the absolute value circuit 21 is equal to or higher than the threshold level, and the second state is output when the output signal G of the absolute value circuit 21 is less than the threshold level. A binarization circuit 22 which outputs a signal of "(L)";
Absolute value circuit 2 for outputting the absolute value of output signal E of subtractor 8
3 and (d) the signal in the first state (“H”) is output when the output signal H of the absolute value circuit 23 is equal to or higher than the threshold level, and when the output signal H of the absolute value circuit 23 is less than the predetermined level. Second
A binarization circuit 24 that outputs a signal of the state (“L”);
(E) The output signal I of the binarization circuit 22 and the binarization circuit 24
AND gate 25 for obtaining a logical product of the output signal J of

The output signal K of the AND gate 25 is in the first state ("H") for a period substantially the same as the edge period of the Y signal input A. When the signal K is in the first state (“H”), the switch 26 is turned on and the adder 14 is turned on.
However, the output signal of the delay line 2 and the contour emphasis signal are added. When the signal K is in the second state (“L”) (that is, when the Y signal input A is not in the edge period), the switch 26 is in the off state.

FIG. 2 shows the signal waveform of each part of the embodiment of FIG. 1, and FIG. 3 shows the waveforms of the two input signals of the adder 14 of the embodiment of FIG. 1 and the contour correction obtained from the adder 14. The waveform of the Y signal output is shown. The operation of the embodiment shown in FIG. 1 will be described below with reference to these figures. In the contour emphasis signal generating means, the delay line 2 delays the Y signal input A for a predetermined time and outputs it, and the delay line 4 delays the output signal B of the delay line 2 for a predetermined time and outputs it. 6 is the delay line 2
Of the input signal A and the output signal B of the delay line 4, the subtractor 8 outputs the difference signal of the input signal B of the delay line 4 and the output signal C, and the adder 10 of the subtractor 6 and 8 Output signal D
And E are added, and the sharpness volume 12 adjusts the level of the output signal F of the adder 10, and the switch 2
Output to 6.

On the other hand, in the edge detection / correction circuit 20, the absolute value circuit 21 outputs the absolute value of the output signal D of the subtractor 6, and the binarization circuit 22 outputs the output signal G of the absolute value circuit 21 as a threshold value. A signal in the first state (“H”) is output when the level is above the level, and a signal in the second state (“L”) is output when the output signal G of the absolute value circuit 21 is less than the threshold level. Further, the absolute value circuit 23 outputs the absolute value of the output signal E of the subtractor 8, and the binarization circuit 24 outputs the first state (“H” when the output signal H of the absolute value circuit 23 is equal to or higher than the threshold level. )), The second state (“L”) signal is output when the output signal H of the absolute value circuit 23 is less than a predetermined level.

The AND gate 25 finds the logical product of the output signals of the binarization circuits 22 and 24. The switch 26 is controlled by the output of the AND gate 25, and when the switch 26 is in the ON state, that is, when the Y signal input A is in the edge period, the adder 14 causes the output signal of the delay line 2 and the contour emphasis signal. And are added and output.

FIG. 4 shows the contour correction according to the embodiment of FIG.
It is shown in comparison with the contour correction by the conventional circuit of FIG. Figure 4
As shown in FIG. 1, according to the embodiment of FIG. 1, the dv / dt of the edge portion is corrected to almost the same level as the conventional one, and the width of the overshoot becomes narrower than the conventional one.

In the embodiment shown in FIG. 1, when a pulse (see FIG. 5A) whose rising and falling edges are close to each other, that is, whose edges are close to each other as shown in FIG. Unnatural contour enhancement as shown may occur. This is as shown in the edge detection signal K of FIG.
The input pulse waveform of (a) is determined to be a rising waveform + falling waveform and is generated in order to correct each of them, that is, to emphasize the contour.

The embodiment shown in FIG. 6 avoids the unnatural contour enhancement as shown in FIG. 5C and is close to a certain extent to realize a more natural contour enhancement of the pulse waveform.
One edge is judged as a series of edges.

In the embodiment of FIG. 6, the contour emphasizing signal generating means (1) delays the signal A'by delaying it by a predetermined time and outputs it, as in the embodiment of FIG. 1, and (2) delay line. A delay line 4 for delaying the output signal B ′ of 2 by a predetermined time and outputting
(3) A subtracter 6 that outputs a difference signal D ′ between the input signal A ′ and the output signal B ′ of the delay line 2, and (4) a difference signal between the input signal B ′ and the output signal C ′ of the delay line 4. Adjusts the level of the subtractor 8 that outputs E ′, (5) the adder 14 that adds the output signals D ′ and E ′ of the subtracters 6 and 8, and (6) the output signal F ′ of the adder 10. And a sharpness volume 12 for outputting a contour enhancement signal.

Edge detection / correction means 20C of the embodiment shown in FIG.
Is different from the edge detection circuit 20 of the embodiment of FIG. That is, the edge detection / correction circuit 20C is (a) Y
Delay line 2C for delaying signal input A by a predetermined time and outputting it
And (b) a delay line 4C that delays the output signal B of the delay line 2C for a predetermined time and outputs the delayed signal, and (c) a subtractor 6C that outputs a difference signal D between the input signal A and the output signal B of the delay line 2C. When,
(D) a subtracter 8C that outputs a difference signal E between the input signal B and the output signal C of the delay line 4C, (e) an absolute value circuit 21C that outputs the absolute value of the output signal D of the subtractor 6C, and ( f) The signal of the first state (“H”) is output when the output signal of the absolute value circuit 21C is equal to or higher than the threshold level, and the second state (“L” is output when the output signal of the absolute value circuit 21 is less than the threshold level. )), A binarization circuit 22C that outputs the signal, and (g) an absolute value circuit 23C that outputs the absolute value of the output signal E of the subtractor 8,
(H) When the output signal of the absolute value circuit 23C is equal to or higher than the threshold level, the signal in the first state ("H") is output, and when the output signal of the absolute value circuit 23C is less than the predetermined level, the second state (" L ") signal for outputting a binarization circuit 24C,
(I) An AND gate 25C for obtaining the logical product of the output signals I and J of the binarization circuits 22C and 24C, and (j) A
A predetermined number of serially connected minute delay lines D that receive the output signal of the ND gate 25C and (k) the first half of the predetermined number of minute delay lines D (lines K _-n and K _{-n in} FIG. 6). _{+ 1} 、 K _{-n + 2} ...
..K ₀ ) OR gate 27 for obtaining the logical sum of output signals
And (l) obtain the logical sum of the output signals of the latter half of the predetermined number of minute delay lines D (lines K ₀ , K ₁ , K ₂ ... K _n-1 , K _{n in} FIG. 6). OR gate 28 and (m) OR gate 2
AND gate 29 for obtaining the logical product of the output signals K ′ and K ″ of 7 and 28, and when the output signal K ″ ′ of the AND gate 29 is “H”, the switch 26 is turned on, It enables the adder 14 to add the output signal B ′ of the delay line 2 and the contour emphasis signal which is the output signal of the sharpness volume 12. The delay compensation circuit 5 provided between the output of the delay line 2C and the input of the delay line 2 is
It is provided to match the delay time of the edge detection / correction circuit 20C with the delay time of the contour emphasis signal.

FIG. 7, FIG. 8 and FIG. 9 show signal waveforms of respective parts of the embodiment of FIG. 6, and FIG. 10 shows the signal waveforms of the embodiment of FIG.
FIG. 11 shows that the unnatural enhancement as in the embodiment of FIG. 1 is not made, and FIG. 11 shows the edge detection signal K ″ ′ obtained in the embodiment of FIG. The operation of the embodiment shown in FIG. 6 will be described below with reference to these figures.

In the contour emphasizing signal generating portion of the embodiment of FIG. 6, the delay line 2 delays the input signal A'by a predetermined time and outputs it, and the delay line 4 outputs the output signal B'of the delay line 2 by a predetermined time. The signals are delayed and output, the subtractor 6 outputs a difference signal D ′ between the input signal A ′ of the delay line 2 and the output signal B ′, and the subtractor 8 outputs the difference signal D ′ of the delay line 4 and the input signal B ′. The difference signal E ′ from the signal C ′ is output, and the adder 10 adds the output signals D ′ and E ′ of the subtracters 6 and 8. The output signal F ′ of the adder 10 is level-adjusted by the sharpness volume 12 and supplied to the switch 26.

In the edge detection / correction circuit 20C, the delay line 2C delays and outputs the Y signal input A by a predetermined time, and the delay line 4C delays and outputs the output signal B of the delay line 2C by a predetermined time. The subtractor 6C outputs the difference signal D between the input signal A and the output signal B of the delay line 2C, and the subtractor 8C
Is a difference signal E between the input signal B and the output signal C of the delay line 4C.
And the absolute value circuit 21C outputs the absolute value of the output signal D of the subtractor 6C, and the binarization circuit 22C outputs the first state (" H ”) is output, and the signal in the second state (“ L ”) is output when the output signal of the absolute value circuit 21 is less than the threshold level. Further, the absolute value circuit 23C outputs the absolute value of the output signal E of the subtractor 8, and the binarization circuit 24C outputs the first state (“H”) when the output signal of the absolute value circuit 23C is equal to or higher than the threshold level. ) Is output, and the signal in the second state (“L”) is output when the output signal of the absolute value circuit 23C is less than the predetermined level.

The AND gate 25C is a binarization circuit 22C.
AND the output signals of 24C are obtained, and a predetermined number of minute delay lines D connected in series delay the output signal of the AND gate 25C, and the OR gate 27 causes the first half of the predetermined number of minute delay lines D to be delayed. The OR gate 28 obtains the logical sum of the output signals of the portions, the OR gate 28 obtains the logical sum of the output signals of the latter half of the predetermined number of minute delay lines D, and the AND gate 29 outputs the output signals K ′ of the OR gates 27 and 28. And K ″ are ANDed. Then, the output signal K ′ ″ of the AND gate 29
The switch 26 is controlled by. When the output signal K ′ ″ of the AND gate 29 is “H”, the switch 26 is turned on, and when the output signal K ′ ″ of the AND gate 29 is “L”, the switch 26 is turned off. When the switch 26 is on, the adder 14 adds the output signal B ′ of the delay line 2 and the contour emphasis signal L ′ output from the switch 26, and outputs the contour-corrected Y signal M ′. ..

The output signal K'of the OR gate 27 is a signal indicating whether or not an edge has occurred in a portion delayed with respect to the pulse center with respect to the pulse center. Further, the output signal K ″ of the OR gate 28 becomes a signal indicating whether or not an edge has occurred in a portion which is temporally advanced with respect to the center of the pulse. The output signal K ′ of the OR gate 27.
AND which is the logical product of the output signal K ″ of the OR gate 28 and
As shown in FIG. 11, the output signal of the D gate 29, that is, the edge detection signal K ′ ″, changes from t0 to t.
There is a part of "H" between 1 (edge detected),
Further, when there is a portion of "H" between t0 and t2 (edge is detected), even if the period of t0 is "L" (even if no edge is detected), the period of t0 is " H ”(determine that the edge continues). Therefore, the two edges that are close to each other are determined to be a series of edges, so that unnatural emphasis is not applied to signals whose edges are close to each other. (See Figure 10).

[0029]

According to the contour correction circuit of the first aspect, the edge period of the input signal is detected, and the input signal and the contour emphasis signal are added only during this period. Is large (dv / d of relatively low frequency components
Since it is possible to enhance the contour with a small overshoot, it is possible to improve the image quality (a crisp feeling and an image quality without glare can be obtained).

According to the contour correction circuit of the second aspect, the first means for outputting the difference signal between the input signal and the output signal of the first delay means for outputting the input signal after delaying the input signal by the edge detecting means. A first state signal is output when the output signal of the subtracting means is equal to or higher than a predetermined level, and a second state signal is output when the output signal of the first subtracting means is less than the predetermined level.
When the output signal of the detection means and the second subtraction means for outputting the difference signal between the input signal and the output signal of the second delay means for delaying and outputting the output signal of the first delay means for a predetermined time or more Second detecting means for outputting a signal in the first state and outputting a signal in the second state when the output signal for the second subtracting means is below a predetermined level; the output signal for the first detecting means;
Since it is configured by including the first logical product means for obtaining the logical product with the output signal of the detection means, it is possible to perform contour enhancement with a simple configuration, with a large edge inclination angle and a small overshoot.

According to the contour correction circuit of the third aspect, the means for detecting the edge is the third delay means for delaying the input signal by a predetermined time and outputting the delayed signal, and the output signal of the third delay means is delayed for the predetermined time. Outputting the difference signal between the input signal and the output signal of the third delay means, and outputting the difference signal between the input signal and the output signal of the fourth delay means. When the output signals of the fourth subtraction means and the third subtraction means are equal to or higher than a predetermined level, the signal of the first state is output,
Third detecting means for outputting a signal in the second state when the output signal of the subtracting means is less than the predetermined level; and outputting a signal in the first state when the output signal of the fourth subtracting means is more than the predetermined level, A fourth detecting means for outputting a signal in the second state when the output signal of the 4-subtracting means is less than a predetermined level, a logical product of the output signal of the third detecting means and the output signal of the fourth detecting means A first logic for obtaining a logical sum of two logical product means, a predetermined number of delay means connected in series with the output signal of the second logical product means as input, and the output signals of the first half of the predetermined number of delay means. Summing means, a second logical sum means for obtaining the logical sum of the output signals of the latter half of the predetermined number of delay means, and a third logical sum means for obtaining the logical product of the output signals of the first and second logical sum means. The two edges that are close to each other form a series of edges. Since the cross-sectional, never perform unnatural emphasis on signals edge close.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a contour correction circuit of the present invention.

FIG. 2 is a waveform diagram showing signal waveforms of various parts of the embodiment of FIG.

3 is a waveform diagram showing waveforms of two input signals of the adder 14 and a waveform of a contour-corrected Y signal output obtained from the adder 14 of the embodiment of FIG.

4 is a waveform diagram showing a waveform of a Y signal output whose contour has been corrected by the embodiment of FIG. 1 in comparison with a waveform of a Y signal output whose contour has been corrected by a conventional technique.

5 is a waveform diagram showing an example in which unnatural emphasis is made in the embodiment of FIG.

FIG. 6 is a block diagram showing the configuration of another embodiment of the contour correction circuit of the present invention.

FIG. 7 is a waveform diagram showing signal waveforms of various parts of the embodiment of FIG.

FIG. 8 is a waveform diagram showing signal waveforms of various parts of the embodiment of FIG.

FIG. 9 is a waveform diagram showing signal waveforms of various parts of the embodiment of FIG.

10 is a waveform chart showing that unnatural emphasis is not made in the embodiment of FIG. 6 as in the embodiment of FIG.

FIG. 11 is an explanatory diagram showing an edge detection signal obtained in the embodiment of FIG.

FIG. 12 is a block diagram showing an example of a video signal display device provided with a contour correction circuit.

FIG. 13 is a block diagram showing an example of a conventional contour correction circuit.

FIG. 14 is a waveform diagram showing signal waveforms of respective parts of the conventional contour correction circuit shown in FIG.

FIG. 15 is an explanatory diagram showing an input signal of the contour correction circuit and ideal correction.

[Explanation of symbols]

 2,2C, 4,4C delay line 5 delay time compensation circuit 6,6C, 8,8C subtractor 10,14 adder 12 sharpness volume 20,20C edge detection correction circuit 21,21C, 23,23C absolute value circuit 22, 22C, 24, 24C Binarization circuit 25, 25C AND gate 26 Switch 27, 28 OR gate 29 AND gate D Micro delay line

Claims (3)

[Claims] 1. A contour emphasis signal generation means for generating a contour emphasis signal from an input signal, a first addition means for adding the input signal and the contour emphasis signal, the contour emphasis signal generation means, and the first A contour comprising: a switching means arranged between the adding means and an edge detection / correction means for detecting an edge period of the input signal and turning on the switching means during this period. Correction circuit. 2. The contour emphasis signal generation means delays the input signal for a predetermined time and outputs it, and a second delay means outputs the output signal of the first delay means for a predetermined time and outputs it. A first subtracting means for outputting a difference signal between the input signal and the output signal of the first delay means, and a second subtracting means for outputting a difference signal between the input signal and the output signal of the second delay means, A second for adding the output signals of the first and second subtraction means
An addition unit, the edge detection and correction unit outputs a signal in a first state when the output signal of the first subtraction unit is equal to or higher than a predetermined level, and the output signal of the first subtraction unit is less than a predetermined level. When the output signal of the second subtraction means is equal to or higher than a predetermined level, the first detection means that outputs the signal of the second state when the output signal of the second subtraction means is output. A second detection means for outputting a signal in the second state when the output voltage is less than a predetermined level; and a first logical product means for obtaining a logical product of the output signal of the first detection means and the output signal of the second detection means. The switching means is controlled by the output of the first logical product means, and when the switching means is in an ON state,
2. The first adding means adds the output signal of the first delay means and the contour emphasis signal.
The described contour correction circuit. 3. The contour emphasis signal generation means delays the input signal for a predetermined time and outputs it, and second delay means outputs the output signal of the first delay means for a predetermined time and outputs it. A first subtracting means for outputting a difference signal between the input signal and the output signal of the first delay means, and a second subtracting means for outputting a difference signal between the input signal and the output signal of the second delay means, A second for adding the output signals of the first and second subtraction means
A third delay means for delaying the input signal by a predetermined time and outputting the delayed signal; and a fourth delay for delaying and outputting the output signal of the third delay means for a predetermined time. Means, third subtracting means for outputting a difference signal between the input signal and the output signal of the third delay means, and fourth subtracting means for outputting a difference signal between the input signal and the output signal of the fourth delay means. A third state signal is output when the output signal of the third subtracting means is above a predetermined level, and a second state signal is output when the output signal of the third subtracting means is below a predetermined level When the output signal of the detecting means and the fourth subtracting means is above a predetermined level, the signal in the first state is output, and when the output signal of the fourth subtracting means is below the predetermined level, the signal in the second state is output. Output of the fourth detecting means and the third detecting means A second logical product means for obtaining a logical product of a signal and an output signal of the fourth detection means; a predetermined number of serially connected delay means having an output signal of the second logical product means as an input; A first logical sum means for obtaining the logical sum of the output signals of the first half of the predetermined number of delay means; and a second logical sum means for obtaining the logical sum of the output signals of the latter half of the predetermined number of delay means, A third logical product means for obtaining a logical product of the output signals of the first and second logical sum means, and controlling the switching means by the output of the third logical product means, and when the switching means is in the ON state. To
2. The first adding means adds the output signal of the first delay means and the contour emphasis signal.
The described contour correction circuit.