JPS6052186A - Sigal rpocessing circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal processing circuit, and specifically to a circuit for emphasizing the rise time and fall time of a transition portion of a signal.

[Background]

When a signal is processed through a device with a limited bandwidth or slew rate, the rise and fall times of the signal's level-to-level transitions are correspondingly limited.

That is, the narrower the bandwidth, the smoother the transition.

In television (TV) devices, for example, the bandwidth of chrominance signals is limited by transmission standards. In the NTSC system, the chrominance component signal is 1
, 5 MHz, and the Q chrominance component signal has a bandwidth of 0.5 MHz. It is not uncommon for TV receivers to process both optical and Q chrominance component signals with a bandwidth of 0.5 MHz.

Although it would be desirable to further improve the rise and fall times for most image conditions, the rominance signal processing method described above is satisfactory. However, if the rise and fall times of the chrominance signal are limited, the edges of the subject become unclear. This results in a tendency for color fidelity to deteriorate. This undesirable effect on the image occurs when the subject has sharp edges that can be reproduced with a wide-bandwidth (4.2 MHz) luminance signal but not with a narrow-band chrominance signal, and Furthermore, this phenomenon is particularly noticeable when the color of the subject is significantly different from the background color.

Accordingly, there is a need for circuitry and detectors of such transitions that improve (eg, reduce) signal rise and fall times when certain transitions occur. If the high frequency components of the signal are highly attenuated due to the limited bandwidth of the signal, the effect of a normal peaking circuit that emphasizes the high frequency components of the signal relative to the low frequency components is ineffective. known to be limited.

[Summary of the invention]

Therefore, the signal processing circuit according to the present invention includes a plurality of delay means connected in cascade and sequentially delaying input signals;
The delay means includes means for detecting changes in the magnitude of the input signal, and selective coupling means for coupling the inputs of the delay means in accordance with the detection means.

[Detailed explanation]

In the following description, the signals will be explained as digital signals, but it goes without saying that the present invention can be applied to signals in various other formats, such as analog or digital sample data signals, and analog signals. stomach. In the drawings, wide arrows represent signal paths for multi-bit parallel digital signals, and line arrows represent signal paths for single-bit or serial digital signals or for analog signals.

FIG. 1 illustrates a signal transition enhancement circuit with a transition detector. This circuit is suitable for processing digital chrominance signals in television receivers equipped with digital signal processing circuits. This receiver produces a digital chrominance signal C8, which is further processed by an apparatus employing the invention into an enhanced digital chrominance signal C8'/.

In the following description, emphasis on rise and fall times corresponds to row values. That is, signal C8 now has the magnitude indicated by sample F, and this is equal to clock signal f
This means that sample C had the size indicated by sample A five cycles before.

Solid line 50 connects samples A-F to
It represents the period of 114 degrees of the transition expressed by .

Furthermore, this sample sequence is detected by the detector 10 as described above.
0 has a magnitude such that it generates a control signal MC that enables MUXs 20 and 22. MUX20 then provides the value of sample E instead of the value of sample D at the input of delay stage 140, and MUX22
gives the value of sample B in place of the value of sample C at the input of delay stage 16. These substitutions are indicated by arrow 5 in Figure 2a.
4 and 52, and the replacement sample values from samples E and B are designated D' and C', respectively. In the next occurring cycle of clock signal fSe, samples B1C', D', E, F are respectively applied to delay stage 18.
16.14.Latched to 12 and 10, detector 10
0 removes control signal MC. This is because the transition detection condition is no longer satisfied. clock signal fs
In response to further subsequent cycles of c, the signal C8' becomes a modified sample sequence A, B, C', D', E, F' (i.e. (columns of size A, B, BXESE, F). A dashed line 56 connects the samples in this modified sample sequence and represents the exaggerated rise time of the transition represented by this sequence.

As another example, the sample sequence of signal C8 illustrated in FIG. let's think. The above-described operations performed in connection with FIG. 2a result in the IVI U
and 22 respectively perform permutations 62 and 64 to produce a series of samples A, B, B, E, E, F of the fall time emphasized modified signal C8' illustrated by the dashed line 66.

Next, the displacement detector 100 and predetermined conditions for detecting the occurrence of displacement will be described. A waveform transition is an instantaneous change from one amplitude level to another and can be described by the difference between the levels and the time required for the level change. For example, in the case of a sample, the digital signal of which is an example, a shift can be described by the size of the sample or group of samples and the number of samples within the range over which the change in size occurs.

The detector 100 determines the thickness of the sample data signal as follows:
A transition is detected when the sizes of two groups of consecutive samples are relatively close to each other, and when there is a large difference in size between non-consecutive samples. Specifically, in the case of six consecutive sample sequences, (1
) first and second samples (first of consecutive samples
(2) the fifth and sixth samples (the second group of consecutive samples) when the sizes of the groups) are relatively close to each other;
when the sizes of are relatively close to each other, and (3)
A shift is detected when the magnitudes of the second and fifth samples (two non-consecutive samples) are significantly different from each other. This principle states that the first, second, fifth and sixth samples are not part of the transition, but that a substantial transition occurs between the two groups of samples (see Figure 2 a and b). stipulates.

The displacement detector 100 of FIG.
The subtracter 30 generates the absolute value of the difference in magnitude and supplies this to a comparator 32. Comparator 32 produces an output that provides a manual actuation level of AND gate 46 if the absolute value of this difference IE-Fl is less than the relatively small value REF-1.

Similarly, subtractor 34 generates the absolute value of the difference between successive samples A and B, and comparator 36 generates the absolute value of this difference IA
-A when Bl is smaller than a relatively small value REF-2
A movable level corresponding to the second human power of the ND gate 46 is applied. Further, the subtractor 40 generates the absolute value of the difference IB-El from the non-operating samples B and E, and if the absolute value is greater than the minimum value MIN, the comparator 42 generates the difference A N
The movable level that becomes the third human power of the D gate 46 is applied. Assuming that there is an active signal EN coincident in time with the above inputs to the A N D gate 46, a control signal MC is generated and MUXs 20 and 22 respectively transfer the value of sample E to the delay stage 14 as described above. The value of the sample B which was manually generated is applied to the input of the delay stage 16. The above principles regarding detection of transitions are summarized in Table 1 below.

Controller 48 generates an enable signal EN that enables or disables detector 100. The control device 48 is, for example,
If there is a change in the brightness signal YS, the movable signal E is changed accordingly.
This is a displacement detector that generates N.

Since the signals C8 and YS are component signals representing the same image, they have a temporal relationship. The control device 48 can also be omitted.

-1°'"'- The element 47 is a Sulhals generator or a digital one-shot generator responsive to the AND gate 46 and the clock signal fsc, and is, for example, a one-sample period wide pulse MO.
is generated, and then the subsequent parnu is not output for, for example, two sample periods. One-shot generator 47 eliminates the continuous recirculation of samples within the loop containing multiplexer 22 and delay stage 16, which may occur if transition sensing functionality is included in the transition enhancement circuit. It is something to prevent. However, it is also not necessary to provide the one-shot generator 47 if separate but parallel delay stages are used for the shift detector and enhancement circuit.

The displacement detector 200 shown in FIG. 3 is a modification of the detector 100 in which another sensing principle also needs to be satisfied in order to generate the control signal MC. This additional sensing principle is
It is only emphasized when the transition is relatively smooth and uniform, so that useful relatively high frequency sample information is not lost.

The above effect means that the difference in the magnitude of the transition between the second and fifth samples does not exceed the maximum value that the magnitude of the third and fourth samples becomes, respectively. This can be achieved by an additive detection principle that requires the magnitude of the average value to be intermediate between the magnitude of the second and fifth samples.

Detector 200 includes subtractors 30.34 and 4o and comparators 32.36 and 42, which correspond to the same numbered elements in detector 100 described above. Referring to FIGS. 2 and 3, the comparator 44
applies a moving level to the AND gate 46' when the absolute value IB-El of the difference produced by the subtractor 40 is less than the maximum value MAX which is greater than the minimum value M I N . The subtractor 40 is also used to represent whether the transition is positive or negative and to simplify the construction of a comparator for checking whether the additive detection principle is met. , sign bit SB is also generated.

The check for compliance with the principles of smoothness and uniformity of transitions is carried out by comparators 70, 74, 84 and 88 in the following manner. Comparator 70 detects sample B
and C, and the result obtained is selectively inverted by controllable inverter block 72 depending on the sign bit SB. Then, when the principles B and C are satisfied in the case of a positive displacement, and when the principles B) and C are satisfied in the case of a negative displacement, the single-man power of the AND gate 46' is activated. . Similarly, the comparator 74 and the controllable inverter block 76 operate according to principle D on positive transitions (when E is satisfied, and principle D on negative transitions).
is satisfied, one input of AND gate 46' is enabled. By this, sample C,! : The size of D is intermediate between the sizes of samples B and E to give a first indication of uniformity.

Adder circuit 80 and divide-by-2 circuit 82 generate an average of the magnitudes of samples B and E. This average value is indicated by the dashed line at level l/2 (B 1 E ) in FIGS. 2a and b. For sampled analog signals, circuits 80 and 82
is a resistive circuit, and for digital signals, circuit 80
is an adder, and the circuit 82 is connected according to the following formula: /F' rule C< /
2 (B + E) y5"Xj foot support rc toki, and C>"/2 (B + E
) is satisfied, the input of AND gate 46' is enabled. Similarly, the comparator 88 and the controllable inverter block 90 operate in the case of positive transitions in principle D〉l/
The input of the AND gate 46' is enabled when 2(B+E) is satisfied and when the principle D<1(B+E) is satisfied for negative transitions. This ensures that the magnitude of sample C is intermediate between the average level of B and E and the magnitude of sample B, and that the magnitude of sample D is intermediate between said average level and the magnitude of sample E; Furthermore, the uniformity of the transition is displayed.

AND gate 46' generates control signal IVIC in response to the temporal coincidence of the signals at all of its inputs. These detection principles can be summarized in Table IIO.

Table: For an 8-bit digital chrominance signal with values ranging from 0 to 255 in decimal value, the following nominal comparison levels are appropriate: That is, REF-1=8, REV-
2=8, MIN=48, MAX=255° The other portions of FIG. 3 show a control circuit 48 constituting a luminance signal change detection device. The luminance signal YS is sent to the delay stage 31
0.312.314.316 and 318 sequentially and are provided to the displacement detector 300. Detector 3
00, for example, the control signal from there is the movable signal EN.
The structure is similar to that of the detector 100 or 200 described above, except that the voltage is applied to the A and ND gates I and 46'. The delay stage 310-3tg is a delay stage 310-3tg of the -'i
I (may exist together with

FIGS. 4 and 5 show advantageous embodiments that can replace the comparators 32, 36, 42 or 44 in FIGS. 1 and 2. These embodiments are used when the digital samples are represented in sign-magnitude format. The inverting input AND gate 32' of FIG.
(but not the sign bit) are all 1011, a movable level is applied to the AND gate) 464 or 46'.

NOR game) 32"' (FIG. 5) is the selected number of high order bits of the absolute value of the difference produced by the subtractor 3o, in response to the fact that the MSBs are all II OII,
A movable level is applied to AND gate 46 or 46'.

The level of the reference level REF-1 supplied by the gate 32' or 32'' is given by [2N-1], where N is the lower bit L not connected to the gate.
sB, the above relationship is shown in Table m.

Table m FIG. 6 shows an embodiment that may be used in place of comparator 42 of FIG. 2, for example, if the digital samples are represented in sign-magnitude format.

OR gate 42' applies a movable level to AND gate 46-1:46' in response to any one of the MSBs of the absolute value of the difference produced by subtractor 40 being IILII. For the standard MIN level, OR N)
When the number of LSHs not connected to 42' is [2N-
1) is given.

Various modifications can be made within the scope of the invention as set forth in the claims. For example, subtracter 80, divider circuit 82, comparator 88 and inverter block 90 of FIG. 3 can be omitted and samples C and D can be applied directly to comparator 84.

This allows an indication of uniformity when principle C(D is satisfied for positive displacements and when principle C>D is satisfied for negative displacements.

Furthermore, the configurations of the comparators in FIGS. 4, 5, and 6 are as follows:
Exclude SB from the comparison operation! So,
It is shown that the absolute value of the difference magnitude can be obtained for digital numbers in sign-magnitude format. .

the number of delay stages 10.12.14... used, the sequentially delayed samples of the repetition frequency signal C8 of the clock signal fsc that are applied to the detectors 100 and 200, and the MUX 20 in the cascade delay stages. 22, etc. all affect the limits of rise and fall detection and the degree to which rise and fall times are emphasized. For example, a rate of four times the color subcarrier number (i.e., NTS
In the C method, a large number of delay stages are required to emphasize the transition of the luminance signal samples generated at 4 fsc =14.32 MHz). Furthermore, the number of samples in those groups can be more or less than the two samples mentioned above (A, B and E, F), and the number of tuples between those seven groups can also be more or less than the two samples mentioned above (C, D) Can be done more or less.

Transitions faster than those illustrated in FIGS. 2a and b can be emphasized as long as there is at least one signal sample during the transition. That is, as long as the two samples being compared to detect a transition are not one after the other. For example, the circuit in Figure 1 is
Signal sample E in Figure 2! : C is compared by a subtractor 40 and a comparator 42 to detect a transition, the delay stages 12 and 14 and the multiplexer 20 being the main components, and the permutation 54 of FIG. 2 a and b. It is also possible that only 64 is performed. Therefore, in this case, MUX 22 is omitted and delay stage J4 is directly connected to delay stage 16.

Although the emphasis on transitions described herein has been with respect to reducing the rise and fall times of transitions, the invention can also be usefully used to increase rise and fall times. In the case of such a modification, 1viUX
20 before delay stage 12 to receive signal samples E and D at its inputs, MUX 22 before delay stage 18 to receive signal samples C and B at its inputs, and delay stage 12 to delay stage 14. and coupling delay stage 14 to delay stage 16. Thus, detector 100 generates a control signal MC to cause samples C and E to be used in place of samples B and D, respectively.

As a further example, the controllable inverter block 72.7
6.86 and 90 are omitted, and each comparator 70.74.
A multiplexer can also be added to invert the inputs to 84 and 88. Furthermore, at appropriate locations within the displacement detectors 100 and 200, the two shown in FIG.
By inserting a converter such as a complement-to-binary converter, digital number systems other than those mentioned above can also be processed with the circuit of the invention.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a device having a circuit according to an embodiment of the present invention, FIGS. 2a and b are diagrams illustrating the form of signals in the device of FIG. 1, and FIGS. 3 to 7 These are 41-4 diagrams each showing a modified or substituted embodiment of a part of the apparatus shown in FIG. 1. C8...Input, C8'...Output, 10.12.14
．． 16 and 18...delay means, respectively, 20.22
... multiplexer (means for coupling one input of the delay means to another input), 30.34.40 ... subtractor,
32.36.42... Comparator, 46... AND gate, 48... Control device, 100... Detection means (displacement detector), A, B, C, D, E, F... - Each position in the sample loop or signal path of signal C8. Special Wf Applicant: RCSNY Corporation Agent: Tetsu Shimizu and 2 others

Claims (1)

[Claims] (1) an input that receives an input signal, an output that generates an output signal in response to the input signal, and a plurality of delay means that are cascade-coupled between these inputs and the output and sequentially delay the input signal; a detection means coupled to the plurality of delay means for detecting a change in the magnitude of the input signal according to the sequentially delayed input signals; and means for selectively coupling one input of said delay means to another input of said delay means in response to detecting a transition in accuracy.