FI76901C - Signal processing circuit. - Google Patents

Description

1 76901

This invention relates to a signal processing circuit according to the preamble of claim 1.

5 When signals are processed in systems with limited bandwidth or tracking speed, the rise and fall times of changes between signal levels are limited accordingly. That is, lower bandwidth causes gentler changes. For example, in a television system (TV), the bandwidth of color 10 signals is limited by a transmission system standard. In the NTSC system, the I chrominance component signal has a bandwidth of 1.5 megahertz (MHz) and the Q chrominance component signal has a bandwidth of 0.5 MHz. Often, the TV receiver circuit processes both I and Q chrominance component components at a bandwidth of 0.5 MHz.

For most image conditions, the chrominance signal processing described above is satisfactory, although it is desirable that the rise and fall times be improved. However, the limited rise and fall times of the chrominance signal tend to blur the edges of the object and suffer from poor color reproduction accuracy. These detrimental image effects occur especially when the subject has a well-defined limit that the high bandwidth of the luminance signal (4.2 MHz) is able to provide, but the lower bandwidth of the chrominance signals 25 is unable, and also when the color of the subject differs significantly from that of the background.

Thus, there is a need for a circuit that improves (i.e., reduces) the rise and fall times of a signal when certain changes occur, and a need for detectors for such changes. It has been found that conventional enhancement circuits which emphasize the higher frequency components of a signal compared to the lower frequency components have a limited effect when the higher frequency components are strongly attenuated due to the limited bandwidth of the signal.

In order to overcome this drawback, the signal processing circuit according to the invention is mainly characterized by the features set out in the characterizing part of claim 2 76901.

Thus, the signal processing circuit of the present invention comprises: a plurality of cascaded delay devices that sequentially delay input signals; a device si-5 for detecting changes in the magnitude of the weather input signals; and selectively connecting devices between the inputs of the delay devices in response to the detector. In the drawing: Fig. 1 is a diagram in block diagrammatic form 10 of an apparatus including an embodiment of the present invention; Figures 2a and 2b are diagrams showing the signals in the device of Figure 1; and Figures 3-7 are block diagrams of modifications and alternative embodiments of parts of the device of Figure 1.

15 Although in the following description the signals are treated as digital signals, it is to be understood that the present invention has been adequately implemented with a number of different types of signals, for example, both analog and digital type mixed data signals. In the drawings, the wide arrows represent the signal paths of multi-bit, parallel digital signals, while the line arrows represent the signal paths of single-bit or serial digital signals, or analog signals.

Figure 1 shows a signal change enhancement circuit including a change detector. The circuit is used to process digital chrominance signals in a TV with a digital signal processing circuit. The receiver provides digital chrominance signals CS, which are further processed by a device using the present invention, to provide enhanced digital chrominance signals CS '.

In the following description, the operation of the delay stages 10, 12, 14, 16 and 18 and the MUX 20 and 22 to implement the rise and fall time will be described first. The operation of the change detector 100 is then described.

35 Assume first that the multiplexers (MUX) 20 and 22 combine the signals at locations D and C with their respective outputs, the input signals CS are sufficiently delayed by cascaded delay stages 10, 12, 14, 16 and 18 so that the output signals CS1, are simply time-delayed input signals CS.

Each of the delay stages 10, 12, 14, 16 and 18 is, for example, an 8-bit parallel latch which responds to the clock signal f The clock signal f has a repetition frequency which is proportional to the frequency of the color carrier, i. about 3.58 MHz in an NTSC TV system. Thus, CS 'is time-delayed from CS by five periods of the clock signal f.

When changes in signals CS occur that meet a certain preset magnitude and rise or fall condition, the change detector 100 generates and supplies a control signal to the MC MUXs 20 and 22 such that the MUXs 20 and 22 selectively combine the inputs of the delay stages. inputs of other delay stages. Specifically, the MUX 20 connects the input of the delay stage 12 to the input of the delay stage 14 and separates the output of the delay stage 12 from this. Similarly, the MUX 22 connects the delay stage 18 to the input of the delay stage 16 and separates the output of the delay stage 14 from the output 20.

Consider, for example, the change in the time sequence of samples A, B, C, D, E, F of the signal CS shown in Fig. 2a from a lower magnitude to a higher magnitude (change in the positive direction). (Note that in the case of either analog or digital sample queue systems, the signal takes care of the value for the entire period. The straight line between samples is for illustrative purposes only in this type of system). The time interval shown by Fig. 2a is the time during which the time sequence of the CS samples is synchronized through the delay stages 10, 12, 14, 16 and 18. Thus, the samples labeled with the sample identifiers in Fig. 2a correspond to the values of the samples with the signal paths corresponding to the signal paths in Fig. 1. That is, the signal CS is currently magnified by sample F and was magnified by sample A wool five cycles earlier than the clock signal f.

SO

4,76901

The solid line 50 connects samples A-F, thus illustrating the rise time of the change represented by samples A-F.

Note further that this time this sequence of samples has such magnitudes that the detector 100 generates a control signal MC activating MUXs 20 and 22 as described above. Then MUX replaces the value of sample E with sample D at the input of delay stage 14 and MUX 22 replaces the value of sample B with the value of sample C with the input of delay stage 16. These exchanges are indicated by arrows 54 and 52, respectively, and the exchanged sample values from samples E and B are denoted D 'and C, respectively, in Figure 2a. In the next period of the clock signal f, the samples B, C ', D1, E, F are connected to delays 18, 16, 14, 12 and 10, respectively, and the detector 100 removes the control signal MC, 15 because the change detection condition is no longer valid. In response to subsequent periods of f, the signal CS 'shall be

Sv to this the transformation sequence of samples A, B, C, D ', E, F (i.e. the magnitudes A, B, B, E, E, F in succession) with a change with an improved (reduced) rise time.

Dashed line 56 connects the samples in the change sequence, thus illustrating the improved rise time of the transform shown therein.

Using the following example, note the sequence of the CS samples in the signal CS shown in Figure 2b to change from a larger magnitude to a smaller magnitude (negative direction change), shown by line 60. According to the operation of Figure 2a above, exchanges 62 and 64 are performed with MUXs 20 and 22, respectively. in response to the control signal MC so as to provide a conversion sequence A, B, B, E, E, F of the signal CS '

representing the improved descent time illustrated by dashed line 66.

The transform indicator 100 and the preset condition under which the occurrence of the change is detected will now be described. The change in waveform is a change in instantaneous amplitude from one amplitude level to another, and can be described as the difference between levels and the time required to change the level. For a sample sequence of which digital signals are an example, the change can be described in terms of the magnitudes of the samples or groups of samples and the number of samples during which the change in magnitude occurs.

Detector 100 detects a change when the magnitudes of the sample sequence signal are relatively close in magnitude to each successive incremental sample of the two groups and when the difference in magnitudes between non-consecutive samples is significant. More specifically, in the sequence of six consecutive incremental samples, a change is observed when 1) the first and second samples (first group of consecutive samples) are relatively close in magnitude, 2) the fifth and sixth samples (second group of consecutive samples) are relatively close in magnitude, and 3) when the magnitudes of the second and fifth samples (two non-consecutive samples) differ significantly. These features indicate that the first, second, fifth, and sixth samples are not part of the change, and that a significant change occurs between the two groups of samples, as illustrated in Figures 2a and 2b.

The change detector 100 of Figure 1 includes a subtractor 30 that provides the absolute value of the difference between the magnitudes E and F of successive samples 25, which is applied to a comparator 32. The comparator 32 provides an output to input an AND gate 46 to a second input when the absolute value of the difference EF is less than relative. low value REF-1. Similarly, subtractor 34 provides an absolute value of the difference between successive samples A and B, and comparator 36 provides an enabling level to the second input of gate 46 when the difference A-B is less than the relatively small value REF-2. In addition, the subtractor 40 generates the absolute value B-E of the difference 35 from the non-consecutive samples B and E, which, if greater than the actual minimum value MIN, causes the comparator 42 to input this enabling level AND gate 46 to the third input. Assuming that an enabling signal EN exists, concurrency at the inputs of AND gate 46 causes the control signal MC to cause MUXs 20 and 22 5, respectively, to input the value of sample E to the input of delay stage 14 and the value of sample B to input of delay stage 16, as described above. These characteristics to indicate the change are summarized in Table I,

10 Table I

Well. Elements Test Criteria with AND Gate 46 15 1. 30, 32 | E-F | <REF-1 2. 34, 36 | A-B | <REF-2

3. 40, 42 | B-E | > MIN

4. 48 EN = 1 20

The control device 48 generates an enabling signal EN which enables and disables the reception of the input signals of the detector 100. For example, the control device 48 is a change detector, which generates an enabling signal EN in response to changes in the luminance signals YS. The signals CS and YS are temporally related because they are component signals representing the same image. The control device 48 can be omitted.

Element 47 is a pulse generator or digital one-shot element responsive to port 46 and a clock signal f is used to generate a pulse MC, e.g., the width of one sample period, and cannot produce the next pulse for e.g., two sample periods. The one-shot element 47 makes it impossible to continuously recycle samples in a loop-35 compartment that includes a multiplexer 22 and a delay stage, which can occur when the change detection circuit is associated with the change highlight circuit. Alternatively, if the change detector and highlight circuit use separate but parallel delay stages, a one-shot element is unnecessary.

The change detector 200 shown in Fig. 3 is a modification of the detector 5, where the criteria for additional detection must be met to provide a control signal MC. The criteria for additional expression ensure that the change is highlighted only if it is a relatively uniformly changing and monotonic change, thus avoiding the loss of valuable relatively high-frequency sample information.

This is achieved by the additional expression criteria so that the difference in magnitude of the change between the second and fifth samples does not exceed the maximum value and that the magnitudes of the third and fourth samples are between the mean magnitudes of the second and fifth samples and the second and fifth samples, respectively.

Detector 200 includes subtractors 30, 34 and 40 and comparators 32, 36 and 42 corresponding to similarly numbered elements of detector 100 described above.

Referring to both Figure 2 and Figure 3, the comparator 44 feeds the enabling level AND gate 46 to one input when the absolute value of the difference generated by the subtractor 40 is less than the maximum value MAX, which in itself is greater than the minimum value MIN. The subtractor 40 also generates an identification bit SB, which indicates whether the change is positive or negative, and which is used to simplify the structure of the comparator to test the criteria of the additional detector.

Criteria indicating uniform variability and monotonicity of change are tested on comparators 70, 74, 84, and 88 as follows. The comparator 70 compares samples B and C, as a result of which the comparison is selectively inverted by a controllable inverter block 72 in response to the flag bit SB. Thus, one input-35 of the AND gate 46 'is made possible when the criterion B <C is valid for positive changes and when the criterion B> C is valid for negative changes. Similarly, the comparator 74 and the controllable inverter block 76 allow a single input of the AND gate 46 'when the criterion D <E is valid for positive-direction changes and when the criterion D> E is valid for negative-direction changes. This ensures that the magnitudes of samples C and D are between those of samples B and E, respectively, providing a first indication of monotonicity.

The adder circuit 80 and the dichotomy circuit 82 generate an average of the magnitudes of samples B and E, which is indicated by dashed lines at level 1/2 (B + E) in Figures 2a and 2b. For analog sample sequence signals, circuits 80 and 82 are resistive circuits; for digital-15 signals, circuit 80 is an adder and circuit 82 is a bit shifter implemented with wired connections. The comparator 84 and the controllable inverter block 86 allow the input of the AND gate 46 'when the criterion C <1/2 (B + E) is valid for positive parallel changes and when C> 1/2 (B + E) is valid for negative changes. Similarly, the comparator 88 and the controllable inverter block 90 allow the input of the AND gate 46 'when the criterion D> 1/2 (B + E) is valid for positive changes and when D <1/2 (B + E) is valid for negative changes. This ensures that the magnitude of sample C is between the mean of B and E and the Raag of the sample B, and that the magnitude of sample D is between the mean of the magnitude and the magnitude of sample E, thus providing an additional indication of mono-novelty.

The AND gate 46 'generates a control signal MC in response to the simultaneity of all its input signals. These criteria for expression are summarized in Table II.

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Table II

Text Criteria with AND Gate 46 * Positive Negative 5-way parallel

No Elements changes_ changes 1. 30, 32 | E-F | <REF-1 IE-F | <REF-1 10 2. 34, 36 | A-B | <REF-2 | A-B | <REF-2

3. 40, 42 | B-E | > MIN | B-E | > MIN

4. 40, 44 | B-E | <MAX | B-E | <MAX

5. 70, 72 B <C B> C

6. 74, 76 D <E D> E

15 7. 80, 82, 84, 86 C <H (E + B) C> H (B + E) 8. 80, 82, 88, 90 D> H (E + B) D <MB + E) 9 48 EN = 1 EN = 1 20 An eight-bit digital chrominance signal with values corresponding to decimal values from zero to 255, the following nominal reference levels are sufficient: REF-1 = 8, REF-2 = 8, MIN = 48, MAX = 255 .

The remainder of Figure 3 shows a control circuit 25 48 comprising a luminance signal change aeronautical system. The luminance signals YS are sequentially delayed by delay stages 310, 312, 314, 316 and 318 and applied to the change detector 300. For example, the detector 300 is similar in structure to either of the detectors 100 or 30,200, as described above except that the control signal is applied to the AND gate 46 '. as an EN signal. The delay stages 310-318 may be a delay line that is part of the FIR or a link filter in the luminance processing circuit.

Figures 4 and 5 show useful embodiments to replace, for example, the comparators 32, 36, 42 or 44 of Figures 1 and 2. These embodiments can be used when displaying digital samples in a token-magnitude format. The AND gate 32 'of the inverted input of Figure 4 responds to a selected number of the most significant bits (MSBs) (but not the ID bit) of the difference caused by the subtractor 30, all being' 0 'to supply the enabling level to the AND gate 46 or 46'. . The OR gate 32 ”of Figure 4 responds to a selected number of MSBs of the absolute value of the difference caused by the subtractor 30, all being '0' to supply 10 enabling levels to the AND gate 46 or 46 '.

Reference level REF-1 provided by port 32 'or 32 "

OF

the level is given in the form 2 -1, where N is the number of non-associated minor bits (LSBs) and is listed in Table III.

15 AND gate 32 'and NO gate 32 ”: Used MSBs Unused LSBs Value of REF-1 20 8 0 0 7 1 1 6 2 3 5 3 7 4 4 15 25 3 5 31 2 6 63 1 7 127 30

Fig. 6 shows a useful embodiment to replace, for example, the comparator 42 of Fig. 2 when digital samples are displayed in a characteristic magnitude format. The OR gate 42 'responds to the absolute value 35 of the difference caused by the subtractor 40 to any MSB that is' 1 'to supply an enabling level to the AND gate 46 or 46'. Reference level MIN

11 76901

OF

is given in the form 2 -1, where N is the number of LSBs connected to the non-OR gate 42 '.

Modifications are possible within the scope of this invention as set forth in the appended claims. For example, the subtractor 80, divider circuit 82, comparator 88, and inverter block 90 of Figure 2 may be omitted and samples C and D applied directly to comparator 84. This provides a monotonic indication when the criterion C <D is valid for positive changes 10, and when C > D is valid for negative changes. In addition, the comparator arrangements of Figures 4, 5, and 6 show that the absolute value of the difference magnitude is obtained for the digital numbers in the form of the characteristic magnitude by omitting the characteristic bit SB from the comparison.

15 The number of delay stages 10, 12, 14 ... used, the repetition frequency of the clock signal f, to the indicators 100 and

SO

The numbers of sequentially delayed samples of the input signals CS 200, and the location of the MUXs 20 and 22 in the cascade of the delay stages, all affect the detection limits of the rise and fall times and the degree to which the rise and fall times are highlighted. For example, a larger number of delay stages is required to emphasize changes in luminance signal samples produced at four times the color carrier frequency (i.e., 4 f for a 14.32 MHz NTSC system). In addition, the number of samples in their groups may be greater or less than the number of samples described herein (A, B, and E, F), and the number of samples between these groups may be greater or less than the number of samples described herein (C, D).

Changes that are faster than those shown in Figures 2a and 2b can be highlighted as long as there is at least one signal sample in the change. That is, as long as the two samples being compared to detect the change are not consecutive. For example, the circuit of FIG. 1 may be modified so that the signal samples E and C of FIG. 2 are compared by a track reducer 40 and a comparator 42 to detect a change # in which case delay stages 12 and 14 and multiplexer 20 are important elements and are performed only in Figures 2a and 2b. exchanges 54 and 64. Si-5 ten MUX 22 can be omitted and delay stages 14 connected directly to delay stage 16.

Since the emphasis on change described herein has been addressed to reduce the rise and fall times of changes, the present invention is also useful for increasing rise and fall times. In this variation, MUX 20 is placed before delay stage 12 and receives signal samples E and D at its inputs, MUX 22 is placed before delay stage 18 and receives signal samples C and B at its inputs, delay stage 12 is connected to delay stage 14 15 and delay stage 14 is connected to delay stage 16. Thus detector 100 causes the control signal MC to cause the replacement of sample C by sample B and the replacement of sample D by sample E.

Additional inverter-controllable blade blocks 72, 76, 86, and 90 may be omitted and multiplexers may be added to reverse the inputs to each of the comparators 70, 74, 84, and 88. Still other digital numbering systems may be processed within the scope of this invention by connecting converters such as 25 for example, the two complement binary transducers of Figure 7, at appropriate locations in the change detectors 100 and 200.

Claims (35)

A signal processing circuit, comprising: an input terminal for receiving input signals and an output terminal for providing output signals responsive to the input signals; a plurality of delay devices cascaded between the input terminal and the output terminal to sequentially delay the input signals, characterized by: detector devices (100) coupled to said plurality of delay devices and sequentially responding to the delayed input signals for large input signals; and a device (20; 22) coupled to said plurality of delay devices and a detector device for selectively connecting the input of one delay device (12; 18) to the input of another delay device (14; 16) in response to detecting a change in magnitude. A circuit according to claim 1, characterized in that said one delay device (12) is closer to the input terminal than said other delay device (14). A circuit according to claim 1, characterized in that said one delay device (18) 25 is closer to the output terminal than said other delay device (16). The circuit of claim 1, further characterized by a second device (22) coupled to the delay devices and the detector device for selectively connecting the input of the second delay device (18) to the input of the other second delay device (16) in response to detecting a change in magnitude. A circuit according to claim 4, characterized in that said one delay device (12) 35 is closer to the input terminal than said other delay device (14), and that said second delay device (18) is closer to the output terminal than said other delay device (14). device (16). The circuit of claim 1, characterized in that the detector device (100) includes a comparator device (42) for detecting a difference in magnitude between successively delayed input signals between non-consecutive (B, E) signals that exceeds a preset value (MIN). . A circuit according to claim 6, characterized in that the detector device (100) further comprises a second reference device (32; 36) for detecting a difference in magnitude between the successively delayed input signals of the others (E, F; A, B) which is less than another preset value (REF-1; REF-2). The circuit of claim 1, further characterized by a control device (48) that generates an activation signal (EN) and a device (46) for supplying an activation signal to the detector device (100) to enable detection of a change in magnitude. A circuit according to claim 8, characterized in that the control device (48) generates an activation signal in response to a change in the second input signal (YS) which is temporally proportional to the input signals received at the input terminal. Circuit according to Claim 9, characterized in that the input signals (CS) represent the chrominance components of the television signals and in that the second input signals (YS) represent their luminance components. A circuit according to claim 1, characterized by: a selective switching device (20; 22) comprising a multiplexing device (20) having a first input to which the output of the first delay device (12) is connected, having a second input, and the output is connected to the weather output of the second delay device (14), the multiplexer selectively switching its first and second inputs to its output in response to the control signal (MC); means (10) for inputting input signals 5 to the input of the first delay device and the second input of the multiplexer; a detector (100) for generating a control signal in response to a preset magnitude condition of the input signals and for supplying the control signals to the multiplexer. A circuit according to claim 11, characterized by: a third delay device (16) having an input and an output for delaying the signals input to the input thereof; a second channelization device (22) having a first input to which the output of the second delay device (14) is connected, having a second input to which the output of the third delay device is connected, and having an output 20 connected to the input of the third delay device, the channelization device selectively switching the first and second inputs output in response to a control signal (MC). A circuit according to claim 12, characterized in that the detector device (100) comprises a comparator device (40) having a first input to which either the input of the first (12), second (14) or third (16) delay device is connected having a second input to which the output of either the first, second or third delay device is connected and having an output for generating a control signal (MC) at its output in response to signals at its first and second inputs differing in a predetermined amount (MIN). 13 76901 A circuit according to claim 1, characterized in that: said plurality of delay devices (10, 12, 14, 16, 18) provide a plurality of signal samples (A, B, C, D, E, F) which are sequential in time and that the detector device (100) comprises a first detector device (30, 32) responsive to the first group of signal samples (E, F) for generating a first indication when the sample size in the first group differs by less than the first preset value 10 (REF -1), a second detecting device (40, 42) responsive to the two signal samples (B, E) for generating a second indication when the magnitudes of the two signal samples differ by more than a second preset value (MIN), and the indication generating device (46) -15 in response to the first and second indications. The circuit of claim 1, characterized in that: said plurality of delay devices (10, 12, 14, 16, 20 18) provide a plurality of signal samples (A, B, C, D, E, F) that are sequentially delayed in time; and that the detector device (200) comprises a first detector device (30, 32) responsive to the first group (E, F) of signal samples 25 for generating a first indication when the sample size in the first group differs by less than the first preset value (REF-1) , a second detector (34, 36) responsive to the second group of signal samples (A, B) for generating a second detection when the sample size in the second group differs by less than the second preset value (REF-2), the third detector (40) , 42) responsive to the two (B, E) signal samples for generating a third indication when the magnitudes of the two signal samples 35 differ by more than a third preset value (MIN), and the indication generating device (46 ') for detecting the indication (MC). in response to the first, second and third indications. A circuit according to claim 15, characterized in that the first detection device (30, 32) comprises: a connecting device (30) for generating an indication of the difference between the sizes of the two signal samples (E, F) of the first group; and a comparator (32) for generating a first indication when the difference indication is less than the first preset value (REF-1). Circuit according to Claim 16, characterized in that the signal samples (E, F) are digital signals and in that the connecting device (30) is a digital reducer. A circuit according to claim 17, characterized in that the comparison device (32) comprises an AND gate (32 ') for detecting the concurrence of the inverse value of the preset number of the most significant bits of the difference indication generated by the digital subtractor. A circuit according to claim 17, characterized in that the reference device (32) includes an NOT-OR gate (32 ") in response to a preset number of most significant bits generated by the digital subtractor. A circuit according to claim 15, characterized in that the third detection device (40, 42) comprises: a connecting device (40) for generating an indication of the difference between the sizes of the two signal samples 30 (B, E); and a comparator (42) for generating a third indication when the difference indication exceeds the third preset value (MIN). A circuit according to claim 20, characterized in that the signal samples are digital signals 76901 and the connecting device (40) is a digital reducer. A circuit according to claim 21, characterized in that the comparison device (42) comprises an OR gate (42 ') responsive to a preset number of bits of the most significant difference indication generated by the digital subtractor. A circuit according to claim 15, characterized in that the address generating device (46 ') comprises an AND gate (46') responsive to the simultaneity of the first, second and third assignments. to develop a recommendation (MC). A circuit according to claim 15, characterized in that the first group (E, F) contains at least two consecutive signal samples and the second group (A, B) contains at least two consecutive signal samples other than those included in the first group. A circuit according to claim 15, characterized in that the two signal samples comprise a first (B) and a second (E) non-consecutive signal sample. A circuit according to claim 25, characterized by a fifth detection device (70, 72, 74, 76) for generating a fifth indication when the magnitudes of the signal samples (C, D) between the first (B) 25 and the second (E) non-consecutive signal samples are between the second non-consecutive signal sample, and an indication generating device (46 '), which is further responsive to the fifth indication for generating the air recommendation 3. A circuit according to claim 25, characterized by at least two signal samples (C, D) between the first (B) and second (E) non-consecutive signal samples, and a fifth detection device for generating a fifth indication that the first (B) the sequence of the (7, 9) and the second (E) signal sample quantities in between is monotonic. A circuit according to claim 27, characterized in that the fifth detector device (80 82, 84, 86, 88, 90) comprises: 5 means (80, 82) for generating a magnitude value which is not equal to the first (B) and second (E) between the values of its signal sample; a first device (84, 86) for comparing the magnitude of one (C) of said intervening signal sample to said intervening magnitude value; a second device (88, 90) for comparing the magnitude of said second (D) intermittent signal sample to an intervening magnitude value, and that the Fifth Indication includes assignments generated by the first device and the second device. The circuit of claim 1, characterized in that: said plurality of delay devices (10, 12, 14, 16, 18) provide a plurality of signal samples (A, B, C, D, E, F) 20 that are sequentially delayed in time; and that the detector device (20) comprises a first detector device (30, 32) responsive to the first group (E, F) containing at least two consecutive signal samples for generating a first indication when the sample size in the first group differs by less than the first predetermined set value (REF-1), a second detector device (34, 36) responsive to the second group (A, B) of signal samples for generating a second indication when the sample size in the second group differs by less than the second preset value, the second the group comprising at least two consecutive signal samples other than those included in the first group, a third detector device (40, 42) responsive as a signal; for the first (B) and second (E) non-consecutive samples to generate a third indication 20 7 6 9 01 when the values of the first and second signal samples differ by more than the third preset value (MIN), whereby at least one of the signal samples (C, D) is between the first and second signal samples, a fourth detection device (80, 82, 84, 86, 88, 90) for generating a fourth indication that the sequence of said first intermediate and second signal sample quantities is monotonic, and an indication generating device (46 ') for generating an detection indication in response to the first-10, second, third, and fourth indications. A circuit according to claim 29, characterized in that the fourth detector device (80, 82, 84, 86, 88, 90) generates a fourth indication when the magnitudes of the signal samples (C, D) between the first and second non-consecutive signal samples are between the magnitudes of the first (B) and second (E) non-consecutive signal samples. A circuit according to claim 29, characterized in that there are at least two signal samples (C, D) between the first (B) and the second (E) non-successive signal samples, and in that the fourth detection device comprises: a device ( 80, 82) to generate a magnitude value between the first (B) and second (E) non-consecutive signal-25 samples; a first device (84, 86) for comparing the magnitude of the second intermediate signal sample with the intermediate magnitude value, while the fourth indication includes indications generated by the first and second devices; 30 second devices (88, 90) for comparing the second intervening signal sample to an intervening magnitude value; and that the fourth indication includes indications generated by the first device and the second device. A circuit according to claim 31, characterized in that the fourth detector device generates a fourth indication when the magnitudes of the signal samples (C, D) between the first (B) and second (E) non-consecutive signal samples are between consecutive signal sample sizes. 2i 76 901 The circuit of claim 1, characterized in that: said plurality of delay devices (10, 12, 14, 16, 18) provides samples of a respective plurality of first (CS) and second (YS) signals, each of which is time-delayed; and the detector device comprises a first detector device (30, 32) responsive to the first group (E, F) of the first signal samples for generating a first indication when the size of the samples in the first group differs by less than the first preset value (REF-1) , a second detector device (34, 36) responsive to the second group (A, B) of the first signal samples for generating a second assignment, than the size of the samples in the second group differs by less than the second preset value (REF-2), the third detector device (40, 42) responsive to the first two (B, E) signal samples to generate a third indication when the magnitudes of the two signal samples 20 differ by more than a third preset value (MIN), a fourth detector device responsive to the first group of second signal samples (YS) to generate a fourth indication , when the samples in the first group are large new differs by less than four-25 preset values, a fifth detector device responsive to the second group of second signal samples to generate a fifth indication when the sample size in the second group differs by less than the fifth preset value, a sixth detector device 30 responsive to the two second signal samples to generate a sixth indication when the magnitudes of the two signal samples differ by more than a sixth preset value, and to generate an indication indication of the indication generating device (46 ') in response to the first, second, third, fourth, fifth and sixth indications. 22 7 69 01 The circuit of claim 1, characterized by: a plurality of delay devices (10, 12, 14, 16, 18) comprising N delay devices, wherein N is an integer; a selective switching device (20, 22) comprising a first multiplexing device (20) interposed between a cascade of delay devices, the output of which is connected to the weather input si-10 of the Jth delay device (14), and the first and second inputs are connected respectively (J1 ): for the outputs of the delay device (12) and (J-2): for the delay device (10), where J is an integer not greater than N, the first multiplexer selectively connecting its first and second 15 inputs to its output in response to the control signal (MC), and the second a multiplexer (22) interposed between the cascade of the delay devices, the output of which is connected (K1) to the input of the delay device (16) and the first and second inputs of which are connected to the outputs of the delay device (K) (14) and (K1), respectively; where K is an integer not greater than N, the second multiplexer selectively coupling the first and to its input to its output in response to the control signal; A detector (100) comprising a first detector (30, 32) coupled to the delay device and responsive to the first group (E, F) of at least two consecutive input signal samples to detect that the magnitudes of the first group of consecutive input signal samples 30 are within a preset within the range (REF-1), a second detector device (34, 36) coupled to the delay device and responsive to the second group (A, B) of the at least two other consecutive input signal samples to detect that the magnitudes of the second group of consecutive input samples are within a preset range of reference values 23 76901 (REWF-2), a third detector device (40, 42) coupled to the delay device and responsive to the two non-consecutive (B, E) input signal samples, to detect that the two non-consecutive si -5 weather input signal sample sizes differ by at least a preset amount (MIN), and a device (46) for generating a control signal (MC) in response to the detection obtained by the first, second and third detectors and for supplying the control signal to the first and second channels-10 subscriber devices. A circuit according to claim 34, characterized in that the two non-consecutive samples (B, E) contain one sample from each of the first (E, F) and second (A, B) groups of consecutive samples. 76901