AT404200B - CIRCUIT ARRANGEMENT FOR PROCESSING SIGNALS - Google Patents

Description

AT 404 200 B

The invention relates to a shaft arrangement for processing signals according to the preamble of claim 1.

When signals pass through facilities whose bandwidth or response speed is limited, the rise and fall times of transitions between signal levels are limited accordingly. That means a lower bandwidth leads to slower signal transitions. In a television system, for example, the bandwidth of the chrominance signals is limited by the standard of the transmission system. In a system of the NTSC standard, for example, the I component (in-phase component) of the chrominance signal has a bandwidth of 1.5 MHz and the Q component (quadrature component) has a bandwidth of 0.5 MHz. It is not uncommon for the circuits of a television receiver to process both the I and the Q chromaticity components with a bandwidth of 0.5 MHz. Such processing of the chrominance signal is sufficient for most image conditions, although it would be desirable to improve the rise and fall times of the signals. Limited rise and fall times in the hue-tone signal, however, make the edges of objects appear less sharp and in worse color fidelity. These undesirable image effects are particularly noticeable when the object itself has a sharply defined edge, which can be reproduced by the luminance signal (4.2 MHz) that occurs with a high bandwidth, but not by the color tone signals transmitted with a smaller bandwidth. The effects mentioned are also noticeable when the color of the object differs significantly from the color of the background.

There is therefore a need for circuit arrangements which can detect the occurrence of very specific signal transitions and are able to improve (i.e. shorten) the rise and fall times of such transitions. Conventional amplification circuits, which emphasize the higher-frequency components of a signal compared to the lower-frequency components, have only a limited effect if the higher-frequency components have been strongly attenuated due to a limited signal bandwidth.

The aim of the invention is to avoid these disadvantages and to propose a circuit arrangement of the type mentioned at the outset which makes it possible to change the delay as a function of the input signals.

According to the invention, this is achieved in a circuit arrangement of the type mentioned at the outset by the characterizing features of claim 1.

A signal processing circuit according to the invention contains a plurality of cascade-connected delay devices for successively delaying the input signals, a device for detecting the amplitude transitions of the input signals and a coupling device which responds to the aforementioned detection device in order to selectively couple the inputs of selected copies of the delay devices to one another.

This makes it possible, depending on the presence of certain criteria, to bridge more or less of the delay stages.

The features of claim 1 result in a very simple construction of the circuit arrangement.

The features of claim 3 allow rapid adaptation of the delay to the respective input signals.

The features of claims 4 and 5 allow a very precise adaptation of the delay time to the respective requirements.

The invention is explained in more detail below using exemplary embodiments with reference to drawings.

Fig. 1 shows in block form an embodiment of an arrangement according to the invention;

Figures 2a and 2b are graphical representations of signals in the arrangement of Fig. 1;

Figures 3 to 7 are circuit diagrams of parts of the arrangement of Fig. 1 in modified and alternative embodiments.

If the individual embodiments are explained below in connection with digital signals, this is not to be understood as a limitation, but only as an example. It should be noted that the invention can also be implemented with many other types of signals, e.g. with queried signals in analog or digital form or with analog signals. In the drawings, broad arrows represent signal paths for digital signals with several bits in parallel, while thin lines represent paths for digital signals from a single or serial bits or for analog signals.

Fig. 1 shows a circuit arrangement which serves to improve signal transitions and contains a transition detector. The circuit arrangement is designed for the treatment of digital chrominance signals in a television receiver which works with digital signal processing. The receiver generates digital color signals CS, which are further processed with the aid of the arrangement according to the invention in order to generate improved digital color signals CS '. 2nd

AT 404 200 B

1 contains a combination of several delay stages 10, 12, 14, 16 and 18 and multiplexers 20 and 22, which serves to improve the rise and fall times and whose operation is first described. The operation of a transition detector 100 included in the arrangement will be described later.

First of all, it is assumed that the multiplexers (abbreviated MUX) 20 and 22 couple the signals appearing at positions D and C to their respective outputs and that the input signals CS are successively delayed by the delay stages 10, 12, 14, 16 and 18 connected in cascade are, so that the output signals CS 'simply represent a time-delayed version of the input signals CS. Each of the delay stages 10, 12, 14, 16 and 18 is e.g. a buffer for 8 parallel bits, which is controlled by a clock signal f, *. The clock signal i has a repetition frequency which is related to the color subcarrier frequency (approximately 3.85 MHz in the NTSC television system). The signal CS ’is compared to the signal CS by five periods of the clock signal frequencies2 f«. delayed.

If transitions appear in the CS signal that meet predetermined criteria in terms of their magnitude and their rise or fall times, then the transition detector 100 generates a control signal MC and applies it to the multiplexers 20 and 22 so that these multiplexers selectively input certain instances of the delay stages couple with the inputs of other delay stages. In particular, multiplexer 20 couples the input of delay stage 12 to the input of delay stage 14 and separates the output of stage 12 from the input of stage 14. Similarly, multiplexer 22 couples the input of delay stage 18 to the input of delay stage 16 and separates the output of stage 14 from the input of stage 16.

As an example, consider the case where the temporal sequence of the interrogation values (signal samples) A. B, C, D, E and F of the signal CS forms a transition from a lower amount to a higher amount (positive transition), as is the case with the Fig. 2a shows. It should be mentioned that in a system working with interrogated analog or digital signal samples, the signal maintains the respectively interrogated value for the said duration of an interrogation period. The straight line connection shown in FIG. 2a between individual query values only serves to explain the arrangement to be described here. The time interval shown in FIG. 2a corresponds to the time which elapses until the sequence of samples of the signal CS has been transmitted by the delay stages 10, 12, 14, 16 and 18. Each of the query values denoted by the letters A to F in FIG. 2a thus corresponds to the value of the signal sample that is currently on the signal path denoted by the same letter in FIG. 1. This means that the signal CS has the amount represented by the query value F at the moment and had five periods of the clock signal fs the amount represented by the query value A a time ago. The solid line 50 in FIG. 2a connects query values A through F to indicate the rise time of the transition represented by these query values.

It is further assumed that, at the time in question, the sequence of signal samples shown has such magnitudes that the detector 100 generates the control signal MC, whereby the multiplexers 20 and 22 are activated in the manner described above. Multiplexer 20 then replaces sample D with the value of sample E at the input of delay stage 14, and multiplexer 22 replaces the value of sample C with the value of sample B at the input of delay stage 16. These replacement processes are shown in FIG. 2a indicated by arrows 54 and 52, and the query values obtained and newly used from query values E and B are identified by D 'and C'. At the next period of the clock signal f *. samples B, C ', D', E and F are stored in delay stages 18, 16, 14, 12 and 10 (in that order), and detector 100 removes control signal MC because the. Detection criteria for the transition are no longer met. In the next periods of the clock signal f «, the signal CS 'appears modified as a result of the query values A, B, C', D \ E, F (ie successively with the amounts A, B, B, E, E, F), in which a signal transition with an improved (ie shorter) rise time takes place. The dashed line 56 in FIG. 2a connects the query values of the modified sequence to illustrate the shortening of the rise time of the transition.

As a further example, consider a sequence of samples of the signal CS, which, as shown in FIG. 2b, forms a transition from a higher amount to a lower amount (negative-directional transition), as shown by line 60. Similar to the mode of operation described above in connection with FIG. 2a, the multiplexers 20 and 22 effect two replacements 62 and 64 of query values on the basis of the control signal MC, so that the modified value sequence A, B, B, E, E, F with a shortened fall time appears, as illustrated by broken line 66.

The transition detector 100 and the predetermined criteria upon meeting which a transition is detected are described below. A "transition" of a signal is a change in the instantaneous amplitude from one amplitude value to another amplitude value and can be described by the difference between the two values and by the time required for the change. If the third

AT 404 200 B

Signals, for which digital signals are an example, a transition can be described by the amounts of signal samples or sample groups and by the number of samples over which the change in amount extends.

Detector 100 detects a transition when the magnitudes of the signal samples in each of two groups of immediately consecutive samples are relatively close together and when the magnitude difference between non-consecutive signal samples is substantial. That is, in a sequence of six immediately consecutive signal samples, a transition is detected if 1) the first and second samples (first group of directly consecutive samples) are relatively close in terms of their amount, 2) the fifth and sixth samples (second group immediately consecutive samples) are also relatively close in terms of the amount and 3) the amounts of the second and fifth samples (two non-consecutive samples) differ significantly from one another. These three criteria mean that the first, the second, the fifth and the sixth sample are not part of a transition and that there is an essential transition between the two groups of samples mentioned, e.g. is shown in Figures 2a and 2b.

The transition detector 100 according to FIG. 1 contains a subtracting circuit 30, which forms the absolute value of the difference between the amounts (amplitudes) of directly successive samples E and F and outputs it to a comparator 32. The comparator 32 supplies an output of an AND gate 46 with an output signal which has an activating level when the absolute value of the difference | E-F | is lower than a relatively small value REF-1. Similarly, a subtraction circuit 34 forms the absolute value of the difference between the directly successive query values A and B, and a downstream comparator 36 applies an activating level to a second input of the AND gate 36 if the difference | A-B | is less than a relatively small value REF-2. In addition, a subtraction circuit 40 forms the absolute value of the difference | BE | from the non-directly consecutive query values B and E, which, if greater than a considerable minimum value MIN, causes a comparator 42 to supply an activating level to a third input of the AND gate 46 lay. Provided that an additional activation signal EN is present, the coincidence-activating level at the inputs of the AND gate 46 causes a control signal MC, which causes the multiplexers 20 and 22, to output the value of the sample E to the input of the delay stage 14 and apply the value of sample B to the input of delay stage 16 as described above. The criteria for detecting a transition are summarized in Table I below:

TABLE I

No. elements test criteria on AND gate 46 1. 30.32 IE-FI < REF-1 2. 34, 36 IA-BI < REF-2 3. 40, 42 IB-EI > MIN 4. 48 EN = 1

The activation signal EN, which switches the detector 100 on and off, is generated by a control device 48. The control device 48 is e.g. a transition detector that generates the activation signal EN due to transitions in the luminance signal YS. The signals CS and YS are temporally related to each other because they are component signals of the same picture. The controller 48 can be omitted.

Element 47 is a pulse generator or digital monopulser which, under the control of the AND gate 46 and the clock signal fsc, generates a pulse MC which e.g. is one sampling period wide and within e.g. two sampling periods can only be generated once. Monopulser 47 prevents continuous circulation of samples within the loop containing multiplexer 22 and delay stage 16, as might occur if the transition detector exceeded the steepening circuit. On the other hand, if the transition detector and the step-up circuit used separate but parallel delay stages, then the monopulser 47 would not be needed.

The transition detector 200 shown in FIG. 3 is a modification of the detector 100, in which additional detection criteria have to be met in order to generate the control signal MC. The additional detection criteria ensure that the transition is only improved if the signal transition is relatively soft and monotonous. This avoids that valid query information of higher frequencies is lost. 4 ΑΤ 404 200 Β

For this purpose, the conditions are established as additional detection criteria that the difference in amount between the second and fifth samples in the signal transition must not be greater than a maximum value and that the amounts of the third and fourth samples between the mean of the amounts of the second and fifth samples and the Amount of the second sample or the amount of the fifth sample.

The detector 200 contains subtracting circuits 30, 34 and 40 and comparators 32, 36 and 42 which correspond to the elements of the detector 100 described above with the same reference numbers. A comparator 44 applies an activating level to an input of the AND gate 46 'when the absolute value of the difference | B-E | formed by the subtracting circuit 40 is less than a maximum value MAX, which in turn is greater than the minimum value MIN. The subtracting circuit 40 also generates a sign bit SB, which indicates whether the transition is positive or negative, and which is used to simplify the comparator structure to test the additional detection criteria.

The criteria indicating that a transition is smooth and monotonic are checked using comparators 70, 74, 84 and 88 in the manner described below. The comparator 70 compares the signal samples B and C, and the result of this comparison is optionally inverted in a controllable inverter 72 depending on the sign bit SB. Thus, an input of the AND gate 46 'is activated when the criterion B < C is satisfied for positive transitions and if the criterion B > C is fulfilled for negatively directed transitions. Similarly, through the action of the comparator 74 and a controllable inverter 76, an input of the AND gate 46 'is activated if the criterion D < E for positive transitions and the criterion D > E is fulfilled for negatively directed transitions. This recognizes that the amounts of signal samples C and D lie between the amounts of samples B and E, which is a first indication of monotony.

An adding circuit 80 and a circuit 82 dividing by "two" form the mean of the amounts of samples B and E, which is indicated in FIGS. 2a and 2b by the dashed line 1/2 (B + E). In the case of interrogated analog signals, circuits 80 and 82 are an ohmic network, and for digital signals circuit 80 is an adder and circuit 82 is an arrangement for position shifting, which is formed by wiring. The comparator 84 and a controlled inverter 86 activate an input of the AND gate 46 'if, in the case of positive transitions, the criterion C < 1 / 2- (B + E) and in the case of negatively directed transitions the criterion C > 1/2 (B + E) is fulfilled. Similarly, the comparator 88 and a controllable inverter 90 activate an input of the AND gate 46 *. if in the case of positively directed transitions the criterion D > 1/2 (B + E) and in the case of negatively directed transitions the criterion D < 1/2 (B + E) is fulfilled. This assures that the amount of sample C is between the mean of B and E and the amount of sample B and that the amount of sample D is between the aforementioned average and the amount of sample E. This is another indication of monotony.

The AND gate 46 'generates the control signal MC when activation signals coincide at all inputs of this gate. The detection criteria of the embodiment according to FIG. 3 are summarized in Table II below:

TABLE II

No. elements test criteria on AND gate 46 'positive transition negative transition 1. 30, 32 IE-FI < REF-1 IE-FI < REF-1 2. 34, 36 IA-BI < REF-2 IA-BI < REF-2 3. 40, 42 IB-EI > MIN IB-EI > MIN 4. 40, 44 IB-EI < MAX IB-EI < MAX 5. 70.72 B < C B > C 6. 74, 76 D < E D > E 7. 80, 82, 84, 86 C < 1/2 (E + B) C > 1/2 (B + E) 8. 80, 82, 88, 90 D > 1/2 {E + B) D < 1/2 (B + E) 9. 48 EN = 1 EN = 1 The following nominal values can be used in the comparison processes for a color beard signal coded as an 8-bit digital signal with values that correspond to the range of decimal numbers from 0 to 255: REF-1 = 8, REF-2 = 8, MIN = 48, MAX = 255. 5

AT 404 200 B

The remaining part of FIG. 3 shows the control circuit 48, which has a device for detecting transitions in the luminance signal. The luminance signals YS are successively delayed in individual delay stages 310, 312, 314, 316 and 318 and applied to the transition detector 300. The detector 300 is e.g. constructed similarly to the detector 100 or 200 described above, except that the control signal supplied by it is given as an activation signal EN to the AND gate 46 '. The delay stages 310 to 318 can be formed by a delay line which is part of a so-called " filter with finite impulse response " (abbreviated: FIR filter) or a comb filter is present within the luminance processing circuit.

Figures 4 and 5 show embodiments of devices which e.g. the comparators 32, 36, 42 or 44 in Figures 1 and 2 can replace. These embodiments can be used if the digital query values are presented in a form with sign and amount. In the device according to FIG. 4, an AND gate 32 ′ provided with inverted inputs switches through when a selected number of the upper (ie more significant) bits (but not the sign bit) of the difference value formed by the subtracting circuit 30 all have the value " 0 " have to apply an activating level to the AND gate 46 or 46 'in this case. 5, a NOR gate responds when a selected number of the uppermost bits of the absolute value of the difference formed by the subtracting circuit 30 all have the value " 0 " have to apply an activating level to the AND gate 46 or 46 '.

The level of the 32 'or 32 " provided reference value REF-1 is given by (2N-1), where N is the number of lower bits not connected to the link, as shown in Table III below:

TABLE III AND gate 32 'and NOR gate 32 " Value of REF-1 connected top bits not connected bottom bits 8 0 0 7 1 1 6 2 3 5 3 7 4 4 15 3 5 31 2 6 63 1 7 127

Fig. 6 shows the embodiment of a device which e.g. can be used as a replacement for the comparator 42 in FIG. 2 if the digital query values are represented in a form with sign and amount. An OR gate 42 'responds when any of the uppermost bits of the absolute value of the difference formed by the subtracting circuit 40 is "1" to apply an activating level to the AND gate 46 or 46'. The value of the reference quantity MIN is given by (2N-1>, where N is the number of the lowest bits that are not connected to the OR gate 42.

Modifications to the above-described embodiments are also possible. For example, the subtracting circuit 80. the dividing circuit 82, the comparator 88 and the inverter 90 are omitted in the arrangement according to FIG. 2 and the signal samples C and D are fed directly to the comparator 84, in this case a monotony is indicated if this is the case for positive signal transitions Criterion C < D is satisfied and if the criterion C > D is satisfied. Incidentally, as the comparator arrangements in FIGS. 4, 5 and 6 show, the absolute value of the difference for digital numbers represented with sign and amount is obtained by excluding the sign bit SB from the comparison.

The number of delay stages 10, 12, 14 ... used, the repetition frequency of the clock signal fsc, the copies of the successively delayed samples of the signal CS supplied to the detectors 100 and 200 and the location of the multiplexers 20 and 22 within the cascade of the delay stages all influence the limits of the rise and fall times for the detection of transitions and the extent to which the rise and fall times are shortened. To e.g. Improving the transitions of luminance signal samples generated at four times the color subcarrier frequency (i.e. at 4 ^ * 14.32 MHz in the case of the NTSC system) requires a greater number of delay stages. Also 6

Claims (6)

AT 404 200 B may contain the sample groups mentioned above more or less than the two samples described (A, B and E, F), and the number of samples between these groups may be greater or less than the number 2 described above (samples C and D) be. Transitions that are faster than the transitions shown in Figures 2a and 2b can be improved as long as at least one signal sample lies within the transition, i.e. as long as the two signal samples compared to detect a transition do not immediately follow one another. For example, the circuit of FIG. 1 can be modified so that the signal samples E and C of FIG. 2 are compared by the subtracting circuit 40 and the comparator 42 to detect a transition. In this case the delay stages 12 and 14 and the multiplexer 20 are the most important elements and only the replacements 54 and 64 according to FIGS. 2a and 2b are carried out. The multiplexer 22 can then be omitted and the delay stage 14 can be connected directly to the delay stage 16. In the above description, the improvement of transitions is to shorten the rise and fall times of the transitions. However, the invention is also suitable for increasing the rise and fall times. In a modification of this, the multiplexer 20 is inserted before the delay stage 12 and receives the signal samples E and D at its inputs, the multiplexer 22 is placed before the delay stage 18 and receives the signal samples C and B at its inputs, the delay stage 12 is with the Delay stage 14 is connected, and delay stage 14 is connected to delay stage 16. Detector 100 provides a control signal MC to cause Sample B to be replaced by Sample C and Sample E to be replaced by Sample 0. For example, it is also possible to omit controllable inverters 72, 76, 86 and 90 and to provide additional multiplexers to reverse the input signals for each of comparators 70, 74, 84 and 88. Finally, it should be mentioned that other digital codes can also be processed by the arrangement according to the invention by inserting suitable converters at suitable locations within the transition detectors 100 and 200, e.g. the converter shown in FIG. 7, which converts the two's complement to the binary representation. 1. Circuit arrangement for processing signals, with an input for receiving input signals and an output, where output signals are generated in response to the input signals, and with a plurality of delay stages which are connected in cascade between the input and the output to delay the input signals step by step, characterized by a transition detector (100), which is coupled to the plurality of delay stages (10, 12, 14, 16, 18) and detects changes in the input signal and examines them for specific criteria; a first switching device (20, 22) connected to delay stages (12, 14, 16, 18) from the plurality of delay stages and to the transition detector (100), which selectively detects a delay stage (12) when a change in the input signal having the specific criteria is detected bridged. 2. Circuit arrangement according to claim 1, characterized in that the delay stages (12, 14, 16, 18) are connected in series with the interposition of at least one switching device (20, 22). 3. Circuit arrangement according to claim 1, characterized in that two switching devices (20, 22), which are preferably designed as multiplexers, are interposed in the series circuit of the delay stages (10, 12, 14, 16, 18), wherein between the switching devices (20 , 22) at least one delay stage (14) is arranged. 4. Circuit arrangement according to claim 1, characterized in that the transition detector (100) is a subtracting circuit (40), the inputs of which are connected to the outputs of a pair (10, 16) of not immediately successive delay stages from the plurality of delay stages (10, 12, 14, 26, 18), and has a comparator (42) which has its first input connected to the output of the subtracting circuit (40) and has a reference signal (MIN) at its second input, and at least one further subtracting circuit (30) , the inputs of which are coupled to the inputs of a pair (10, 12) of immediately successive delay stages from the plurality of delay stages (10, 12, 14, 16, 18) and a further comparator (32) is provided, which compares with its first Input is connected to the output of the additional 7 AT 404 200 B subtracting circuit (30) and at its second input a further reference signal (R EF-1) is applied, the outputs of the comparators (42, 32) being connected to a logic circuit (46, 47) which is connected on the output side to and / or controls the switching devices (20, 22). 5. A circuit arrangement according to claim 1 and 4, characterized in that the transition detector (100) has two further subtractor circuits (30, 34), the inputs of which are connected to the inputs of a pair (10, 12; 16, 18) of directly successive, the Input or output of the circuit arrangement closest delay stages from the plurality of delay stages (10, 12, 14, 16, 18) are coupled and the outputs of these further subtracting circuits (30, 34) are each connected to an input of a comparator (32, 36) a reference signal (REF-1, REF-2) is present at each of the second inputs. 6. Circuit arrangement according to claim 1, characterized in that for processing an input signal (CS), which is formed by the color signal component of a color television signal mixture also having a luminance signal component (YS), a control circuit (48) is connected to the transition detector (100) the input of which the luminance signal component (YS) is present, the control circuit (48) sending an activation signal (EN) to the transition detector (100) as a function of transitions in the luminance signal component (YS). Including 3 sheets of drawings 8