JPH05243863A - Chopper stabilizing operational amplifier - Google Patents

Abstract

PURPOSE:To eliminate an input offset voltage by executing operations of write of an input voltage and voltage holding by an external signal, switching alternately internal signal systems by a chopping circuit under the control from a control circuit, and making a balanced state of the inside. CONSTITUTION:A control circuit 51 controls opening and closing of a first a fourth switch means 52, 54, 56 and 58 of a chopping circuit 50, and also, controls start and stop operations of a first and a second sequential A/D converters 67, 68. Also, the control circuit 51 outputs alternately control signals, and repeats alternately a first correcting operation of a first input branch and a third input branch, and a second correcting operation of a second input branch and a third input branch. As a result, a first input branch 42 and a second input branch 44 are balanced, and an offset voltage of a chopper stabilizing operational amplifier 1 can be eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of an amplifier circuit, and more particularly to a chopper-stabilized operational amplifier for correcting an offset voltage.

[0002]

BACKGROUND OF THE INVENTION Differential amplifier circuits output an output voltage as a function of the potential difference between their inputs. If both inputs are short-circuited, the potential difference between the inputs is essentially zero, so the output should also be zero. However, an unbalanced state occurs inside the amplifier due to various factors, and the output voltage of the amplifier causes an offset voltage from the ideal state.

FIG. 2 is a circuit diagram showing a configuration of a chopper-stabilized operational amplifier invented for removing an offset voltage as disclosed in Japanese Patent Laid-Open No. 58-3304, which is a conventional technique.

A chopper-stabilized operational amplifier 101 described in this publication has a negative input terminal 12, a positive input terminal 14, an output terminal 36, a positive power supply terminal 92, a negative power supply terminal 94, and a current supply element 62. And the differential pair circuit 40
It has a chop circuit 50, a control circuit 51, a voltage supply element 64, a first voltage holding capacitor 66a, a second voltage holding capacitor 66b, an inverting amplifier circuit 72, and an output buffer circuit 74.

The differential pair circuit 40 includes a first input branch 42.
And a second input branch 44 and a third input branch 46.

At the fourth terminal 22, a first input branch 42, a second input branch 44, and a third input branch 46.
And the current supply element 62 connected to the positive power supply terminal 92.
And connect.

At the fifth terminal 24, a first input branch 42, a second input branch 44, and a third input branch 46.
And the voltage supply element 64 connected to the negative power supply terminal 94.
And a first voltage holding capacitor 66a connected to the sixth terminal 34a and a second voltage holding capacitor 66b connected to the seventh terminal 34b.

The differential pair circuit 40 is connected to the output buffer circuit 74 at the second terminal 44c and connected to the inverting amplifier circuit 72 at the third terminal 46c.

The first input branch 42 has a first terminal 42c.
And a first active input element 42a and a first active load element 42b whose drains are connected to each other.

The input of the first active input element 42a is connected to the negative input terminal 12, and the first active input element 42a is connected.
The board input of a is connected to the positive power supply terminal 92.

The input of the first active load element 42b is connected to the first terminal 42c, and the substrate input of the first active load element 42b is connected to the sixth terminal 34a.

The second input branch 44 has a second terminal 44c.
And a second active input element 44a and a second active load element 44b whose drains are connected to each other.

The input of the second active input element 44a is connected to the plus input terminal 14, and the second active input element 44a is connected.
The board input of is connected to the positive power supply terminal 92.

The input of the second active load element 44b is connected to the first terminal 42c, and the substrate input of the second active load element 44b is connected to the seventh terminal 34b.

The third input branch 46 has a third terminal 46c.
And a third active input element 46a and a third active load element 46b whose drains are connected to each other.

The input of the third active input element 46a is connected to the switching terminal 16, and the third active input element 46a is further connected.
The board input of is connected to the positive power supply terminal 92.

The input of the third active load element 46b is connected to the first terminal 42c, and the substrate input of the third active load element 46b is connected to the fifth terminal 24.

The chop circuit 50 has a first switch means 52 and a second switch means 54.

The first switch means 52 has a first switch 52a and a second switch 52b.

The first switch 52a is connected to the minus input terminal 12 and the switching terminal 16, and the second switch 52b is connected to the plus input terminal 14 and the switching terminal 16.

The second switch means 54 has a third switch 54a and a fourth switch 54b.

The third switch 54a is connected to the eighth terminal 3
2 and the sixth terminal 34a, and the fourth switch 54
b is connected to the eighth terminal 32 and the seventh terminal 34b.

The conventional chopper stabilizing operational amplifier 101 is constructed by the circuit described with reference to FIG. Next, the operation of the chopper-stabilized operational amplifier based on the above configuration will be described.

First, from the control circuit 51 to the first switch means 52, the first switch 52a is closed and the second switch 5 is closed.
A signal for opening 2b is sent, and the same voltage as at the minus input terminal 12 appears at the switching terminal 16. Then, the deviation between the first input branch 42 and the third input branch 46 becomes the third terminal 46.
It will appear in c.

This deviation is input to the inverting amplifier circuit 72, and the output voltage of the inverting amplifier circuit 72 appears at the eighth terminal 32.

At the same time, a signal is sent from the control circuit 51 to the second switch means 54 to close the third switch 54a and open the fourth switch 54b, and the first active load element 42b.
To the substrate input of the inverting amplifier circuit 7 through the sixth terminal 34a
The second output voltage is applied, the first correction operation is started, and the first correction operation is performed.
Input branch 42 and the third input branch 46 are balanced, and the output voltage of the inverting amplifier 72 at this time is equal to the first voltage holding capacitance 6
6a is stored.

Next, the first switch 52a is opened from the control circuit 51 to the first switch means 52, and the second switch 5 is opened.
A signal for closing 2b is sent, and the same voltage as the plus input terminal 14 appears at the switching terminal 16. Then, the deviation between the second input tributary 44 and the third input tributary 46 becomes the third terminal 46.
It will appear in c.

This deviation is input to the inverting amplifier circuit 72, and the output voltage of the inverting amplifier circuit 72 appears at the eighth terminal 32.

At the same time, the third switch 54a is opened from the control circuit 51 to the second switch means 54, and the fourth switch 5 is opened.
The signal for closing 4b is sent to the second active load element 44b.
To the substrate input of the inverting amplifier circuit 7 through the seventh terminal 34b.
The second input voltage 44 and the third input voltage 46 are balanced, and the output voltage of the inverting amplifier circuit 72 at this time is the second voltage holding capacitance. 6
6b is stored.

The control circuit 51 alternately outputs the above-described signals, whereby the first input branch 42 and the third input branch 46 are output.
By alternately repeating the first correction operation of and the second correction operation of the second input branch 44 and the third input branch 46, the first input branch 42 and the second input branch 44 Are balanced and the offset voltage of the chopper stabilizing operational amplifier 101 is removed.

[0031]

In the chopper stabilizing operational amplifier 101 described above, the first input branch 42 and the second input branch 44 are in balance after the power is turned on, and the offset voltage is removed. It can be understood from the above description of the prior art that the first voltage holding capacitor and the second voltage holding capacitor are required to maintain the stable operation state.

Furthermore, it can be easily understood that a considerably large capacitance value is required in order to prevent the influence of external noise and the like.

In addition, the time required from when the power is turned on until the stable state is reached is required, and the charge held in the capacitor changes with a certain time constant due to the influence of leakage current. It is unavoidable, and it is destined to constantly perform rewriting operations.

The object of the present invention is to solve the above problems,
An object of the present invention is to provide a chopper-stabilized operational amplifier that does not require a voltage holding capacity.

[0035]

To achieve the above object, a chopper-stabilized operational amplifier according to the present invention adopts the configuration described below.

The chopper-stabilized operational amplifier according to the present invention includes a negative input terminal, a positive input terminal, an output terminal, a positive power supply terminal, a negative power supply terminal, a current supply element, a differential pair circuit, and a control circuit. Circuit, chop circuit, voltage supply element, first sequential AD converter, and second sequential AD
The differential pair circuit includes a converter, an inverting amplifier circuit, and an output buffer circuit, and the differential pair circuit includes a first input branch, a second input branch, and a third input branch, and the first input branch is A first active input element and source in which the source is connected to the fourth terminal, the drain is connected to the first terminal, the gate is connected to the negative input terminal, and the substrate electrode is connected to the positive power supply terminal. Is connected to the fifth terminal, the drain is connected to the first terminal, the gate is connected to the first terminal, and the substrate electrode is connected to the sixth terminal. Source is the fourth input branch of
The second active input element and source connected to the positive terminal, the drain connected to the second terminal, the drain connected to the second terminal, the gate connected to the positive input terminal, and the substrate electrode connected to the positive power supply terminal. A second active load element having a drain connected to the second terminal, a gate connected to the first terminal, and a substrate electrode connected to the seventh terminal. A third active input element having a source connected to the fourth terminal, a drain connected to the third terminal, a gate connected to the switching terminal, and a substrate electrode connected to the positive power supply terminal; Connected to the terminal of and the drain is the third
A third active load element having a gate connected to the first terminal and a substrate electrode connected to the fifth terminal.
The chop circuit comprises first switch means, second switch means, third switch means and fourth switch means. One of the first switch means is connected to the minus input terminal and the other is connected to the switching terminal. A second switch, one of which is connected to the positive input terminal and the other of which is connected to the switching terminal
The second switch means, one of which is connected to the sixth terminal and the other of which is connected to the eighth terminal.
And a fourth switch, one of which is connected to the seventh terminal and the other of which is connected to the eighth terminal. This third switch means has one connected to the sixth terminal and the other connected to the first terminal. A
A fifth switch connected to the first serial AD converter input terminal of the D converter and one connected to the sixth terminal and the other to the first serial AD converter output terminal of the first serial AD converter. And a sixth switch to be connected, wherein the fourth switch means has a seventh switch, one of which is connected to the seventh terminal and the other of which is connected to the second successive AD converter input terminal of the second successive AD converter. And an eighth switch, one of which is connected to the seventh terminal and the other of which is connected to the second sequential AD converter output terminal of the second sequential AD converter, and the control circuit includes the first switch means and the second switch. Controlling the opening and closing of the switch means, the third switch means and the fourth switch means, the input of the inverting amplifier circuit is connected to the third terminal and the output is connected to the eighth terminal, and the output buffer circuit is connected to the input. The second terminal is connected, the output is connected to the output terminal, and the current supply element is It is connected to the positive power supply terminal connected to the other of the fourth terminal, one voltage supply device and the other connected to the negative supply terminals, characterized in that connected to the fifth terminal.

[0037]

In place of the first voltage holding capacitor and the second voltage holding capacitor of the conventional chopper-stabilized operational amplifier, the third switch means, the fourth switch means, the first successive A / D converter and the first Two sequential AD converters are provided.

This successive A / D converter converts the data, which is always converted into digital in the process of converting the input voltage from analog into digital, into analog again and compares it with the input voltage to judge the magnitude. However, it is based on the operating principle that the input voltage and the digitally converted value are finally made to match. Further, since this operation is performed in synchronization with the clock signal, it has a characteristic of maintaining the state before the stop when the clock is stopped.

Therefore, it has the functions of writing and holding the input voltage required by the chopper-stabilized operational amplifier and is optimal.

[0040]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a circuit configuration in an embodiment of the chopper stabilizing operational amplifier of the present invention.

As shown in the circuit diagram of FIG. 1, the chopper-stabilized operational amplifier 1 according to the present invention has a minus input terminal 1
2, the positive input terminal 14, the output terminal 36, the positive power supply terminal 92, the negative power supply terminal 94, and the current supply element 62.
, Differential pair circuit 40, chop circuit 50, control circuit 51, voltage supply element 64, and first sequential AD converter 6
7, a second sequential AD converter 68, and an inverting amplifier circuit 72
And an output buffer circuit 74.

The differential pair circuit 40 includes a first input branch 42.
And a second input branch 44 and a third input branch 46.

At the fourth terminal 22, a first input branch 42, a second input branch 44, and a third input branch 46.
And the current supply element 62 connected to the positive power supply terminal 92.
And connect.

At the fifth terminal 24, a first input branch 42, a second input branch 44, and a third input branch 46.
And the voltage supply element 64 connected to the negative power supply terminal 94.
And connect.

The differential pair circuit 40 is connected to the output buffer circuit 74 at the second terminal 44c and connected to the inverting amplifier circuit 72 at the third terminal 46c.

The first input branch 42 is connected to the first terminal 42c.
The first active input element 42a and the first active input element 42a
Active load element 42b.

The source of the first active input element 42a is the fourth
Connected to the terminal 22 of the first active input element 42a, the drain connected to the first terminal 42c, the input connected to the negative input terminal 12, and the substrate input of the first active input element 42a connected to the positive power supply terminal 92.
Connect with.

The source of the first active load element 42b is the fifth
, The drain is connected to the first terminal 42c, the input is connected to the first terminal 42c, and the substrate input of the first active load element 42b is connected to the sixth terminal 34a.

The second input branch 44 has a second terminal 44c.
Second active input element 44a and second active input element 44a
Active load element 44b.

The source of the second active input element 44a is connected to the fourth terminal 22, and the drain is the second terminal 44c.
, The input is connected to the positive input terminal 14, and the substrate input of the second active input element 44a is connected to the positive power supply terminal 9
Connect with 2.

The source of the second active load element 44b is the fifth
, The drain is connected to the second terminal 44c, the input is connected to the first terminal 42c, and the substrate input of the second active load element 44b is connected to the seventh terminal 34b.

The third input branch 46 has a third terminal 46c.
The third active input element 46a and the third active input element 46a
Active load element 46b.

The source of the third active input element 46a is connected to the fourth terminal 22, and the drain is the third terminal 46c.
, The input is connected to the switching terminal 16, and the substrate input of the third active input element 46a is connected to the positive power supply terminal 92.

The source of the third active load element 46b is the fifth
, The drain is connected to the third terminal 46c, the input is connected to the first terminal 42c, and the substrate input of the third active load element 46b is connected to the fifth terminal 24.

The chop circuit 50 includes a first switch means 52, a second switch means 54 and a third switch means 5.
6 and a fourth switch means 58.

The first switch means 52 has a first switch 52a and a second switch 52b. This first
The switch 52a is a minus input terminal 12 and a switching terminal 1
6, and the second switch 52b is connected to the plus input terminal 14 and the switching terminal 16.

The second switch means 54 has a third switch 54a and a fourth switch 54b. This third
The switch 54a of the eighth terminal 32 and the sixth terminal 34
a and the fourth switch 54b is connected to the eighth terminal 3
2 and the seventh terminal 34.

The third switch means 56 has a fifth switch 56a and a sixth switch 56b. The fifth switch 56a includes a sixth terminal 34a and a first sequential AD converter input terminal 67a of the first sequential AD converter 67.
And the sixth switch 56b is connected to the sixth terminal 34
a and the first sequential AD converter output terminal 67b of the first sequential AD converter 67.

The fourth switch means 58 has a seventh switch 58a and an eighth switch 58b. The seventh switch 58a includes a seventh terminal 34b and a second sequential AD converter input terminal 68a of the second sequential AD converter 68.
And the eighth switch 58b is connected to the seventh terminal 34
b and the second sequential AD converter output terminal 68b of the second sequential AD converter 68.

The control circuit 51 is the first circuit of the chop circuit 50.
Of the switch means 52, the second switch means 54, the third switch means 56, and the fourth switch means 58 are controlled, and the first sequential AD converter 67 and the second sequential A are controlled.
It controls the start and stop operations with the D converter 68.

The first sequential AD converter 67 and the second sequential A
As shown in FIG. 3, the D converter 68 includes a comparator 81,
Control circuit 82, successive approximation register 83, D
A converter 84.

When an input voltage is applied to the input terminal 87a of this successive A / D converter and a clock signal is input to the control circuit 82 from the outside, the successive approximation register 83 performs a count-up or count-down operation. Further, the DA converter 84 converts this data into an analog signal to generate an output voltage at the output terminal 87b of the successive A / D converter, and the comparator 81 compares the input voltage with the output voltage to determine the magnitude relationship between them. Then, the result is passed to the control circuit 82.

Upon determination of the magnitude relationship between the input voltage and the output voltage, if it is large, an instruction to reduce the value of the output voltage converted by the DA converter 84 into analog is given to the successive approximation register 83, and conversely if it is small, it is increased. The control circuit 82 operates so as to give an instruction to perform. As a result, the successive A / D converter operates as shown in the graph of FIG.

When the clock from the outside is stopped, the output voltage before the clock is stopped is maintained.

The circuit described above constitutes the chopper stabilizing operational amplifier 1 of the present invention. Next, the operation based on the configuration of the above chopper stabilizing operational amplifier will be described.

First, from the control circuit 51, the first switch means 52, the second switch means 54, the third switch means 56, the fourth switch means 58, and the first sequential A.
A signal is sent to the D converter 67 and the second sequential AD converter 68.

Then, the first switch 52a is closed and the second switch 52a is closed.
Switch 52b is opened, the third switch 54a is closed, the fourth switch 54b is opened, and the fifth switch 56b is opened.
a is closed, the sixth switch 56b is opened, the seventh switch 58a is opened, the eighth switch 58b is closed, the first successive A / D converter 67 starts operating, and the second successive A / D converter 68 is stopped. ..

As a result, the same voltage as that at the minus input terminal 12 appears at the switching terminal 16, and the deviation between the first input branch 42 and the third input branch 46 appears at the third terminal 46c.

This deviation is input to the inverting amplifier circuit 72,
The output voltage of the inverting amplifier circuit 72 appears at the eighth terminal 32.

To the substrate input of the first active load element 42b,
The output voltage of the inverting amplifier circuit 72 is applied through the sixth terminal 34a, the first correction operation starts, and the first input branch 4
The second and third input branches 46 are in equilibrium, and the output voltage of the inverting amplifier 72 at this time is taken into the first sequential AD converter 67.

Next, from the control circuit 51, the first switch means 52, the second switch means 54, the first switch means 56, the fourth switch means 58, and the first sequential A.
A signal is sent to the D converter 67 and the second sequential AD converter 68.

Then, the first switch 52a is opened and the second switch 52a is opened.
Switch 52b is closed, the third switch 54b is opened, the fourth switch 54b is closed, and the fifth switch 56b is closed.
a is opened, the sixth switch 56b is closed, the seventh switch 58a is closed, the eighth switch 58b is opened, the first sequential AD converter 67 is stopped, and the second sequential AD converter 68 is further opened. Start to move.

As a result, the same voltage as that at the plus input terminal 14 appears at the switching terminal 16. Further, the deviation between the second input branch 44 and the third input branch 46 appears at the third terminal 46c.

This deviation is input to the inverting amplifier circuit 72, and the output voltage of the inverting amplifier circuit 72 appears at the eighth terminal 32.

To the substrate input of the second active load element 44b,
The output voltage of the inverting amplifier circuit 72 is applied through the seventh terminal 34b, the second correction operation starts, and the second input branch 4
4 and the third input branch 46 are in equilibrium, and the output voltage of the inverting amplifier circuit 72 at this time is taken into the second sequential AD converter 68.

The first sequential AD converter 67 and the second sequential A
As shown in the graph of FIG. 4, the D converter 68 operates so that the output voltage matches the input voltage in the step of synchronizing with the input clock. When the clock is stopped, the operation is stopped while keeping the output voltage in the state before the stop.

The control circuit 51 alternately outputs the signals described above, and alternately outputs the first input branch 42 and the third input branch 46.
And the second correction operation of the second input branch 44 and the third input branch 46 are repeated. As a result, the first input branch 42 and the second input branch 44 are balanced and the offset voltage of the chopper stabilizing operational amplifier 1 can be removed.

An example of the switch described above is constituted by a field effect transistor, for example.

[0079]

As is apparent from the above description, in the present invention, instead of the first voltage holding capacitor and the second voltage holding capacitor of the conventional chopper stabilizing operational amplifier, the third switch means and the third voltage holding capacitor are provided. 4 switch means, a first sequential AD converter and a second sequential AD converter are provided.

Therefore, by repeating the first correction operation and the second correction operation, the first input branch and the second correction pulse are finally obtained.
The operation to reach the equilibrium state with the input branch can be realized without the voltage holding capacity which is conventionally required.

Further, since the mechanism of voltage storage using the electric charge charged between both ends of the voltage holding capacitor is not used, it is almost unnecessary to consider the voltage change due to the leakage current, and once the equilibrium state is reached, the offset voltage originally intended is obtained. After removing the
No correction operation is required.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a chopper stabilizing operational amplifier according to the present invention.

FIG. 2 is a circuit diagram showing a configuration of a chopper-stabilized operational amplifier in a conventional example.

FIG. 3 is a circuit diagram showing a configuration of a successive A / D converter used in the chopper-stabilized operational amplifier of the present invention.

FIG. 4 is a graph showing a relationship between an input voltage and an output voltage in the successive A / D converter used in the chopper-stabilized operational amplifier of the present invention.

[Explanation of symbols]

 1 Chopper Stabilizing Operational Amplifier 40 Differential Pair Circuit 50 Chop Circuit 67 First Sequential AD Converter 68 Second Sequential AD Converter 51 Control Circuit 72 Inversion Amplifier Circuit 74 Output Buffer Circuit 81 Comparator 82 Control Circuit 83 Successive Comparison Register 84 DA converter

Claims (1)

[Claims] 1. A negative input terminal, a positive input terminal, an output terminal, a positive power supply terminal, a negative power supply terminal, a current supply element, a differential pair circuit, a control circuit, and a chop circuit, A voltage supply element, a first successive A / D converter, and a second
Of the sequential AD converter, the inverting amplifier circuit, and the output buffer circuit, and the differential pair circuit includes a first input branch, a second input branch, and a third input branch. Is
The first active input element and the source are connected to the fourth terminal, the drain is connected to the first terminal, the gate is connected to the negative input terminal, and the substrate electrode is connected to the positive power supply terminal. 5 terminal, the drain is connected to the first terminal, and the gate is the first
And a substrate electrode connected to a sixth terminal and a first active load element. A second input branch has a source connected to the fourth terminal and a drain connected to the second terminal. A gate connected to the positive input terminal and a substrate electrode connected to the positive power supply terminal; and a source connected to the fifth terminal and a drain connected to the second terminal. Connected to the first terminal and the substrate electrode to the seventh terminal and a second active load element, and the third input branch has a source connected to the fourth terminal and a drain connected to the third terminal. The third active input element and the source are connected to the fifth terminal, the drain is connected to the third terminal, the gate is connected to the switching terminal and the substrate electrode is connected to the positive power supply terminal. The gate circuit is composed of a third active load element connected to the first terminal and the substrate electrode is connected to the fifth terminal. The first switch means comprises a first switch means, a second switch means, a third switch means, and a fourth switch means. One of the first switch means is connected to the minus input terminal and the other is connected to the switching terminal. And a second switch, one of which is connected to the plus input terminal and the other of which is connected to the switching terminal. The second switch means has a third switch in which one is connected to the sixth terminal and the other is connected to the eighth terminal. And a fourth switch, one of which is connected to the seventh terminal and the other of which is connected to the eighth terminal, wherein the third switch means has one connected to the sixth terminal and the other to the first AD. A fifth switch connected to the input terminal of the first successive A / D converter of the converter and one to the sixth terminal and the other to the first successive A
A sixth switch connected to the output terminal of the first successive A / D converter of the D converter, and one of the fourth switch means is connected to the seventh terminal and the other is the second switch of the second successive AD converter. Two
From a seventh switch connected to the input terminal of the successive AD converter and an eighth switch, one of which is connected to the seventh terminal and the other of which is connected to the output terminal of the second successive AD converter of the second successive AD converter. The control circuit controls opening / closing of the first switch means, the second switch means, the third switch means, and the fourth switch means, and the inverting amplifier circuit has an input connected to the third terminal and an output connected to the third terminal. The output buffer circuit has an input connected to the second terminal and an output connected to the output terminal, and the current supply element has one connected to the positive power supply terminal and the other connected to the fourth terminal. , The voltage supply element is connected to the negative power supply terminal on one side, and the other side is connected to the fifth terminal, a chopper stabilizing operational amplifier.