JP2857949B2 - Offset voltage compensation circuit for differential amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an offset voltage compensating circuit for a differential amplifier, and more particularly to an offset voltage compensating circuit which can arbitrarily set the output voltage of the differential amplifier during offset compensation.

[0002]

2. Description of the Related Art As a circuit for compensating an offset voltage of a differential amplifier on a chip, a circuit for compensating an offset voltage of an input stage (Japanese Patent Laid-Open No. 56-529932, Japanese Patent Laid-Open No. 2-1).
No. 42214), or an apparatus in which the output voltage of an amplifier is fed back to a non-inverting input terminal to charge an offset voltage to a capacitor (Japanese Patent Application Laid-Open Nos. 58-135467 and 60-1).
No. 42610, JP-A-62-261205) and the like.

[0003]

By the way, circuits having various input threshold voltages are connected to the subsequent stage of the differential amplifier. However, in the conventional offset voltage compensating circuit, the output of the differential amplifier after the compensation is compensated. The reference level of the voltage cannot be set arbitrarily in accordance with the threshold voltage of the subsequent circuit, and the degree of freedom in circuit design is limited.

The present invention has been made to solve the above problem, and provides an offset voltage compensating circuit of a differential amplifier capable of matching a reference level of an output voltage after offset voltage compensation with an input threshold voltage of a subsequent circuit. The purpose is to do.

[0005]

To explain the structure of the present invention, an offset voltage compensating circuit for a differential amplifier according to claim 1 is described.
The path receives the output voltage (Vout) of the differential amplifier
A terminal connected to the inverting input terminal (71) of the differential amplifier
1 input line (W1), and is compared with the output voltage
The input signal is input from outside and the above differential amplifier is non-inverted.
Second input line (W2) connected to input terminal (61)
And short-circuits the first input line and the second input line.
And the inverting input terminal of the differential amplifier and the non-inverting input terminal.
A short-circuit switch (SW1) for making the same potential as the input terminal;
Connected to a node that can change the output voltage of the differential amplifier
Charged capacitors (10, 11) and the capacitors
Charge / discharge switch (SW3 to S
W6) and the output voltage (vout) of the differential amplifier
A comparator (4) that compares the reference voltage with a reference voltage (V +);
Activate the short-circuit switch in response to the compensation start signal.
And based on the comparison signal of the comparator
Make sure that the output signal of the amplifier matches the reference voltage.
Activate the charge / discharge switch, and when a match signal is obtained,
Cancel the operation of the short-circuit switch and charge / discharge switch
A switch control circuit (5).
The circuit enters the second input line immediately before the compensation start signal is input.
After inputting the input signal,
The switch for short-circuit and the
And operating the charge / discharge switch.
You. Further, the offset voltage of the differential amplifier according to claim 2
The compensation circuit is a capacitor connected to the second input line.
And the second input line immediately before the input of the compensation start signal.
After inputting the compensation start signal
Characterized in that it is provided with holding means for temporarily holding
And

[0006] The offset of the differential amplifier according to claim 1
Short-circuit when receiving the compensation start signal
Switch (SW1) is activated and the differential amplifier
The inverting input terminal (71) and the non-inverting input terminal (61)
Both have the same potential as the input signal . At this time, the output of the differential amplifier
Only the offset appears in the force voltage (Vout),
This output voltage (Vout) is referenced by the comparator (4).
The charge and discharge switch is compared with the voltage and based on this comparison signal.
(SW3 to SW6) are activated and the differential amplifier
The output signal is made to match the reference voltage. Moreover, the differential increase
Offset according to the change of the input signal
Even if the reset voltage fluctuates, the switch control circuit
Input to the non-inverting input terminal via the second input line immediately before
The input signal is temporarily restored after the compensation start signal is input.
Switch and the charge / discharge switch
Switches to follow long-term fluctuations in the input signal
Not only can the proper offset voltage compensation and, short
Offset voltage in a stable state with little effect of periodic fluctuations.
Pressure compensation is possible.

[0007]

Embodiment 1 FIG. 1 shows a circuit diagram in Embodiment 1 of the present invention. FIG. 2 shows a circuit diagram of the switch control circuit 5. The differential amplifier 1 is a typical two-stage CMOS comparator circuit. The switches SW1 to SW6 are MOS
Switch. The differential amplifier 1 has signals V- and V
+ Is connected to a pair of signal lines W1 and W2 for input
The following circuit is formed by the lines W1 and W2 and the switching circuit 2.
To achieve. These signal lines W1 and W2 and the switching circuit
Describing the path 2, the input V + is input to one end of a switch SW2 constituting the switching circuit 2, and the other end of the switch SW2 is connected to the gate 61 of the transistor 6, which is the non-inverting input terminal of the differential amplifier 1. . Input V-
Is input to one end of the switch SW1 and the gate 71 of the transistor 7 which is the inverting input terminal of the differential amplifier 1, and the other end of the switch SW1 is connected to the gate 61 of the transistor 6. The differential amplifier 1 is connected to the sources of the transistors 6 and 7 from the power supply VDD via the constant current source 12,
The drain of the transistor 6 is connected to the drain of the transistor 8 and the gates of the transistors 8 and 9.

[0008] The drain of the transistor 7 is connected to the drain of the transistor 9 and the gate of the transistor 14. The drain of the transistor 14 is connected to the constant current source 13, and its voltage is the output voltage Vout. The source of the transistor 14 is connected to the power supply Vss. The output voltage Vout is connected to the non-inverting input terminal of the comparator 4, and the inverting input terminal of the comparator 4 is connected to the reference voltage Vref.

The comparison signal V output from the comparator 4
comp is input to the switch control circuit 5. The transistors 10 and 11 of the offset adjusting circuit 3 are connected in series between the sources of the transistors 8 and 9 of the differential amplifier 1 and the power supply Vss, respectively. Note that it is also possible to connect the transistors 10 and 11 in parallel with the transistors 8 and 9, respectively. The gate of each of the transistors 10 and 11 and the power supply Vss
Between them, capacitors C ₁ and C ₂ are connected, respectively.

A constant voltage source Vrst and a transistor 10,
Switches SW3 and SW5 are connected between the gates of the transistors 11 and 11, respectively.
Between the gates of the switches SW
4, SW6 is connected. The voltage applied to the Vrst terminal is the threshold voltage V of the transistors 10 and 11.
Voltage greater than T, and the voltage applied to the Vsup terminal is
A voltage different from Vrst and a potential difference between Vrst-Vsup cover the region where the channels of the transistors 10 and 11 are turned on as widely as possible (for example, Vrst
= VT +0.1 [V] and Vsup = VDD or Vrst
= VDD and Vsup = Vss). However, Vrst
Switch SW4 depending on which potential of Vsup or
, SW6 change operation.

The capacitance values of the capacitors C ₁ and C ₂ and the resistance 15
Are set such that the time for charging and discharging the capacitors C ₁ and C ₂ from Vrst to Vsup is sufficiently longer than the transmission delay time of the comparator 4 and the switch control circuit 5. Note that the resistor 15 can be replaced with a transistor having the same level of ON resistance instead of the resistor. The reference voltage Vref is the same voltage as the input threshold voltage VT of the subsequent circuit (for example, when an inverter of VT = VDD / 2 is connected to the subsequent stage, Vref =
VDD / 2).

The switch control circuit 5, as shown in FIG.
D-flip-flops (hereinafter referred to as D-FFs) 21 to
23, inverters 24-26, and a NOR gate 27. CSW1 to CSW6 in FIG.
A signal for controlling the opening and closing of W1 to SW6. A reset signal as a compensation start signal controls SW3 and SW5 and is input to an inverter 24. An output of the inverter 24 is input to a reset terminal (RB) of the D-FF 21 and a clock terminal of the D-FFs 22 and 23. Input to (C).

The comparison signal Vcomp is supplied to the inverter 26 and D-
The signal is input to the reset terminal of the FF 23, and the output of the inverter 26 is input to the reset terminal of the D-FF 22. DF
The data terminals (D) of F21 to F23 are connected to the power supply VDD. The output terminal (Q) of the D-FF 21 controls SW2 and inputs it to the inverter 25, and the output of the inverter 25 controls SW1. The outputs of the D-FFs 22 and 23 control the switches SW6 and SW4 respectively,
The signal is input to the NOR gate 27, and the output of the NOR gate 27 is input to the clock terminal of the D-FF 21.

An example of the operation of the compensation circuit is shown in the time chart of FIG. In this example, with respect to V +> V- becomes input, shows a case where the output Vout to the offset voltage is present is set to 0 at time T ₀ in the differential amplifier 1. A voltage of Vsup> Vrst is applied to Vsup and Vrst.

The reference voltage Vref is set to VDD / 2. At time T ₀ , capacitors C ₁ and C ₂ respectively
V ₁ and V ₂ , and the switch S
Portions other than W2 are open, and the differential amplifier 1 operates as a comparator. At time _{T 1,} when the reset signal becomes "HI", closes switch SW3, SW 5 (CSW3, C
SW5 = “HI”) Charge voltage V of capacitors C ₁ and C _{2
c1, V c2} is the same potential Vrst. At the same time, the switch SW2 is opened (CSW2 = “LO”), and the input V + is shut off.
Is done. The switch SW1 is closed (CSW1 = “H
I "), and the gate voltages of the transistors 6 and 7 are the same potential V-
become. Note that the input V- does not change during the offset compensation operation.

If the offset voltage of the differential amplifier 1 is 0, the output Vout becomes VDD / 2, but the output voltage Vout remains 0 and the comparison signal Vc
omp is “LO”. When the reset signal at time T _2, becomes "LO" switch SW3, SW5 open (C
SW3, CSW5 = "LO"). At the same time, D-FF22, 2
3 becomes "HI", but at this point, Vco
Since mp = “LO” and the D-FF 23 is in the reset state, only the output terminal (Q) of the D-FF 22 becomes “HI”, and the switch SW6 closes (CSW6 = “HI”).

The charging voltage Vc ₂ of the capacitor C ₂ gradually increases from Vrst to Vsup. When the offset voltage approaches 0, the output voltage Vout also approaches VDD / 2 and Vou
When t exceeds VDD / 2, the comparison signal Vcomp is inverted to "HI" and the D-FF 22 is reset, so that the switch SW6 is opened (CSW6 = "LO"). NOR gate 2
7 (output terminals of the D-FFs 22 and 23) both become "LO", so that the output of the gate 27 becomes "HI", the output terminal of the D-FF 21 becomes "HI", and the switch SW2 is turned on. Close (CSW2 = "HI"). The output voltage Vout of the differential amplifier 1 becomes the output Vout = VDD corresponding to the relationship between the inputs V + and V- (V +> V-) because the offset voltage is compensated.

The circuit configuration shown in FIGS. 1 and 2 can be easily made monolithic, and can automatically compensate for the offset voltage without using external electronic components. Ma
When the offset voltage is compensated, both terminals 7 of the differential amplifier 1 are
Since the input V− is input to 1, 61, the offset
The pressure compensation is appropriate according to the magnitude of the input V-.
Further, since the reference voltage Vref of the comparator 4 can be arbitrarily changed, offset voltage compensation can be performed by setting Vref = VT even when a circuit having a different input threshold voltage VT is connected to a subsequent stage.

[0019]

Embodiment 2 Comparator 4 to which reference voltage Vref is input
, A simple configuration using a buffer 4 'as shown in FIG. 4 and using the threshold voltage VT of the buffer 4' as a reference voltage may be adopted. Thus, a logic gate or another switching element having a threshold value can be used instead of the comparator.

[0020]

Embodiment 3 In this embodiment, as shown in FIG. 5, and a capacitor C ₅ between the gate of the drain of the transistor 14 of the transistor 7 of the differential amplifier 1, capacitor C ₅
Adjust the offset voltage with the charge amount. Capacitor C ₅
A switch SW3 'is connected to both ends of the
One end of a resistor 15 'is connected to the gate of the switch 4, and a switch SW4' is connected between the other end of the resistor 15 'and VDD, and a switch SW6' is connected between the other end and VSS. The switches SW3 ', SW4', and SW6 'are the switches S of the first embodiment.
Controlled by the same signals as W3, SW4 and SW6,
Resistance and the capacitance value of the capacitor C ₅ of the 'is set in the same manner as the resistor 15 and the capacitor C1, C2 of Example 1.

The switching circuit 2, switch control circuit 5, and comparator 4 are the same as those in the first embodiment, and the operations of the switches SW1, SW2, SW3 ', SW4', and SW6 'are the same as those in the first embodiment. However, the charge amount of the capacitor C ₅ is' to 0 by closing is time T _2, thereafter switch SW4 'switch SW3 at time T _1, or either of the switch SW6' is closed VDD or V,
It will be charged towards SS.

As described above, the offset adjusting circuit 3 can be connected to various nodes of the differential amplifier that can change the output voltage Vout.

[0023]

Embodiment 4 This embodiment shown in FIG. 6 shows a case where the differential amplifier 1 is used as an operational amplifier. Example 1
The difference from FIG. 1 is that the output voltage Vout is input to the gate 71 of the transistor 7 via the switch SW2a, the Vref terminal of the comparator 4 is connected to the gate 61 of the transistor 6, transistor 1 capacitor C ₄ via a switch SW2b for
4 and being connected between the output terminal, the capacitor C ₃ of the input voltage holding gate of the transistor 6 - is that connected to DOO 61, other configuration is the same as FIG.

The switches SW2a and SW2b are connected to the switch SW2.
Are controlled by the same signal as 2, when the reset signal becomes "HI" switch SW2, SW2a, opens SW2b, the feedback loop and a phase compensation capacitor C ₄ is disconnected. The capacitor C ₃ is retained V + terminal voltage immediately before the switch SW2 is opened, at the same time since the switch SW1 is closed, the inverting input terminal voltage of the gate 61, 71 voltage comparator 4 of the transistor 6 becomes V + except, the same as the state at time T ₁ of the first embodiment (see FIG. 3), opening and closing of the switches at time T ₁ after also the same as in example 1.

However, the comparison signal Vcomp is inverted when the output voltage Vout becomes larger than V +, and at time T ₃
Thereafter, the output voltage Vout becomes a voltage substantially equal to V +.
As shown in this embodiment, even when the target value of the output voltage Vout changes when the offset voltage is compensated, the offset compensation can be performed by inputting the target value to the inverting input terminal of the comparator 4.

[0026]

As described above, according to the offset voltage compensating circuit of the present invention, the reference level of the output voltage after offset voltage compensation can be arbitrarily set, so that the degree of freedom in circuit design can be increased. .

[Brief description of the drawings]

FIG. 1 is an overall circuit diagram of an offset voltage compensation circuit according to a first embodiment.

FIG. 2 is a circuit diagram of a switch control circuit.

FIG. 3 is a signal time chart.

FIG. 4 is an overall circuit diagram of an offset voltage compensation circuit according to a second embodiment.

FIG. 5 is an overall circuit diagram of an offset voltage compensation circuit according to a third embodiment.

FIG. 6 is an overall circuit diagram of an offset voltage compensation circuit according to a fourth embodiment.

[Explanation of symbols]

1 differential amplifier 2 switching circuit 3 offset adjusting circuit 4 comparator 5 switch control circuit 61 a non-inverting input terminal 71 an inverting input terminal C _{1, C} 2, _{C 5} capacitors SW1, SW2 shorting switch SW3, SW4, SW5, SW6, SW3 ', SW4
', SW6' charge / discharge switch W1, W2 signal line

Claims (2)

(57) [Claims] An output voltage of a differential amplifier is input and
A first input line connected to the inverting input terminal of the differential amplifier,
And the input signal to be compared with the output voltage
The second input line connected to the non-inverting input terminal of the differential amplifier and the first input line and the second input line are short-circuited ,
And the inverting input terminal of the differential amplifier and the non-inverting input terminal and the switch shorting the same potential and eggplant, a capacitor connected to a node that can change the output voltage of the differential amplifier, the charging source the capacitor or A charge / discharge switch connected to a discharge power source; a comparator for comparing the output voltage of the differential amplifier with a reference voltage; receiving the compensation start signal to activate the short-circuit switch; actuated the discharge switch as allowed to coincide with the reference voltage output signal of the dynamic amplifier, and a switch control circuit to eliminate the actuation of the switch and the charge and discharge switching the short circuit at the time to obtain a coincidence signal, the switch Control circuit
Is input to the second input line immediately before the input of the compensation start signal.
After inputting the compensation start signal,
Hold the switch for short-circuit and
An offset voltage compensating circuit for a differential amplifier, wherein the charge / discharge switch is operated . 2. A capacitor connected to the second input line.
And the second input immediately before the input of the compensation start signal.
The input signal input to the line to the compensation start signal input
2. A holding means for temporarily holding the sheet afterward.
An offset voltage compensating circuit for a differential amplifier as described in the above.