JP3506561B2 - Output circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit which outputs an analog level, and more particularly to an output circuit which is used for a multi-grayscale LCD source driver for driving a liquid crystal panel and has a high speed operation.

[0002]

2. Description of the Related Art The output portion of a conventional TFT type multi-tone LCD source driver has a structure as shown in FIG.

FIG. 7 shows an output circuit of a TFT type multi-gradation LCD source driver. In FIG. 7, an output circuit 1 is an operational amplifier (Amp1) and capacitors (capacitances) C1 and C.
2, a switch SW1 to SW6, and a load Z.

The output circuit 1 includes switches SW1 to W6.
A predetermined level is output by controlling.

8 to 15 show the output circuit 1 of FIG.
FIG. 17 is a circuit diagram showing an operation when switches SW1 to SW6 are turned on / off at the timing shown in FIG. FIG. 17 is a circuit diagram for each timing, which is represented by a short circuit when the switches SW1 to SW6 are in the ON state at the timings shown in FIG. 16 and is open when the switches are in the OFF state.

FIG. 16 shows a switch S of the output circuit 1 of FIG.
7 is a timing chart showing ON / OFF timings of W1 to SW6, and it is assumed that each switch is turned on at a “H” level and turned off at a “L” level. In the figure, A to H correspond to the circuit operations of FIGS. 8 to 15, respectively.

The operation of the output circuit 1 will be described with reference to FIGS.

In the section A of FIG. 16, the output circuit 1 of FIG.
SW1, SW4, SW6 are ON, SW2, SW
Since SW3 and SW5 are in the OFF state, the circuit A is shown in FIG.

In the circuit A, the level input to the level input terminal LIN is inverted / amplified C2 / C1 times by Amp1 centered on the reference potential VP and output to drive the load Z.

Next, in the section B of FIG. 16, SW6 is turned off from the state of the section A to become the circuit B of FIG. 9, and the load Z is disconnected in preparation for the output of the next level.

In the section C of FIG. 16, SW1 changes to the OFF state and SW2 and SW3 change to the ON state from the state of the section B to become the circuit C of FIG.

In the circuit C, a voltage follower connection for returning the Amp1 output to the-input is provided for compensating the offset of the Amp1. By this connection, both ends of the capacitor C1 are short-circuited, the charge charged in the capacitor C1 starts to be discharged, and the terminal side to which the input level of the capacitor C2 was applied is connected to the reference potential VP to thereby connect the capacitor C2. The electric charge that had been charged to the battery also begins to discharge. The discharge in the capacitors C1 and C2 is performed in the section C of FIG.

Next, in the section D of FIG. 16, SW4 is changed to the OFF state and SW5 is changed to the ON state from the state of the section C, and the circuit D of FIG. 11 is obtained.

In the circuit D, the offset voltage of the operational amplifier Amp1 is connected to the capacitance C by the voltage follower connection.
1 and the capacity C2 are stored once. The capacitance C1 and the capacitance C
The offset voltage stored in 2 is added to the voltage input to the level input terminal LIN at the next output.

In the circuit D, the offset voltage stored in the capacitors C1 and C2 is added to the-input of the operational amplifier Amp1, and at the next output, the operational amplifier Amp1 is centered around the accurate reference potential VP having no offset amount. Thus, the level obtained by inverting and amplifying the input value by C2 / C1 times is output. At the same time, an input level for the next output level is created by a circuit (not shown).

In order to operate as described above, the capacitance C1,
It is necessary to wait for the time in the section D for the time when the charge corresponding to the offset voltage is accumulated in C2.

After that, the state E shown in FIG.
SW3 changes to the OFF state from the state in the section of
The circuit E becomes and the feedback is released.

Next, the state of F shown in FIG. 16 is entered, and SW4 is turned on and SW5 is turned off from the state of section E, and the circuit F of FIG. 13 is obtained.

Then, the state of G shown in FIG.
SW1 changes to the ON state and SW2 changes to the OFF state from the state of the section, the circuit G of FIG. 14 is obtained, and the level input to the level input terminal LIN with the load Z disconnected is centered around the reference potential VP Amp1. Is output after being inverted and amplified by C2 / C1 times.

Then, the state of H shown in FIG.
SW6 changes from the state of the section to the ON state, the circuit H of FIG. 15 is obtained, the load Z and the output of the operational amplifier Amp1 are connected to the load Z, and the level input to the level input terminal LIN is centered on the reference potential VP. Amp1 to C2 / C
The load Z is driven at a level that is inverted and amplified by a factor of 1.

At this time, conventionally, a circuit as shown in FIG. 17 is used for the circuit of the operational amplifier Amp1.

FIG. 17 is a circuit diagram showing the configuration of the operational amplifier Amp1.

In FIG. 17, the operational amplifier Amp1 is
Ρ channel MOS transistor (hereinafter referred to as PMOS) 11 that receives − input to the gate electrode and + to the gate electrode
N-channel MOS current-mirror connected to the drain electrodes of the PMOS 12 and the PMOSs 11 and 12 for receiving the input
Transistors (hereinafter referred to as NMOS) 13, 14,
N receiving the source electrode potential of the NMOS 14 at the gate electrode
It is composed of a MOS 15, a phase compensation capacitor (capacitance) C3, and constant current sources I1 and I2.

The capacitor (capacitance) C3 is a capacitance for phase compensation, and the phase compensation capacitance C3 can be adjusted so that the operational amplifier does not oscillate.

[0025]

By the way, in such a conventional output circuit 1, the capacitance C3 of the operational amplifier Amp1 is provided.
Can be adjusted so that the operational amplifier does not oscillate.

Generally, the heavier the load Z, the larger the value of the phase compensation capacitance C3, and the speed of the operational amplifier Amp1 tends to be slower.

In this case, the speed of the operational amplifier Amp1 is slowed down because it is necessary to make adjustment so that it will not oscillate even when the load Z is connected, and the offset voltage stored in the above-mentioned capacitors C1 and C2 is the operational amplifier. A
A is added to the-input of mp1 and is centered around an accurate reference potential VP that does not have the offset amount of the operational amplifier Amp1.
mp1 requires a long time in the section D (FIG. 16) in which the input value is inverted and amplified by C2 / C1 times.

As described above, Am is centered on the accurate reference potential VP having no offset amount of the operational amplifier Amp1.
Since there is a time for inverting and amplifying the input value (time in the section D) due to p1, there is a drawback that there is a limit in operating the output circuit at high speed.

It is an object of the present invention to provide an output circuit which can shorten the time in the section D and can operate at high speed.

[0030]

Means for Solving the Problems] output circuit according to the present invention includes a differential stage, an output stage for amplifying the differential stage output, and a phase compensating means for performing phase compensation of the differential stage and the output stage Performance
It includes a calculation amplifier, the output circuit load that could be connected to the output side, the phase compensation means, capacitance is formed by the phase compensating capacitance can be changed.

Further, the phase compensating means may change the capacity of the phase compensating capacity to a small value at a predetermined timing to speed up the operation of the operational amplifier, and the phase compensating means comprises a plurality of phase compensating capacitors. Alternatively, the capacitors may be connected in parallel and a predetermined capacitor may be selected from the plurality of capacitors for phase compensation to change the capacitor.

Further, the phase compensating means may be provided with a means for discharging the capacitance, and the offset amount of the output may be reduced by discharging the non-selected capacitance. It is also possible to provide a means for charging at a level and reduce the output offset amount by charging a non-selected capacitance at a predetermined level.

The output circuit according to the present invention includes a differential stage,
In an output circuit including an operational amplifier having a current source for supplying a current value to an output stage, a means for changing the current amount of the current source is provided, and the current amount of the current source is increased at a predetermined timing to speed up the operation of the operational amplifier. To configure.

The current source may be provided with a constant current transistor, and the amount of current may be changed by changing the voltage level applied to the gate voltage of the constant current transistor. A constant current transistor may be provided, and one or more of the plurality of constant current transistors may be used in combination to change the gate width of the transistor to change the amount of current.

Further, the output circuit is provided with a plurality of switches between the input / output terminal of the operational amplifier, the input terminal and the output terminal, and outputs the analog level by switching the plurality of switches in a predetermined order. Further, at least the first capacitor is provided between the input terminal and the output terminal of the operational amplifier, and the second capacitor is provided at the input terminal, and the first and second capacitors are connected by a plurality of switches. The offset amount may be removed by changing the state.

[0036]

BEST MODE FOR CARRYING OUT THE INVENTION The output circuit according to the present invention is a TFT.
The present invention can be applied to an operational amplifier that outputs an analog level such as a multi-tone LCD source driver for driving a liquid crystal panel.

FIG. 1 is a circuit diagram showing an operational amplifier circuit of the output circuit according to the first embodiment of the present invention. In explaining the output circuit according to the present embodiment, the same components as those of the output circuit shown in FIG. The same reference numerals are attached.

In FIG. 1, an operational amplifier circuit 20 (operational amplifier) has a gate electrode receiving negative input to a MOS1.
1. PMOS 12, PMO receiving + input to the gate electrode
Connected in parallel with the NMOS 13 and 14, which are current-mirror connected to the drain electrodes of S11 and 12, the NMOS 15 whose gate electrode receives the source electrode potential of the NMOS 14, the first phase compensation capacitance C3, and the first phase compensation capacitance C3. Second phase compensation capacitor C4, second phase compensation capacitor C
4, an analog switch ASW1 connected in series, an inverter INV1 for inverting the voltage applied to one control terminal of the analog switch ASW1, and a constant current source I1,
I2. The control input CIN is input to the control terminal of the analog switch ASW1.

The PMOS 11, 12, the NMOS 13,
14 and the constant current source I1 constitute a comparator 21 (differential stage) for comparing − input and + input as a whole, and the NMOS 15
The constant current source I2 constitutes a buffer unit 22 (output stage) that amplifies the output of the comparator 21. Also, the analog switch ASW1 and the inverter INV1 for controlling the first phase compensation capacitance C3, the second phase compensation capacitances C4, C4.
Constitute the phase compensating means 23 as a whole.

That is, the operational amplifier circuit 20 of the output circuit according to this embodiment has a comparator 21 and a buffer section 22.
And a phase compensating means 23 in which a second phase compensating capacitor C4 and a second phase compensating capacitor C4 configured by connecting the second phase compensating capacitor C4 and the analog switch ASW1 in series are connected in parallel to the first phase compensating capacitor C3. It is composed of and.

The output circuit portion other than the operational amplifier circuit 20 is the same as the output circuit shown in FIG.

The operation of the output circuit configured as described above will be described below.

The circuit portion of the output circuit other than the operational amplifier circuit 20 is the same as that of FIG. 7, and its operation will be described with reference to the circuit diagrams of FIGS. 8 to 15 and the timing chart of FIG. The description of the operation is omitted.

In the state of the circuit A of FIG. 8, in the present embodiment, the analog switch ASW1 of the operational amplifier circuit 20 of FIG. 1 is turned on. Analog switch ASW1
Is in the ON state, the comparator 21 and the buffer unit 22 are in a state of being connected by the first phase compensation capacitance C3 and the second phase compensation capacitance C4, and the phase compensation capacitance is C3 +.
It becomes C4. Since the phase compensating capacitance is C3 + C4, phase compensation can be performed even with a heavy load.

Next, the circuit B state shown in FIG. 9 and the circuit C state shown in FIG. 10 are the analog switch ASW1.
The operation is the same as that of the conventional example except that is ON. That is, in the section B of FIG. 16, from the state of the section A to S
W6 is turned off and the circuit B shown in FIG. 9 is set, and the load Z is disconnected in preparation for the output of the next level. In the section C of FIG. 16, SW1 is in the OFF state from the state of the section B, and SW
2, SW3 changes to the ON state, and the circuit C in FIG. 10 is obtained. In the circuit C, both ends of the capacitance C1 are short-circuited to make the capacitance C1
The electric charge charged to the capacitor C2 starts to be discharged, and the electric charge charged to the capacitor C2 also starts to be discharged by connecting the terminal side to which the input level of the capacitor C2 is applied with the reference potential VP.

Then, the circuit D shown in FIG. 11 is obtained, and the charges corresponding to the offset voltage are accumulated in the capacitors C1 and C2 as in the conventional example.

Here, the analog switch ASW1 is turned off.
The F state is set, and only the capacitance C3 is used as the phase compensation capacitance. At this time, since the load Z is disconnected, the load is in a light state, and thus the phase is compensated. Therefore, the operational speed of the operational amplifier circuit 20 is high as described in the conventional example. Therefore, the time required for the charges corresponding to the offset voltage to be stored in the capacitors C1 and C2, that is, the offset voltage stored in the capacitors C1 and C2 is added to the-input of the operational amplifier circuit 20, and the operational amplifier circuit is obtained. Accurate reference potential VP without offset amount of 20
It is possible to shorten the time of the section of D in which the input value is inverted and amplified with respect to

Thereafter, the state E shown in FIG. 16 is entered, and the SW3 changes from the state in the section D to the OFF state,
The circuit E shown in FIG. 12 is obtained, and the feedback is canceled.

The analog switch ASW1 shown in FIG. 1 is turned off after the E state and before the F state, and the phase compensation capacitance is ready for the next output even with a heavy load of C3 + C4. To

In the F and G states shown in FIG. 16, the level input to the level input terminal LIN with the load Z disconnected is multiplied by C2 / C1 by the operational amplifier circuit 20 with the reference potential VP as the center. It is inverted, amplified and output.

After that, the H state shown in FIG. 16 is entered, the SW6 changes from the state in the G section to the ON state, and the circuit H in FIG.
Is connected to the load Z, and the level input to the level input terminal LIN drives the load Z at a level that is inverted and amplified by C2 / C1 times by the operational amplifier circuit 20 around the reference potential VP.

As described above, the operational amplifier circuit 20 of the output circuit according to the first embodiment has the PMOSs 11 and 1.
2, a comparator 21 including the NMOSs 13 and 14 and the constant current source I1, a buffer unit 22 including the NMOS 15 and the constant current source I2 for amplifying the output of the comparator 21, a first phase compensating capacitor C3, and a second phase Analog switch ASW1 and inverter INV1 for controlling the compensation capacitors C4, C4
And a phase compensating means 23 including
Is a plurality of phase compensation capacitors C3 and C4 connected in parallel,
At the above-mentioned operation timing, the plurality of phase compensating capacitors C3,
Since the capacitance for phase compensation is reduced by disconnecting the capacitance C4 from C4, the time required for accumulating charges corresponding to the offset voltage in the capacitances C1 and C2, that is, the capacitance C1 and the capacitance C2, The stored offset voltage is added to the-input of the operational amplifier circuit 20, and the input value is inverted and amplified around the accurate reference potential VP having no offset amount of the operational amplifier circuit D.
The period of time (see FIG. 16) can be shortened, and the output circuit can be operated at high speed.

Therefore, it is suitable for use in a linear driver circuit required to operate at high speed, for example, a multi-tone LCD source driver for driving a TFT type liquid crystal panel.

FIG. 2 is a circuit diagram showing the configuration of the operational amplifier circuit of the output circuit according to the second embodiment of the present invention.
The same components as those of the output circuit shown in FIG.

In FIG. 2, the operational amplifier circuit 30 includes an ΡMOS 11 that receives a − input to its gate electrode, a PMOS 12 that receives a + input to its gate electrode, and an NMOS 13 that is current-mirror connected to the drain electrodes of the PMOS 11 and 12.
14, an NMOS 15 whose gate electrode receives the source electrode potential of the NMOS 14, a first phase compensation capacitance C3, a second phase compensation capacitance C4 connected in parallel with the first phase compensation capacitance C3, and a second phase A first analog switch ASW1 connected in series to the compensation capacitor C4, a second analog switch ASW2 connected in parallel to the capacitor C4 so as to bypass the second phase compensation capacitor C4, and analog switches ASW1 and ASW2. An inverter INV1 that inverts the voltage applied to one control terminal of the
1, I2. Analog switch ASW1,
A control input CIN is input to the control terminal of ASW2.

The PMOS 11, 12, the NMOS 13,
14 and the constant current source I1 constitute a comparator 21 (differential stage) for comparing − input and + input as a whole, and the NMOS 15
The constant current source I2 constitutes a buffer unit 22 (output stage) that amplifies the output of the comparator 21. Further, the analog switch ASW2 and the inverter INV1 that discharge the electric charges of the analog switches ASW1 and C4 that control the first phase compensation capacitor C3 and the second phase compensation capacitors C4 and C4 constitute the phase compensation means 31 as a whole. To do.

That is, the operational amplifier circuit 30 of the output circuit according to the present embodiment has a comparator 21 and a buffer section 22.
And a second phase compensating capacitor C4, which is configured by connecting the second phase compensating capacitor C4 and the analog switch ASW1 in series to the first phase compensating capacitor C3, and further connected in parallel. The phase compensating means 31 is configured to discharge the electric charge of the second phase compensating capacitor C4 when the phase compensating capacitor C4 is not used.

The output circuit portion other than the operational amplifier circuit 30 is the same as the output circuit shown in FIG.

The operation of the output circuit configured as described above will be described below.

The circuit portion of the output circuit other than the operational amplifier circuit 30 is similar to that of FIG. 7, and its operation will be described with reference to the circuit diagrams of FIGS. 8 to 15 and the timing chart of FIG. The description of the operation of the same parts as those of the above embodiment will be omitted.

In the first embodiment, after the D state shown in FIG. 11, the analog switch ASW1 is turned on to set the value of the phase compensation capacitance to the capacitance C3, and after the E state shown in FIG. 12, the F state is set. Before that, the analog switch ASW1 shown in FIG. 1 was turned off, and the phase compensation capacitor was ready for phase compensation even with a heavy load of C3 + C4 in preparation for the next output.

On the other hand, in the second embodiment, as shown in FIG. 2, the analog switch ASW1 is turned on and the analog switch ASW2 is turned off at the same time.
At the same time that the analog switch ASW1 is turned off, the analog switch ASW2 is turned on and the capacitance C
Since it is configured to discharge the electric charge charged in 4, the timing for turning off the analog switch ASW1 is not limited to the F state after the E state, but before the H state. If there is no problem.

As described above, the operational amplifier circuit 30 of the output circuit according to the second embodiment has the second phase compensation capacitance C4.
The phase compensating means 31 is configured to discharge the electric charge of C4 when not used, and the output offset amount is reduced by discharging the separated capacitor C4.

Therefore, when the capacitance C4 is charged when the analog switch ASW1 is turned on, the potential variation of the node of FIG. Analog switch ASW with the feedback of the operational amplifier in state E turned off
Although it was necessary to prevent the output from being affected by turning 1 on, this embodiment has a configuration in which the operational amplifier circuit 30 is made to operate at high speed and the charge stored in the capacitor C4 is discharged. , Set the phase compensation capacitance value to C3 + C4 so that it can handle a heavy load.
I try not to have any problems before the situation.

FIG. 3 is a circuit diagram showing the configuration of the operational amplifier circuit of the output circuit according to the third embodiment of the present invention.
The same components as those of the output circuit shown in FIG.

In FIG. 3, the operational amplifier circuit 40 includes an ΡMOS 11 that receives a − input to its gate electrode, a PMOS 12 that receives a + input to its gate electrode, and an NMOS 13 that is current-mirror connected to the drain electrodes of the PMOS 11 and 12.
14, an NMOS 15 whose gate electrode receives the source electrode potential of the NMOS 14, a first phase compensation capacitance C3, a second phase compensation capacitance C4 connected in parallel with the first phase compensation capacitance C3, and a second phase When the first analog switch ASW1 connected in series to the compensation capacitor C4, the second analog switch ASW2 connected to one end of the second phase compensation capacitor C4, and the second phase compensation capacitor C4 are not used , An inverter INV that inverts the voltage applied to one of the control terminals of the voltage follower-connected operational amplifier circuit 41 and analog switches ASW1 and ASW2 that charges the second phase compensation capacitor C4 to a predetermined potential.
1 and constant current sources I1 and I2. The control input CIN is input to the control terminals of the analog switches ASW1 and ASW2.

The PMOS 11, 12, the NMOS 13,
14 and the constant current source I1 constitute a comparator 21 (differential stage) for comparing − input and + input as a whole, and the NMOS 15
The constant current source I2 constitutes a buffer unit 22 (output stage) that amplifies the output of the comparator 21. Also, the analog switches ASW1 and CSW that control the first phase compensation capacitor C3, the second phase compensation capacitor C4, and the operational amplifier circuits 41 and C4.
The analog switch ASW2 and the inverter INV1 which discharge the electric charge of 4 constitute the phase compensating means 42 as a whole.

That is, the operational amplifier circuit 40 of the output circuit according to the present embodiment has a comparator 21 and a buffer section 22.
And a second phase compensating capacitor C4, which is configured by connecting the second phase compensating capacitor C4 and the analog switch ASW1 in series to the first phase compensating capacitor C3, and further connected in parallel. The phase compensating means 42 uses an operational amplifier circuit 41 configured to charge the electric charge of the second phase compensating capacitor C4 to a predetermined potential when the phase compensating capacitor C4 is not used.

The output circuit portion other than the operational amplifier circuit 41 is the same as the output circuit shown in FIG.

The operation of the output circuit configured as described above will be described below.

The operation of the output circuit according to this embodiment is substantially the same as that of the first and second embodiments, and only different parts will be described.

In the second embodiment, as shown in FIG. 2, the analog switch ASW1 is turned on, the analog switch ASW2 is turned off at the same time, and the analog switch ASW1 is turned off and the analog switch ASW2 is turned on at the same time. With the configuration in which the electric charge charged in the capacitor C4 is discharged, the timing of turning off the analog switch ASW1 is not limited to the F state after the E state, but before the H state. However, if the analog switch ASW1 is turned on in the second embodiment, the potentials of the node of FIG. 2B and the node of FIG. 2A are originally different. The potential of the node in FIG. 2A slightly changes.

In order to solve this, in the present embodiment, as shown in FIG. 3, when the analog switch ASW1 is turned off, the separated second phase compensation capacitor C4 is used.
Is charged using the operational amplifier circuit 41 to the electric charge that was originally charged when it was not disconnected.

By doing so, even if the analog switch ASW1 is turned on, the electric charges do not move, and therefore the potentials of both nodes in FIGS. 3A and 3B do not fluctuate, which is excellent. An analog output level is obtained.

FIG. 4 is a circuit diagram showing the configuration of the operational amplifier circuit of the output circuit according to the fourth embodiment of the present invention.
The same components as those of the output circuit shown in FIG.

In FIG. 4, an operational amplifier circuit 50 includes an ΡMOS 11 that receives a − input to its gate electrode, a PMOS 12 that receives a + input to its gate electrode, and an NMOS 13 that is current-mirror connected to the drain electrodes of the PMOSs 11 and 12.
14, a NMOS 15 whose gate electrode receives the source electrode potential of the NMOS 14, a first phase compensating capacitor C3, and PMOS 51 and 52 which are current sources whose output current changes according to the reference potential Vc input to the gate electrode.
The reference potential Vc generated by a reference potential generation circuit (not shown) is supplied to the gate electrodes of the current source PMOSs 51 and 52.

The PMOS 11, 12, the NMOS 13,
14 and the current source PMOS 51 constitute a comparator 53 (differential stage) for comparing − input and + input as a whole, and NM
The OS 15 and the current source PMOS 52 form a buffer unit 54 (output stage) that amplifies the output of the comparator 53, and
The first phase compensation capacitor C3 constitutes the phase compensation means 55.

That is, the operational amplifier circuit 50 of the output circuit according to this embodiment has a comparator 53 and a buffer section 54.
And the phase compensating means 5 including the first phase compensating capacitor C3.
In order to make the driving capability of the comparator 53 and the buffer unit 54 variable, the potential level input to the gate electrodes of the transistors PMOS51 and 52 forming the current source is changed. .

The operation of the output circuit configured as described above will be described below.

The operation of the output circuit according to this embodiment is substantially the same as that of the first embodiment, and only different parts will be described.

In the first embodiment, as shown in FIG. 1, the analog switch ASW1 is controlled by the control input CIN to make the phase compensation capacitance variable, and the operational speed of the operational amplifier circuit 20 is made high only when the load is light. But
In the present embodiment, the current sources, which are part of the components of the comparator 51 and the buffer unit 54 and control the driving capability, are the current source PMOSs 51 and 52 whose supply current is variable by the reference potential Vc.
Is used to change the level and increase the current value of the current source at the timing when the operational amplifier circuit 50 is desired to operate at high speed. The timing to operate at high speed is the same as in the case of the first embodiment.

Thus, in this embodiment, the comparator 5
3. Transistors 51 and 52 that form the current source with the ability of the current source that controls the driving ability of the components of the buffer unit 54
This is achieved by varying the level input to the gate electrode of and changing the speed of the operational amplifier. As a result, the same effect as that of the first embodiment can be obtained.

FIG. 5 is a circuit diagram showing the configuration of the operational amplifier circuit of the output circuit according to the fifth embodiment of the present invention.
The same components as those of the fourth embodiment shown in FIG.

In FIG. 5, an operational amplifier circuit 60 includes an ΡMOS 11 that receives a − input to its gate electrode, a PMOS 12 that receives a + input to its gate electrode, and an NMOS 13 that is current-mirror connected to the drain electrodes of the PMOS 11 and 12.
14, the NMOS 15 receiving the source electrode potential of the NMOS 14 at its gate electrode, the first phase compensating capacitor C3, the current source PMOS 61, 62, PMOS 63, 64 serving as a current source whose transistor width is changed when selectively used. It is composed of analog switches ASW3 to ASW6 for switching the source PMOSs 62 and 64 to select / non-select, and an inverter INV2 for inverting the voltage applied to one control terminal of the analog switches ASW3 to ASW6. The reference potential Vc generated by a reference potential generation circuit (not shown) is supplied to the gate electrodes of the current source PMOSs 61 and 63, and the gate electrodes of the current source PMOSs 62 and 64 are connected via the analog switches ASW3 and ASW5. The reference potential Vc is supplied.

The PMOSs 11, 12 and the NMOS 13,
14 and the current source PMOS 61, 62 as a whole-
A comparator 65 (differential stage) that compares the input and the + input is configured, and the NMOS 15 and the current source PMOSs 63 and 64 are
The buffer unit 66 (output stage) that amplifies the output of the comparator 65 is configured, and the first phase compensation capacitance C3 configures the phase compensation unit 67.

That is, the operational amplifier circuit 60 of the output circuit according to the present embodiment has a comparator 65 and a buffer section 66.
And the phase compensating means 6 including the first phase compensating capacitor C3.
In order to make the driving capability of the comparator 65 and the buffer unit 66 variable, the widths of the current source PMOSs 61, 62, PMOS 63, 64, which are current sources, are set by the analog switches ASW3 to ASW6. The configuration is such that the selection / non-selection is switched and changed.

The operation of the output circuit configured as above will be described below.

The operation of the output circuit according to the present embodiment is substantially the same as that of the fourth embodiment, and only different parts will be described.

In the fourth embodiment, as shown in FIG. 4, the driving capability of controlling the current source PMOS 51, 52 whose supply current is variable by the reference potential Vc is changed to change the operation speed of the operational amplifier circuit 50. However, in the present embodiment, the capability of the current source that is a part of the components of the comparator 65 and the buffer unit 66 and that controls the driving capability is set to the width of the transistor that creates the current source. , The operational amplifier is operated at high speed by changing the combination of the transistors used.

In this way, the comparator 65 and the buffer unit 66 are
The same effect as the first embodiment can be obtained by changing the speed of the operational amplifier circuit 60 by changing the widths of the transistors 61 to 64 forming the current source so that the ability of the current source that controls the driving ability of the component of FIG. Obtainable.

Needless to say, the number of transistors for the current source, the type of gate width of the transistors, and the number and types of switches for switching or combining the transistors are not limited to those in the above embodiment.

FIG. 6 is a circuit diagram showing the configuration of the operational amplifier circuit of the output circuit according to the sixth embodiment of the present invention.
9 is an example in which the Ρ channel transistor and the N channel transistor in the first embodiment shown in FIG.

In FIG. 6, an operational amplifier circuit 70 includes an NMOS 71 which receives a − input to its gate electrode, an NMOS 72 which receives a + input to its gate electrode, and a PMOS 73, which is current mirror connected to the drain electrodes of the PMOS 71 and 72.
74, a PMOS 75 whose gate electrode receives the drain electrode potential of the PMOS 74, a first phase compensation capacitance C5, a first
Second phase compensation capacitance C6 connected in parallel with the phase compensation capacitance C5, and analog switch ASW7 and analog switch A connected in series with the second phase compensation capacitance C6.
It is composed of an inverter INV3 that inverts the voltage applied to one control terminal of SW7, and constant current sources I3 and I4. The control input CIN is input to the control terminal of the analog switch ASW7.

As described above, the operational amplifier circuit 70 includes the first
The N-channel transistor and the N-channel transistor in the above embodiment are configured in reverse, and the operation is the first.
This is exactly the same as the case of the above embodiment, and the same effect can be obtained.

Here, the present embodiment is an example in which the transistor in the first embodiment is constructed in reverse, but it goes without saying that there are derived examples in which the transistor in each of the above-described embodiments is constructed in reverse.

The output circuit according to each of the above-described embodiments can be applied to an output circuit used for addition and subtraction of analog signals, etc. However, in the output circuit in which the current values of the differential stage and the output stage have current sources. It goes without saying that the present invention can be applied to any integrated circuit device, or can be applied to an output circuit incorporated and used inside the integrated circuit device. For example, it is suitable to be applied to a switched capacitor integrated circuit, an analog signal processing circuit, and the like.

Further, in the output circuit according to each of the above-mentioned embodiments, although it is formed on the integrated circuit by MOS or the like, the MO
Of course, it is not limited to S.

Further, the output circuit according to each of the above embodiments may have any configuration as long as it has an operational amplifier circuit, and the number of transistors, analog switches, capacitors, etc., connection state, etc. are the same as in each of the above embodiments. Not limited.

[0099]

The output circuit according to the present invention comprises a differential stage, an output stage for amplifying the output of the differential stage, and a phase compensating means for compensating the phase of the differential stage and the output stage. In the output circuit including the operational amplifier to which the load can be connected, the phase compensating means is composed of the phase compensating capacitor whose capacity can be changed. Therefore, the accurate reference potential without the offset amount of the operational amplifier is centered. It is possible to shorten the period of time during which the input value is inverted and amplified, and the output circuit can be operated at high speed.

The output circuit according to the present invention includes a differential stage,
In an output circuit including an operational amplifier having a current source for supplying a current value to an output stage, a means for changing the current amount of the current source is provided, and the current amount of the current source is increased at a predetermined timing to speed up the operation of the operational amplifier. Therefore, it is possible to shorten the period of time during which the input value is inverted and amplified around the accurate reference potential that does not have the offset amount of the operational amplifier, and the output circuit operates at high speed. be able to.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an operational amplifier circuit of an output circuit according to a first embodiment to which the present invention is applied.

FIG. 2 is a circuit diagram showing a configuration of an operational amplifier circuit of an output circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of an operational amplifier circuit of an output circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of an operational amplifier circuit of an output circuit according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of an operational amplifier circuit of an output circuit according to a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of an operational amplifier circuit of an output circuit according to a sixth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of an output circuit of a conventional TFT type multi-tone LCD source driver.

FIG. 8 is a diagram for explaining the operation of a conventional output circuit.

FIG. 9 is a diagram for explaining the operation of a conventional output circuit.

FIG. 10 is a diagram for explaining the operation of a conventional output circuit.

FIG. 11 is a diagram for explaining the operation of a conventional output circuit.

FIG. 12 is a diagram for explaining the operation of a conventional output circuit.

FIG. 13 is a diagram for explaining the operation of the conventional output circuit.

FIG. 14 is a diagram for explaining the operation of a conventional output circuit.

FIG. 15 is a diagram for explaining the operation of the conventional output circuit.

FIG. 16 is a timing chart for explaining the operation of the conventional output circuit.

FIG. 17 is a circuit diagram showing a configuration of an operational amplifier circuit of a conventional output circuit.

[Explanation of symbols]

11, 12, 73, 74, 75 Ρ MOS, 13, 1
4,15,71,72 NMOS, 20,30,40,4
1, 50, 60, 70 Operational amplifier circuit (operational amplifier) 21, 53, 65 Comparator (differential stage), 22, 5
4, 66 buffer section (output stage), 23, 31, 42,
55,67 phase compensation means, 51,52 current source transistor, C3 first phase compensation capacitance, C4 second phase compensation capacitance, ASW1 to ASW7 analog switches, INV1 to INV3 inverters, I1 to I4 constant current sources , CIN control input

Continuation of front page (56) Reference JP-A-1-235403 (JP, A) JP-A-62-274916 (JP, A) JP-A-6-291576 (JP, A) JP-A-6-291574 (JP , A) JP-A 7-221567 (JP, A) JP-A 8-32386 (JP, A) JP-A 4-356816 (JP, A) JP-A 58-35670 (JP, A) JP-A 5-243857 (JP, A) JP-A-2-78308 (JP, A) JP-A-9-27722 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03F 3/45 H03K 19/0175 H04N 5/66 102

Claims (8)

(57) [Claims] 1. An operational amplifier having a differential stage, an output stage for amplifying the output of the differential stage, and a phase compensating means for compensating the phase of the differential stage and the output stage, and a load on the output side. in but output circuit that could be connected, said phase compensating means, by connecting a plurality of phase compensating capacitor in parallel, to change the capacity by selecting a predetermined volume from the phase compensating capacitance of the plurality of further, An output circuit comprising means for charging a capacitance at a predetermined level, and reducing an output offset amount by charging the non-selected capacitance at a predetermined level. 2. The phase compensating means is provided between the differential stage and the output stage and is connected to the differential stage.
A first capacitive element connected to the output stage;
A second capacitive element connected in parallel with the first capacitive element;
A first circuit for controlling electrical connection between the differential stage and the second capacitive element;
1 switch to select the predetermined capacity and capacity
And an operational amplifier circuit whose input is connected to the differential stage and the operational amplifier circuit.
Control the electrical connection between the output of the width circuit and the second capacitive element
A second switch for controlling the non-selected capacitance to a predetermined value.
2. The charging according to claim 1, wherein
Output circuit. 3. The first and second switches are analog
The output according to claim 2, wherein the output is a log switch.
Force circuit. 4. The first and second differential stages each have a constant current source and a source electrode connected to the constant current source.
Second MOS transistor and drain electrodes of the first and second MOS transistors
And a current mirror circuit connected to
The output circuit according to claim 1, wherein: 5. The first and second MOS transistors
Is a PMOS transistor
The output circuit according to item 4. 6. The current mirror circuit is connected to the drain electrode of the first MOS transistor.
Drain electrode and gate electrode, and a reference voltage is applied.
Third MOS transistor having a source electrode
And connected to the drain electrode of the second MOS transistor.
Of the drain electrode and the third MOS transistor
The gate electrode connected to the gate electrode and the reference voltage are
Fourth MOS transistor having a source electrode applied
2. The structure according to claim 1, wherein
Output circuit. 7. The third and fourth MOS transistors
Is an NMOS transistor
The output circuit according to item 4. 8. The output stage is connected to the drain electrode of the fourth MOS transistor.
Gate electrode connected to the first and second capacitance elements
Drain electrode and a saw to which the reference voltage is applied.
A fifth MOS transistor having a drain electrode and a drain electrode of the fifth MOS transistor.
And a second constant current source
The output circuit according to claim 6, further comprising: