JP3108941B2 - Operational amplifier circuit - Google Patents
Operational amplifier circuitInfo
- Publication number
- JP3108941B2 JP3108941B2 JP03196729A JP19672991A JP3108941B2 JP 3108941 B2 JP3108941 B2 JP 3108941B2 JP 03196729 A JP03196729 A JP 03196729A JP 19672991 A JP19672991 A JP 19672991A JP 3108941 B2 JP3108941 B2 JP 3108941B2
- Authority
- JP
- Japan
- Prior art keywords
- amplifier circuit
- inverting amplifier
- output
- inverting
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【産業上の利用分野】本発明は演算増幅回路のオフセッ
ト調整に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to offset adjustment of an operational amplifier circuit.
【０００２】[0002]
【従来の技術】従来の演算増幅回路のオフセット調整を
図２に示す。１はアナログ入力信号端子であり正転増幅
回路２と、反転増幅回路３の入力である。正転増幅回路
２と、反転増幅回路３の出力４，５は外部回路に接続し
ている。反転増幅回路のプラス入力はアナログ・グラン
ド１２に抵抗２０（Ｒ２０），２１（Ｒ２１）を介して
接続している。抵抗２０，２１の分割点は高抵抗２２
（Ｒ２２）を介し外部出力端子２３となる。外部出力端
子２３は、外部外付け可変抵抗２６（Ｒ２６），２７
（Ｒ２７）で電源間２４（ＶＣＣ），２５（−ＶＣＣ）
を分割された点と接続する。図２に於ける抵抗２０，２
１，２２，２６，２７により差動増幅回路３のプラス入
力に与えられるバイアス電位Ｖは、電源電圧を＋ＶＣ
Ｃ，−ＶＣＣとすると以下で表される。2. Description of the Related Art FIG. 2 shows an offset adjustment of a conventional operational amplifier circuit. Reference numeral 1 denotes an analog input signal terminal which is an input of the non-inverting amplifier 2 and the inverting amplifier 3. The outputs 4 and 5 of the non-inverting amplifier 2 and the inverting amplifier 3 are connected to an external circuit. The plus input of the inverting amplifier circuit is connected to the analog ground 12 via resistors 20 (R20) and 21 (R21). The dividing point of the resistors 20 and 21 is a high resistance 22
It becomes the external output terminal 23 via (R22). The external output terminal 23 is connected to an external external variable resistor 26 (R26), 27
(R27) between power supplies 24 (VCC), 25 (-VCC)
Is connected to the divided points. Resistors 20 and 2 in FIG.
The bias potential V applied to the positive input of the differential amplifier circuit 3 by the power supply voltage + VC
If C and -VCC are used, they are expressed as follows.
【０００３】 Ｖ＝（Ｒ２７−Ｒ２６）＊Ｒ２１＊ＶＣＣ／（Ｒ２６＊ＲＡ ＋Ｒ２７＊ＲＡ＋Ｒ２６＊Ｒ２７） （但し ＲＡ＝Ｒ２１＋Ｒ２２）上記式に於て抵抗２
６（Ｒ２６）と抵抗２７が等しい時、前記差動増幅回路
のプラス入力電圧は、０ボルトとなりアナログ・グラン
ド電位となる。ＶＣＣを１２Ｖとし、 又各抵抗を Ｒ２７＋Ｒ２６＝１００Ｋ Ｒ２２＝１Ｍ Ｒ２１＝２０Ｋ とすることにより、差動増幅回路３のオフセット電圧は
±２４０ｍＶ変化することができ抵抗２６，２７を調整
することによりオフセット調整をおこなっていた。[0005] V = (R27-R26) * R21 * VCC / (R26 * RA + R27 * RA + R26 * R27) (where RA = R21 + R22)
When 6 (R26) is equal to the resistance 27, the positive input voltage of the differential amplifier circuit becomes 0 volt, which is the analog ground potential. By setting VCC to 12 V and setting each resistor to R27 + R26 = 100K R22 = 1M R21 = 20K, the offset voltage of the differential amplifier circuit 3 can be changed by ± 240 mV, and the offset is adjusted by adjusting the resistors 26 and 27. I was doing.
【０００４】[0004]
【発明が解決しようとする課題】しかし、前述の従来技
術では外付け抵抗２６，２７に於て出力レベルを正転増
幅，反転増幅レベルを等しくする為手で可変抵抗を調整
をしなければならないという問題点を有する。However, in the above-mentioned prior art, the variable resistors must be adjusted by hand in order to equalize the output levels of the external resistors 26 and 27 in the forward and reverse amplification levels. There is a problem that.
【０００５】そこで本発明はこのような問題点を解決す
るもので、その目的とするところは外付け部品なし無調
整で正転，反転増幅回路の出力レベル間のオフセットを
キャンセルする演算増幅回路を提供するところにある。SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve such a problem, and an object of the present invention is to provide an operational amplifier circuit for canceling an offset between output levels of a normal rotation and inversion amplifier circuit without external components and without adjustment. To provide.
【０００６】[0006]
【課題を解決するための手段】本発明の演算増幅回路
は、アナログ入力信号を差動増幅回路を用い正転増幅、
及び反転増幅する演算増幅回路において、アナログ入力
信号がアナロググランドとなる非動作時には、前記反転
増幅回路のプラス入力はアナロググランドレベルに接続
され、直列接続した等しい容量の２つのコンデンサの両
端に前記正転増幅回路の出力と前記反転増幅回路の出力
を接続する手段を有し、前記アナログ入力信号が所定レ
ベルとなる動作時に、前記直列接続された２つのコンデ
ンサーの中間点を前記反転増幅回路のプラス入力に接続
する手段を有し、前記反転増幅回路の出力が非動作時に
接続された前記２つのコンデンサの一端をアナロググラ
ンドレベルに接続する手段を有することを特徴とする。SUMMARY OF THE INVENTION An operational amplifier circuit according to the present invention comprises a non-inverting amplifier for converting an analog input signal using a differential amplifier circuit.
In the operational amplifier circuit for inverting amplification, when the analog input signal is not operating at analog ground, the positive input of the inverting amplifier circuit is connected to the analog ground level, and the positive terminal is connected to both ends of two capacitors of the same capacitance connected in series. Means for connecting the output of the inverting amplifier circuit to the output of the inverting amplifier circuit. When the analog input signal is at a predetermined level, an intermediate point between the two capacitors connected in series is added to the inverting amplifier circuit. The circuit has a means for connecting to an input, and means for connecting one end of the two capacitors connected when the output of the inverting amplifier circuit is not operating to an analog ground level.
【０００７】[0007]
【作用】本発明の上記の構成によれば、非動作時におい
てオフセット分（Ｖｏｆｆ）をコンデンサーに蓄え、相
等しいコンデンサーが２つ直列接続になっているため動
作時、反転増幅器に帰還する電位を直列接続されたコン
デンサーの一端をアナログ・グランドとし、コンデンサ
ーの中間点から取っている為、オフセット差の１／２を
帰還することにより正転増幅，反転増幅出力レベル間の
オフセットを自動でキャンセルすることが可能となる。According to the above configuration of the present invention, the offset (Voff) is stored in the capacitor during non-operation, and since two equal capacitors are connected in series, the potential fed back to the inverting amplifier during operation is reduced. One end of the capacitor connected in series is used as an analog ground and is taken from the middle point of the capacitor. Therefore, the offset between the forward amplification output and the inverted amplification output level is automatically canceled by feeding back half of the offset difference. It becomes possible.
【０００８】[0008]
【実施例】図１は本発明の実施例における回路図であ
る。入力アナログ信号１は、正転増幅回路２と反転増幅
回路３に接続している。正転増幅回路の出力４及び反転
増幅回路の出力５は出力として半導体集積回路の出力に
電気的に接続する一方、非動作時、直列接続した相等し
いコンデンサー７，８の一端に各々接続するスイッチア
レイ６の入力となる。非動作時に入力アナログ信号はア
ナログ・グランドレベルを入力すると共に反転増幅回路
のプラス入力は、スイッチ１１を通しアナログ・グラン
ド１２に接続する。。このとき理想的には正転増幅回路
２と反転増幅回路３の出力４，５はアナログ・グランド
レベルになる。しかし増幅回路に使用している差動増幅
回路のオフセット電圧が有るため出力は等しくはならな
い。ここで正転増幅回路の差動増幅回路オフセットをＶ
１，反転増幅回路の差動増幅回路オフセットをＶ２とす
ると各々の出力４，５の出力Ｖ４，Ｖ５は Ｖ４＝Ｖ１ ， Ｖ５＝２＊Ｖ２ となり、正転増幅，反転増幅の出力電圧差（Ｖｏｆｆ）
は Ｖｏｆｆ＝Ｖ４−Ｖ５＝Ｖ１−２＊Ｖ２ となる。よって、相等しい容量（Ｃ）の直列接続したコ
ンデンサーに蓄えられる電荷量Ｑは、 Ｑ＝１／２＊Ｃ＊Ｖｏｆｆ である。コンデンサー７，８の中間点は動作時にスイッ
チ１１を介し反転増幅回路のプラス入力に接続する。非
動作時において反転増幅回路出力に接続していたコンデ
ンサー８の一端はスイッチ１０を介しアナログ・グラン
ド１２に接続する。このときコンデンサー７，８の中間
点の一端の電位（Ｖ８）は、 Ｖ８＝１／２＊Ｖｏｆｆ となる。ここで、動作時に於て反転増幅回路のプラス入
力が １／２＊Ｖｏｆｆとなることによりアナログ入力
レベルがアナログ・グランド（０ｖ）のとき反転増幅回
路３の出力電圧Ｖ５は、 Ｖ５＝２＊（Ｖ２＋１／２＊Ｖｏｆｆ） ＝２＊（Ｖ２＋１／２＊（Ｖ１−２＊Ｖ２）） ＝Ｖ１ となる。このときの反転増幅回路の出力Ｖ５と正転増幅
器の出力Ｖ４は互いにＶ１となり相等しくなる。よって
入力アナログ信号に対する正転，反転出力のアナログ・
グランド電位は入力アナログ・グランド電位に対しオフ
セットを持つが正転，反転出力間のオフセットは、０ｖ
となる。FIG. 1 is a circuit diagram of an embodiment of the present invention. The input analog signal 1 is connected to a non-inverting amplifier circuit 2 and an inverting amplifier circuit 3. The output 4 of the non-inverting amplifier and the output 5 of the inverting amplifier are electrically connected as outputs to the output of the semiconductor integrated circuit, and are connected to one end of the series-connected equal capacitors 7 and 8 when not operating. It is the input of array 6. During non-operation, the input analog signal receives the analog ground level and the plus input of the inverting amplifier circuit is connected to the analog ground 12 through the switch 11. . At this time, ideally, the outputs 4 and 5 of the non-inverting amplifier 2 and the inverting amplifier 3 are at the analog ground level. However, the outputs are not equal because of the offset voltage of the differential amplifier circuit used in the amplifier circuit. Here, the differential amplifier offset of the non-inverting amplifier is set to V
Assuming that the offset of the differential amplifier circuit of the inverting amplifier circuit is V2, the outputs V4 and V5 of the outputs 4 and 5 are V4 = V1, V5 = 2 * V2, and the output voltage difference between the forward amplification and the inversion amplification (Voff) )
Is Voff = V4-V5 = V1-2 * V2. Therefore, the charge amount Q stored in the series-connected capacitors having the same capacity (C) is Q = １ ／ * C * Voff. The midpoint of the capacitors 7, 8 is connected to the positive input of the inverting amplifier circuit via the switch 11 during operation. One end of the capacitor 8 connected to the output of the inverting amplifier circuit during non-operation is connected to the analog ground 12 via the switch 10. At this time, the potential (V8) at one end of the intermediate point between the capacitors 7 and 8 becomes V8 = 1/2 * Voff. Here, when the plus input of the inverting amplifier becomes 1/2 * Voff during operation, the output voltage V5 of the inverting amplifier 3 when the analog input level is analog ground (0v) is V5 = 2 * ( V2 + 1/2 * Voff) = 2 * (V2 + 1/2 * (V1-2 * V2)) = V1. At this time, the output V5 of the inverting amplifier circuit and the output V4 of the non-inverting amplifier become V1 and become equal to each other. Therefore, the normal and inverted output analog
The ground potential has an offset with respect to the input analog ground potential, but the offset between the normal rotation and the inverted output is 0 V
Becomes
【０００９】[0009]
【発明の効果】以上述べたように、本発明によれば、非
動作時に正転、反転増幅回路のオフセット電圧をコンデ
ンサーに蓄え、動作時に１/２にし、反転増幅器のプラ
ス入力に接続することにより、正転、反転増幅回路の出
力オフセット電圧をキャンセルするという効果を有す
る。また、オフセット・キャンセルとして追加する回路
は2個の相等しいコンデンサーと数個のスイッチである
ため半導体集積回路に取り組むことが容易であり外付け
部品なしで安価にオフセット・キャンセルを実現できる
という効果を奏する。As described above, according to the present invention, the offset voltage of the non-inverting and inverting amplifying circuit is stored in the capacitor during non-operation, is reduced to 1/2 during operation, and is connected to the positive input of the inverting amplifier. As a result, there is an effect that the output offset voltage of the normal rotation and inversion amplification circuit is canceled. Also, since the circuit to be added as offset cancellation is two equal capacitors and several switches, it is easy to work on a semiconductor integrated circuit, and the effect that offset cancellation can be realized at low cost without external components is achieved. Play.
【図１】本発明の演算増幅回路の１実施例を示す回路
図。FIG. 1 is a circuit diagram showing one embodiment of an operational amplifier circuit according to the present invention.
【図２】従来の演算増幅回路を示す回路図。FIG. 2 is a circuit diagram showing a conventional operational amplifier circuit.
１・・・・・・・・・・・・・・・・アナログ入力信号 ２・・・・・・・・・・・・・・・・正転増幅回路 ３・・・・・・・・・・・・・・・・反転増幅回路 ４・・・・・・・・・・・・・・・・正転増幅回路出力 ５・・・・・・・・・・・・・・・・反転増幅回路出力 ６，１０，１１ ・・・・・・・・・スイッチ ７，８ ・・・・・・・・・・・・・等容量コンデンサ
ー １２ ・・・・・・・・・・・・・アナログ・グラン
ド ２０，２１，２２，２６，２７ ・・調整用抵抗1 ···································································· ······················································ Inverting amplifier circuit output 6, 10, 11 ... Switch 7, 8 ... Equal capacity capacitor 12 ... ..Analog ground 20, 21, 22, 26, 27
Claims (1)
正転増幅、及び反転増幅する演算増幅回路において、ア
ナログ入力信号がアナロググランドレベルとなる非動作
時には、前記反転増幅回路のプラス入力はアナロググラ
ンドレベルに接続され、直列接続した等しい容量の２つ
のコンデンサの両端に前記正転増幅回路の出力と前記反
転増幅回路の出力を接続する手段を有し、前記アナログ
入力信号が所定レベルとなる動作時に、前記直列接続さ
れた２つのコンデンサーの中間点を前記反転増幅回路の
プラス入力に接続する手段を有し、前記反転増幅回路の
出力が非動作時に接続された前記２つのコンデンサの一
端をアナロググランドレベルに接続する手段を有するこ
とを特徴とする演算増幅回路。1. An operational amplifying circuit for amplifying and inverting an analog input signal using a differential amplifier circuit in a non-inverting mode and an inverting mode. Means for connecting the output of the non-inverting amplifier circuit and the output of the inverting amplifier circuit to both ends of two capacitors of the same capacity connected in series and connected in series, wherein the analog input signal is at a predetermined level Sometimes, there is means for connecting an intermediate point between the two capacitors connected in series to a positive input of the inverting amplifier circuit, and one end of the two capacitors connected when the output of the inverting amplifier circuit is not operating is analog. An operational amplifier circuit having means for connecting to a ground level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03196729A JP3108941B2 (en) | 1991-08-06 | 1991-08-06 | Operational amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP03196729A JP3108941B2 (en) | 1991-08-06 | 1991-08-06 | Operational amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0541616A JPH0541616A (en) | 1993-02-19 |
| JP3108941B2 true JP3108941B2 (en) | 2000-11-13 |
Family
ID=16362624
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP03196729A Expired - Fee Related JP3108941B2 (en) | 1991-08-06 | 1991-08-06 | Operational amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3108941B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001292041A (en) * | 2000-04-07 | 2001-10-19 | Fujitsu Ltd | Operational amplifier and its offset cancellation circuit |
| JP4821364B2 (en) * | 2006-02-24 | 2011-11-24 | 日本電気株式会社 | Offset cancel amplifier, display device using the same, and offset cancel amplifier control method |
| JP4928339B2 (en) * | 2007-04-26 | 2012-05-09 | 株式会社アドバンテスト | Arbitrary waveform generator |
-
1991
- 1991-08-06 JP JP03196729A patent/JP3108941B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0541616A (en) | 1993-02-19 |
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