JP2009077184A - Camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a camera which has a simple structure and can constantly perform a clamp processing at a proper OB clamp level. <P>SOLUTION: When an image signal from an imaging device is output, a first output mode and a second output mode which have different clamp levels each other can be switched. When the first output mode is switched to the second output mode, the clamp level is changed within a predetermined period of time. Accordingly, the camera can reach a normal clamp level after the predetermined period of time even the output mode is switched, and thus, the image quality can be maintained. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a camera that performs a clamping process for clamping an image signal from an image sensor.

  In a conventional camera, particularly a digital camera, for example, an analog video signal output from an image sensor is given to a clamp circuit through a correlated double sampling process by a CDS circuit, and the clamp process is performed. The clamped analog video signal is output to the A / D converter, converted into a digital signal, and input to the signal processing circuit.

  In the above-described clamping process, in order to always maintain the offset voltage (DC component) of the analog video signal at a constant level, a dark current is detected from the optical black portion formed in the image sensor, and the optical black is based on the signal level. The potential of the portion is fixed, and processing for setting (clamping) the reference black signal level (OB clamp level) is performed. By doing so, in the signal processing in the signal processing circuit, R, G, and B signals that are three color signals are generated on the basis of the OB clamp level, and gain adjustment and the like are performed on the three color signals. When performing signal processing such as conversion into U, V and V signals, the processing can be performed without being affected by dark current.

As described above, the analog signal output of the image sensor is converted into a digital signal using an A / D converter, and the video camera signal is subjected to subsequent signal processing. In particular, the offset voltage of the analog video signal before A / D conversion is set. Patent Document 1 discloses a clamp circuit that keeps constant.
JP 2001-169188 A [H04N 5/335]

  In the clamp circuit of the prior art 1 described in Patent Document 1, a capacitor for charging / discharging and a bias capacitor for determining an offset are separated and independent, and an alternate operation is performed by time-division for each line. It is possible to obtain a stable video signal that is not affected by charging and discharging of the clamping capacitor within the period.

  However, in this clamp circuit configuration, since two capacitors and a plurality of switching switches must be prepared, the circuit becomes complicated and the cost increases.

  In a digital camera, for example, (1) control of an analog video signal output from an image sensor, when recording a still image in an external memory or the like, and when outputting a through image to a display at a predetermined frame rate, Or (2) the number of bits of the digital signal in A / D conversion is controlled.

  In (1), when a digital camera records a still image in an external memory or the like, all the pixels included in the image sensor of the digital camera are read (all pixel output mode), and a through image is displayed on the finder or the like at a predetermined frame rate. When outputting to a device, the pixels included in the image sensor are mixed on the image sensor and output (pixel addition output mode).

  In the all-pixel output mode, since all the pixels are read, the OB clamp level in the clamp process is a level for one pixel. However, since pixels are added and read in the pixel addition output mode, the OB clamp level in the clamp processing is a level obtained by adding the number of added pixels.

  Now, when the pixel addition output mode is switched to the all pixel output mode, the OB clamp level in the clamp processing must also be changed to a level corresponding to one pixel from the level added for the number of pixels. However, when shifting from the 4-pixel addition output mode shown in FIG. 15 to the all-pixel output mode, the output mode is switched to the desired OB clamp level from the relationship of the time constant when adjusting the OB clamp level in the clamp processing. There is a period in which the OB clamp level cannot be reached within a predetermined period and the OB clamp level is not normal, and the OB clamp level is not appropriate locally or entirely in the image. As a result, black sinking or the like occurs in the lower part of the still image, and the image quality deteriorates.

  In (2), when the digital camera reads all pixels from the image sensor and records a still image in an external memory or the like with an A / D converter, and when outputting a through image at a predetermined frame rate, It changes the dynamic range and outputs a digital signal with a different number of bits.

  When the mode is switched between a still image capturing mode for recording a still image in an external memory or the like and a through image mode for outputting a through image to a display device at a predetermined frame rate, an OB clamp level for clamp processing is determined. In the control circuit, since the digital signal output from the filter unit that does not operate normally due to the change in the number of bits in the previous stage of the control circuit is input, the OB clamp level changes as shown in FIG. 16, and reset processing is performed. A period that does not become normal occurs. As a result, black sinking or the like occurs in the entire through image, and the quality of the image deteriorates.

  As in (1) and (2), the prior art 1 does not disclose any optimization of the OB clamp level when the mode is switched.

  The present invention solves the above-described problems, and provides a camera that can always perform a clamp process at an appropriate OB clamp level with a simple configuration.

  The camera of claim 1 outputs an image signal from a plurality of pixels in which an optical black area and an effective area are formed adjacent to each other according to a plurality of output modes including a first output mode and a second output mode. The first clamp level is detected based on the optical black area of the first image signal output in the first output mode, and the first image signal is clamped with the first clamp level as the reference black level. The second clamp level is detected based on the first clamp means and the optical black area of the second image signal output in the second output mode, and the second clamp level is set as a reference black level for the second image signal. A second clamping means for performing a clamping process; a mode switching means for switching between the first output mode and the second output mode; and a second output mode from the first output mode by the switching means. When switched to de, characterized in that it comprises a control means for performing control for the time required for the level change for changing the reference black level from the first clamp level to the second clamp level within a predetermined time period.

  According to this, when the first output mode is switched to the second output mode, the first clamp level is changed to the second clamp level within a predetermined period. Therefore, even after the output mode is switched, after the predetermined period. Reaches the normal clamp level. Therefore, the image quality can be maintained.

  The camera of claim 2 according to claim 1 is characterized in that, in the level change in the control means, a reset process for lowering the first clamp level below a predetermined level is performed and then the second clamp level is changed.

  According to this, when the output mode is changed, the first clamp level becomes lower than the predetermined level, so that the time to reach the second clamp level can be shortened.

  4. The camera according to claim 3, wherein the first clamp level and the second clamp level are levels based on a register value, and the clamp processing reduces an analog signal in which the register value is converted into an analog video signal. It is characterized by.

  According to this, the first clamp level and the second clamp level are adjusted by the register value, and the clamp process is performed by reducing the analog video signal by the analog signal based on the register value. Therefore, the clamp process can be performed with a simple configuration. Can be executed.

  5. The camera according to claim 4, wherein the first clamp level and the second clamp level are levels based on a charge amount due to charging / discharging of the capacitor, and the clamp processing reduces a charge amount held by the capacitor in the image signal. It is characterized by making it.

  According to this, the first clamp level and the second clamp level are adjusted by the capacitor, and the clamp process is performed by reducing the amount of charge held by the capacitor. Therefore, the clamp process can be executed with a simple configuration.

  According to a fourth aspect of the present invention, in the camera according to the fifth aspect, the reset process at the first clamp level discharges so that the charge amount of the capacitor becomes lower than a threshold value.

  According to this, since the charge amount of the capacitor becomes lower than the threshold value, the charge amount corresponding to the second clamp level is charged, so that the time to reach the second clamp level can be shortened with a simple configuration. Can do.

  The camera according to claim 6, wherein the predetermined period is a vertical blanking period when the image sensor outputs an image signal.

  According to another aspect of the camera of the present invention, an image sensor that outputs an analog video signal from a plurality of pixels formed by adjoining an optical black area and an effective area, and a first bit that performs a first A / D conversion process on the analog video signal. First A / D conversion means for outputting a number of first digital image signals; and second A / D conversion means for performing a second A / D conversion process on the analog video signal and outputting a second digital image signal having a second number of bits. Switching means for switching between the first A / D conversion process and the second A / D conversion process, and a digital black signal corresponding to a specific pixel in the optical black area in the first digital image signal and the second digital image signal. A digital filter that performs the filtering process and a clamp level based on the digital black signal that has been subjected to the filtering process is used as a reference black level for the analog video signal. And clamping means for performing pump process, the first 1A / D conversion process and the 2A / D conversion processing is switched by the switching means, characterized in that it comprises an initialization means for performing an initialization process to the digital filter.

  According to this, in the filtering process of the digital black signal in the digital filter, if the number of bits of the input digital black signal is changed, the initialization process is performed, so that it operates normally. Therefore, an appropriate clamp level can always be maintained.

  The camera according to claim 8, which is dependent on claim 7, further includes a reset process for resetting the clamp level when the initialization process is performed in the clamp means.

  The camera according to claim 9, which is dependent on claim 8, is characterized in that the clamping means includes a register, and the reset processing sets the value of the register to zero.

  According to the camera of the present invention, it is possible to always perform the clamping process at an appropriate OB clamp level with a simple configuration.

  Hereinafter, embodiments of the present invention applied to a digital camera will be described in detail with reference to the drawings.

First Embodiment FIGS. 1 and 2 are block diagrams of a digital camera 10 according to a first embodiment. The digital camera 10 includes an optical lens 12 and a diaphragm 14. Adjustment of the movement of the optical lens 12 and the diaphragm 14 is performed by the motor driving unit 50. However, the motor drive unit 50 is composed of two motors (not shown) that adjust the optical lens 12 and the diaphragm 14 separately.

  The optical image of the subject is formed on the light receiving surface of the CCD imager 16 that is an image pickup element by the optical lens 12 through the diaphragm 14. A primary color filter shown in FIG. 3 is mounted on the light receiving surface of the CCD imager 16, and light having any one primary color component is irradiated to a photodiode which is a part constituting the CCD imager 16. In the photodiode, photoelectric conversion is performed, and a charge signal accumulated according to light intensity and time is various pulse waveforms necessary for driving the CCD imager 16 generated by the timing generator (TG) 18. An analog imaging signal is output in accordance with the charge readout pulse, vertical transfer pulse, and horizontal transfer pulse. The timing generator (TG) 18 generates a clamp pulse and supplies it to the clamp circuit 30 included in the AFE circuit 20.

  In the first embodiment, there are two modes for reading out pixels from the CCD imager 16 when outputting an analog video signal from the CCD imager 16, which will be described in detail later.

  As shown in FIG. 2, the AFE circuit 20 includes a CDS circuit 22, an AGC circuit 24, a subtractor 26, an A / D converter 28, and a clamp circuit 30. The clamp circuit 30 includes a digital filter circuit 30a, a control circuit 30b, a D / A converter 30c, and a switch SW1. The analog imaging signal output from the CCD imager 16 is subjected to correlated double sampling processing by the CDS circuit 22 and gain adjustment is performed by the AGC circuit 24. Then, the clamp circuit 30 performs clamp processing on the analog video signal in response to the clamp pulse output from the TG 18. The analog image signal that has undergone the clamping process is converted into a digital signal by the A / D converter 28. The digital signal is subjected to various signal processing by the signal processing circuit 32, converted into Y, U, and V signals and temporarily stored in the SDRAM 36. The digital signal stored in the SDRAM 36 is subjected to JPEG compression processing by the image compression / expansion processing unit 38 under the control of the CPU 34 and converted into compressed image data. Under the control of the CPU 34, the card control unit 40 controls the external card memory card 42 to record compressed image data.

  The digital signal once stored in the SDRAM 36 is converted into an analog video signal by the D / A converter 44 under the control of the CPU 34, converted into an NTSC signal by the video encoder 46, and displayed on the display 48 as a through image. The

  The operation unit 52 is connected to the CPU 34 and includes a shutter button (not shown). When the shutter button is pressed, an image capturing operation for starting still image capturing and moving image capturing can be performed. In addition, when capturing a still image or a moving image, it is necessary to set the imaging mode of the digital camera, but the imaging mode can be switched by operating an imaging mode setting button (not shown) of the operation unit 52. It is. The operation unit 52 includes a power button (not shown), and the digital camera 10 is turned on and off when pressed. When the power is turned on, a through image is displayed on the display 48 while the imaging operation is not performed, regardless of the mode state of the still image capturing mode or the moving image capturing mode.

  In the first embodiment, there are two modes for reading out pixels from the CCD imager 16 when outputting an analog video signal from the CCD imager 16. In the first mode, when a still image or the like is acquired, all the pixels formed in the CCD imager 16 are read as shown in FIG.

  In the second mode, when a through image is displayed on the display device 48, two pixels of the same color filter are added in the vertical direction on the CCD imager 16, as shown in FIG. The output is performed in a 4-pixel addition output mode in which two identical color filter pixels are read out in the direction. In this case, the signal level is four times and the S / N is one time. The operation in the 4-pixel addition output mode is omitted because it is described in detail in, for example, technical data of Sony CCD area image sensor ICX629AQF, which is a product of Sony Corporation.

  An effective area and an optical black area (OB area) are formed on the light receiving surface of the CCD imager 16 as shown in FIG. The effective area is formed at the center of the light receiving surface, and the optical black area is formed around the light receiving surface. For this reason, the analog video signal output from the CCD imager 16 also has an optical black component.

  Here, clamp processing when still image capturing is performed will be described in detail with reference to FIG. When the user presses the shutter button of the operation unit 52, the optical lens 12 and the aperture 14 are adjusted as described above, and an optical image of the subject is formed on the light receiving surface of the CCD imager 16. The charge generated by the photodiode is read out to the vertical transfer register by the charge read pulse output from the timing generator (TG) 18. The read charges are transferred in the vertical direction by the vertical transfer pulse output from the timing generator (TG) 18. The TG 18 also outputs a horizontal transfer pulse every time a charge for one horizontal line is supplied from each vertical transfer register to the horizontal transfer register. The horizontal transfer register transfers charges for one horizontal line in the horizontal direction in response to such a horizontal transfer pulse. The horizontally transferred charge is output to the outside as an analog video signal (all pixel output mode). At this time, as can be seen from FIG. 3, the charge corresponding to the pixels in the clamp area is first output to the outside as an analog video signal, and then the charge corresponding to the pixels in the effective area is output to the outside as an analog video signal. .

  Further, the switch SW1 is switched so as to connect the A / D converter 28 and the digital filter circuit 30a at the timing when the analog video signal is output from the CCD imager 16 by the clamp pulse generated by the timing generator (TG) 18. . In the CDS circuit 22, the analog black signal corresponding to the pixel in the clamp area is subjected to correlated double sampling processing, the gain is adjusted in the AGC circuit 24, and input to the A / D converter 28 via the subtractor 26. The analog black signal is converted by the A / D converter 28 and input to the digital filter circuit 30a as a digital black signal. The digital filter circuit 30a removes the level value of invalid pixels such as defective pixels in the digital black signal. The digital black signal filtered by the digital filter circuit 30a is input to the control circuit 30b, the OB clamp level is digitally accumulated in the register 30d in the control circuit 30b, and averaged for one pixel, and is D / A converted. To the device 30c. The D / A converter 30c converts the OB clamp level output from the control circuit 30b into an analog signal. By subtracting the above-mentioned analog signal from the analog image signal in the effective area output from the AGC circuit 24, the clamp process is performed, and then the signal is input to the signal processing unit 32 via the A / D converter 28. Signal processing is performed.

  The accumulation and averaging of the OB clamp level performed by the control circuit 30b is performed by outputting an analog video signal corresponding to the optical black area A shown in FIG. 3 from the CCD imager 16 according to the time constant based on the control circuit 30b. This is done during the vertical blanking period.

  Next, clamp processing when a through image is output to the display 48 will be described in detail with reference to FIG.

  When the power button of the operation unit 52 is pressed by the user, the CPU 34 detects that the button is pressed, and the register 30d in the control circuit 30b of the clamp circuit 30 is reset under the control of the CPU 34.

  When an optical image of the subject is formed on the light receiving surface of the CCD imager 16, the charge generated by the photodiode is shown in FIG. 4B by the charge read pulse output from the timing generator (TG) 18. Thus, for example, the charges of the two photodiodes in the first and third rows with the color filter R are read out to the vertical transfer register. The read charges are transferred in the vertical direction by the vertical transfer pulse output from the timing generator (TG) 18, and the two charges in the first vertical row are added by the horizontal transfer register, and the third vertical row is added. Two charges are added. Then, in response to the horizontal transfer pulse from the TG 18, when the charges for one horizontal line are transferred in the horizontal direction, the added charges in the first and third rows are added. That is, one pixel is generated by adding the charges of four pixels. Therefore, the signal level is 4 times and the S / N is 1 time. Such pixel addition processing is similarly performed on the charges of the photodiodes to which the color filters G and B are added, and these charges are transferred in the horizontal direction. The horizontally transferred charge is output to the outside as an analog video signal (4-pixel addition output mode).

  Similar to the description of the all-pixel output mode, an analog black signal is generated, and the OB clamp level based thereon is different depending on the 4-pixel addition output mode and the all-pixel output mode as shown in FIG. In the 4-pixel addition output mode, since the signal level is four times that of the all-pixel output mode, the OB clamp level is also four times.

  Therefore, the OB clamp level, which is four times the signal level compared with the all-pixel output mode, is digitally stored in the register 30d in the control circuit 30b, averaged for four pixels, and sent to the D / A converter 30c. Output. The D / A converter 30c converts the OB clamp level output from the control circuit 30b into an analog signal. By subtracting the above-mentioned analog signal from the analog video signal in the effective area output from the AGC circuit 24, the clamp process is performed and then the signal is input to the signal processing unit 32 via the A / D converter 28. Signal processing is performed.

  The accumulation and averaging of the OB clamp level performed by the control circuit 30b is performed by outputting an analog video signal corresponding to the optical black area A shown in FIG. 3 from the CCD imager 16 according to the time constant based on the control circuit 30b. This is done during the vertical blanking period.

  Now, referring to FIG. 6, when a through image is being output to the display 48, that is, when the CCD imager 16 is performing a 4-pixel addition process and outputting it (4-pixel addition output mode). A case where the shutter button of the operation unit 52 is pressed and the process is switched to the process of outputting all pixels (all pixel addition output mode) will be described.

  When the shutter button of the operation unit 52 is pressed, the CPU 34 detects that the shutter button of the operation unit 52 is pressed, and the register 30d in the control circuit 30b of the clamp circuit 30 is reset by the control of the CPU 34. Then, the clamping process in the all-pixel output mode as described above is performed.

  As shown in FIG. 6, the OB clamp level when switching from the 4-pixel addition output mode to the all-pixel output mode is zero. Then, the OB clamp level in the all-pixel output mode is reached according to the time constant based on the control circuit 30b. Since the OB clamp level in the all-pixel output mode is lower than the OB clamp level in the 4-pixel addition output mode, it is more desirable to set the OB clamp level to 0 and then accumulate the OB clamp level in the control circuit 30b. The time to reach the clamp level is shortened.

  Then, as shown in FIG. 15, when switching from the 4-pixel addition output mode to the all-pixel output mode, an appropriate value is obtained within the vertical blanking period when the OB clamp level is lowered according to the time constant based on the control circuit 30b. The problem of not being able to reach the OB clamp level is eliminated. Therefore, an image in which the lower part is darkened is not generated, and a stable image can always be recorded.

  Further, after the still image capturing process is performed, the through image is output to the display 48 again. Therefore, the CCD imager 16 is switched from the all-pixel output mode to the 4-pixel addition output mode. However, in the clamp circuit 30, the CPU 34 accumulates the OB clamp level in the register 30d so as to reach the OB clamp level in the 4-pixel addition output mode without performing control to reset the register 30d.

  Next, processing executed by the CPU 34 in the clamp circuit 30 when the above-described 4-pixel addition output mode and all-pixel addition output mode are switched will be described with reference to the flowchart of FIG.

  When the power button of the operation unit 52 is pressed, the digital camera 10 is turned on. Then, the CPU 34 sets the analog video signal output from the CCD imager 16 to be output in the through image mode, that is, by adding four pixels, in order to display the through image on the display 48 in step S1. That is, control is performed so that the charge readout pulse, vertical transfer pulse, and horizontal transfer pulse of the timing generator (TG) are added and output by four pixels.

  In step S3, the OB clamp level is reset, that is, the register 30d is reset to zero.

  Then, the process proceeds to step S5, and it is determined whether or not the capture of one screen has been completed. If “YES” is determined here, the process proceeds to a step S7 to determine whether or not there is a switching operation to the still image mode, that is, the all-pixel output mode. An example of this switching operation is whether or not the shutter button of the operation unit 52 has been pressed.

  If NO is determined in step S7, the process proceeds to step S5, and it is determined again whether or not one screen has been captured. If YES is determined, the process proceeds to step S9.

  In step S9, in order to output a still image, an analog video signal output from the CCD imager 16 is set to be output in all pixels. That is, control is performed so that the charge readout pulse, vertical transfer pulse, and horizontal transfer pulse of the timing generator (TG) are output from all pixels.

  In step S11, the OB clamp level is reset, that is, the register 30d is reset to zero.

  Then, the process proceeds to step S13, and it is determined whether or not the capture of one screen has been completed. If YES is determined, the process proceeds to step S15, and the through image mode (4-pixel addition output mode) is set again. Then, the process returns to step S5.

  As described above, in this embodiment, when the analog video signal output from the CCD imager 16 is switched from the four-pixel addition output mode to the all-pixel output mode, the register 30d in the control circuit 30d is reset. The OB clamp level can be reached within the vertical blanking period. Therefore, an image in which the lower part is darkened is not generated, and a stable image can always be recorded.

  In this embodiment, in the output of the CCD imager 16, the 4-pixel addition output mode is described as a mode for displaying a through image on the display 34, and the all-pixel output mode is described as a mode for capturing a still image. However, it goes without saying that the 4-pixel addition output mode may be a mode for recording moving images, and is not limited thereto.

  In the first embodiment, the CCD imager 16 is employed as the image pickup device and the present invention has been described. However, a CMOS imager may be employed.

Second Embodiment FIGS. 8 and 9 show a block diagram of a digital camera 60 of the second embodiment. 8 and 9, blocks having the same reference numerals as those in FIG. 1, which are block diagrams of the digital camera 10 of the first embodiment, have the same functions as the first embodiment and perform the same operations. Is done. Therefore, the same operation as that of the digital camera 10 of the first embodiment is omitted, and the difference between the digital camera 10 of the first embodiment and the digital camera 60 of the second embodiment will be mainly described.

  The digital camera 60 includes a CMOS imager unit 62, and the CMOS imager unit 62 includes a CMOS imager 64 on which a primary color filter is mounted as an image sensor. As in the first embodiment, an effective area and an optical black area (OB area) are formed on the light receiving surface of the CMOS imager 64 as shown in FIG. 3, and the effective area is formed at the center of the light receiving surface. The optical black area is formed around the light receiving surface.

  The CMOS imager 64 has an amplifier for each pixel and reads an analog video signal for each pixel. Therefore, the optical image of the subject is formed on the light receiving surface of the CMOS imager 64 and output as an analog imaging signal in accordance with a transfer signal necessary for driving the CMOS imager 64 generated by the timing generator (TG) 68. The timing generator (TG) 68 generates a clamp pulse and supplies it to the clamp circuit 74.

As shown in FIG. 9, the CMOS imager unit 64 includes a CDS circuit 82, an AGC circuit 84, a subtractor 70, an A / D converter 72, and a clamp circuit 74. The clamp circuit 74 includes a digital filter circuit 74a, a control circuit 74b, a D / A converter 74c, a register 74d, and a switch SW1. The analog video signal output from the CMOS imager 64 is subjected to correlated double sampling processing by the CDS circuit 82 and gain adjustment is performed by the AGC circuit 84. The clamp circuit 74 clamps the analog video signal in response to the clamp pulse output from the timing generator (TG) 68. The analog image signal that has been clamped is converted into a digital signal by the A / D converter 72. The A / D converter 72 converts the analog video signal with a 12-bit or 10-bit dynamic range and outputs a digital signal. The output digital signal is subjected to various signal processing by the signal processing circuit 32, converted into Y, U, and V signals and stored in the SDRAM 36. The processing for recording the data stored in the SDRAM 36 on the external memory card and the processing for displaying the through image on the display 48 are the same as those in the first embodiment, and are therefore omitted.

  Here, a clamp process when still image capturing is performed will be described in detail with reference to FIG. In the still image mode, when the shutter button of the operation unit 52 is pressed by the user, the optical lens 12 and the aperture 14 are adjusted as described above. Further, the CPU 66 controls the timing generator (TG) 68 to output each timing signal in the still image mode. Therefore, the timing generator (TG) 68 generates a switching signal for switching the dynamic range to 12 bits for the A / D converter 72, and invalid pixels such as defective pixels in the 12-bit digital black signal for the digital filter circuit 74a. A setting signal is generated to set so as to remove the level value. The A / D converter 72 and the digital filter circuit 74a perform switching and setting processing according to the switching signal and the setting signal.

When an optical image of a subject is formed on the light receiving surface of the CMOS imager 64, the electric charge generated by the photodiode is read by a timing generator (TG) 68, and an analog image signal corresponding to all pixels is read out. Video signals are output sequentially.
At that time, as in the first embodiment, as can be seen from FIG. 3, the charges corresponding to the pixels in the clamp area are first output to the outside as an analog video signal, and then the charges corresponding to the pixels in the effective area are analog video. It is output to the outside as a signal.

  Further, the switch SW1 is switched so as to connect the A / D converter 72 and the digital filter circuit 74a at the timing when the analog video signal is output from the CMOS imager 64 by the clamp signal generated by the timing generator (TG) 68. . In the CDS circuit 82, the analog black signal corresponding to the pixel in the clamp area is subjected to correlated double sampling processing, the gain is adjusted in the AGC circuit 84, and input to the A / D converter 72 through the subtractor 70. When still image capturing is performed, the dynamic range of the A / D converter 72 is 12 bits. Therefore, the analog black signal is converted into a 12-bit digital black signal and input to the digital filter circuit 74a. The digital filter circuit 74a is set to remove the level value of invalid pixels such as defective pixels in the 12-bit digital black signal, and performs filtering. The digital black signal filtered by the digital filter circuit 74a is input to the control circuit 74b, and based on the digital black signal, the OB clamp level is digitally stored as a value in the register 74d in the control circuit 74b, and is stored for one pixel. Averaging and outputting to the D / A converter 74c. The D / A converter 74c converts the OB clamp level value output from the control circuit 74b into an analog signal. After the analog signal described above is subtracted from the analog image signal in the effective area output from the AGC circuit 84, the signal is processed as a 12-bit digital signal through the A / D converter 72 after being clamped. The signal is input to the unit 32 and various signal processing is performed.

  The accumulation and averaging of the OB clamp level performed by the control circuit 74b is performed by outputting an analog video signal corresponding to the optical black area A shown in FIG. 3 from the CMOS imager 64 according to the time constant based on the control circuit 74b. This is done during the vertical blanking period.

  Next, clamp processing when a through image is output to the display 48 will be described in detail with reference to FIG.

  When the power button of the operation unit 52 is pressed by the user, the CPU 66 detects that the button is pressed and controls the timing generator (TG) 68 to output each timing signal in the through image mode. Therefore, the timing generator (TG) 68 generates a switching signal for switching the dynamic range to 10 bits for the A / D converter 72, and initializes the initialization signal for the digital filter circuit 74a and 10-bit digital black. A setting signal that is set so as to remove the level value of invalid pixels such as defective pixels in the signal is generated. The A / D converter 72 and the digital filter circuit 74a perform a switching process, an initialization process, and a setting process in accordance with the switching signal, the initialization signal, and the setting signal. Further, the register 74d in the control circuit 74b of the clamp circuit 74 is reset by the control of the CPU 66.

  As described above, when the optical lens 12 and the aperture 14 are adjusted and an optical image of the subject is formed on the light receiving surface of the CMOS imager 64, the charge generated by the photodiode is converted into a timing generator (TG) 68. The analog video signals corresponding to all the pixels are sequentially output as analog video signals. The processing until the analog video signal is input to the A / D converter 72 is the same as that for capturing a still image.

  When displaying a through image on the display 48, the dynamic range of the A / D converter 72 is 10 bits. Therefore, when an analog video signal is input to the A / D converter 72, it is output as a 10-bit digital signal. The charge corresponding to the pixels in the clamp area is first output to the outside as an analog video signal, and then the charge corresponding to the pixels in the effective area is output to the outside as an analog video signal. The analog black signal is converted into a 10-bit digital black signal. Then, a 10-bit digital black signal is input to the digital filter circuit 74a. The digital filter circuit 74a is set so as to remove the level value of invalid pixels such as defective pixels in the 10-bit digital black signal, and performs filtering.

  This digital filter circuit 74a corresponds to the erasure processing of the level value of the invalid pixel in the 12-bit or 10-bit digital black signal. Therefore, the setting of switching the threshold value of filtering for erasing the invalid pixel level value and obtaining the valid pixel level value is performed depending on whether the dynamic range of the A / D converter 72 is 12 bits or 10 bits. Is going.

  The filtered digital black signal is input to the control circuit 74b. The OB clamp level is digitally stored as a value in the register 74d in the control circuit 74b and averaged for one pixel.

  Then, the OB clamp level value output to the D / A converter 74c and output from the control circuit 74b is converted into an analog signal. By subtracting the analog signal described above from the analog video signal in the effective area output from the AGC circuit 84, the signal is processed as a 10-bit digital signal through the A / D converter 72 after being subjected to the clamping process. The signal is input to the unit 32 and various signal processing is performed.

  The accumulation and averaging of the OB clamp level performed by the control circuit 74b is performed by outputting an analog video signal corresponding to the optical black area A shown in FIG. 3 from the CMOS imager 64 according to the time constant based on the control circuit 74b. This is done during the vertical blanking period.

  Now, referring to FIG. 10, when the shutter button of the operation unit 52 is pressed and a still image is recorded on the external memory card 42, that is, the dynamic range of the A / D converter 72 is set to 12 bits. When the through image is output to the display 48 from the state where the digital signal is output, that is, the dynamic range of the A / D converter 72 is set to 10 bits, and the 10-bit digital signal is output. The case where it switches to the state which exists is demonstrated.

  As shown in FIG. 10, the OB clamp level when switching from the still image mode to the through image mode is reset to 0. The OB clamp level reaches the OB clamp level in the through image mode in the vertical blanking period according to the time constant based on the control circuit 74b. Since all pixels are output from the CMOS imager 64, the OB clamp level in the still image mode is the same as the OB clamp level in the through image mode, and appropriate clamping processing is performed.

  Then, as shown in FIG. 16, when the still image mode is switched to the through image mode, the OB clamp level changes, and a period that does not become normal until the reset process is performed occurs. The problem of not being able to reach the OB clamp level is eliminated.

  Accordingly, an image in which the entire screen is darkened is not generated, and a stable image can always be recorded.

  As described above, the reason why the OB clamp level changes is that the digital filter circuit 74a operates normally when the still image mode is switched to the through image mode, that is, when the number of bits in the dynamic range is changed. There is a case where the threshold value for filtering for obtaining the level value of the effective pixel is not switched.

  A process executed by the CPU 66 for the clamp circuit 74 when the above-described still image mode and through image mode are switched will be described with reference to a flowchart of FIG. Steps denoted by the same reference numerals as in FIG. 8 in the flowchart of FIG. 11 are the same as the processes based on the flowchart of FIG. 8 described in the first embodiment.

  When the power button of the operation unit 52 is pressed, the digital camera 60 is powered on, and the CPU 66 causes the timing generator (TG) 68 to display the through image mode in order to display the through image on the display 48 in step S16. Control is performed so that each timing signal is output. The timing generator (TG) 68 generates a switching signal for switching the dynamic range to 10 bits for the A / D converter 72, and outputs an initialization signal for initialization processing and a 10-bit digital black signal to the digital filter circuit 74a. A setting signal that is set so as to remove the level value of an invalid pixel such as a defective pixel is generated. The A / D converter 72 and the digital filter circuit 74a perform switching and setting processing according to the switching signal, the initialization signal, and the setting signal.

  In step S17, the OB clamp level is reset, that is, the register 74d is reset to zero.

  Then, the process proceeds to step S5, and it is determined whether or not the capture of one screen has been completed. If “YES” is determined here, the process proceeds to a step S7 to determine whether or not there is an operation for switching to the still image mode. An example of this switching operation is whether or not the shutter button of the operation unit 52 has been pressed.

  If NO is determined in step S7, the process proceeds to step S5, and it is determined again whether or not one screen has been captured. If YES is determined, the process proceeds to step S9.

  In step S19, the CPU 66 controls the timing generator (TG) 68 to output each timing signal in the still image mode in order to output a still image. Therefore, the timing generator (TG) 68 generates a switching signal for switching the dynamic range to 12 bits for the A / D converter 72, and invalid pixels such as defective pixels in the 12-bit digital black signal for the digital filter circuit 74a. A setting signal is generated to set so as to remove the level value. The A / D converter 72 and the digital filter circuit 74a perform switching and setting processing according to the switching signal and the setting signal.

  Then, the process proceeds to step S13, where it is determined whether or not one screen has been captured. If YES is determined, the process returns to step 16 and the timing generator (TG) 68 is caused to display the through image on the display 48. On the other hand, control is performed so that each timing signal in the through image mode is output.

  As described above, in this embodiment, when the still image mode is switched to the through image mode, that is, when the dynamic range of the A / D converter 72 is changed from 12 bits to 10 bits, the digital filter circuit 74a is changed. In order to initialize and reset the register 74d in the control circuit 74b, the OB clamp level can be reached within the vertical blanking period. Therefore, an image in which the entire screen is darkened is not generated, and a stable image can always be recorded.

  In the second embodiment, the dynamic range of the A / D converter 72 is set to 10 bits in the through image mode, and the dynamic range of the A / D converter 72 is set to 12 bits in the still image mode. Needless to say, the through image mode may be a moving image recording mode for recording moving images, and is not limited thereto.

  In the second embodiment, the CMOS imager 64 is used as the image sensor and the present invention has been described. However, a CCD imager may be used.

Third Embodiment FIG. 12 shows a clamp circuit 106 of an AFE circuit 100 applied to the first and second embodiments. In the first and second embodiments, the OB clamp level is adjusted digitally in the clamp process, but the clamp circuit 106 adjusts the OB clamp level in an analog manner. In the third embodiment, a clamp process based on the first embodiment will be described using the clamp circuit 106. Here, the CPU 108 that controls the clamping process performs control different from that of the first embodiment.

  The clamp circuit 106 includes a digital filter 106a, a D / A converter 106b, switches SW1 to SW3, a first discharge resistor R1, a second discharge resistor R2, and a capacitor C. The analog imaging signal output from the CCD imager 16 is subjected to correlated double sampling processing by the CDS circuit 22 and gain adjustment is performed by the AGC circuit 24. The digital filter circuit 106a removes the level value of invalid pixels such as defective pixels in the digital black signal and outputs it to the D / A converter 106b. The D / A converter 106b converts the digital black signal into an analog black signal. To do.

  In addition, the switch SW2 is switched so that the capacitor C and the first discharge resistor R1 are connected by the control of the CPU 34 at the timing when the shutter button of the operation unit 52 is pressed by the user. The charge accumulated in the capacitor C is connected to the first discharge resistor R1, whereby the charge accumulated in the capacitor C decreases. The CPU 34 switches the switch SW2 so that the capacitor C is connected to the D / A converter 106b as soon as the switch SW2 is switched. Therefore, the switch SW3 is connected to the capacitor charging power source V so that the OB clamp level based on the analog black signal from the D / A converter 106b is reached, and charges are accumulated in the capacitor C. The capacitor C and the subtractor 26 are connected in series, and the voltage of the capacitor C is subtracted from the effective area analog video signal output from the AGC circuit 24. After such clamping processing is performed, the signal processing unit 32 performs various signal processing.

  When the user turns on the main body by pressing the power button of the operation unit 52, the CPU 34 switches the switch SW2 so as to connect the capacitor C to the first discharge resistor R1. Then, the electric charge accumulated in the capacitor C is discharged and decreases. Further, the CPU 34 switches the switch SW2 so that the capacitor C is connected to the D / A converter 106b immediately after switching the switch SW2.

  Therefore, the switch SW3 is switched so as to be connected to the capacitor charging power source V, and the electric charge is accumulated in the capacitor C so as to become the OB clamp level. This charge accumulation is performed while an analog video signal corresponding to the optical black area A shown in FIG. 3 is being output from the CCD imager 16, that is, during a vertical blanking period.

  Therefore, the voltage of the capacitor C is subtracted from the analog video signal in the effective area output from the AGC circuit 24. After such clamping processing is performed, the signal processing unit 32 performs various signal processing.

  Then, as shown in FIG. 13, the OB clamp level when the four-pixel addition output mode is switched to the all-pixel output mode becomes sufficiently low when the switching is performed, and then all the values according to the time constants of the capacitor C and the second discharge resistor R2. The OB clamp level in the pixel output mode has been reached. Since the OB clamp level in the all-pixel output mode is lower than the OB clamp level in the 4-pixel addition output mode, it takes a shorter time to reach the desired OB clamp level if the capacitor C is discharged once and then charged. Therefore, as shown in FIG. 15, when the four-pixel addition output mode is switched to the all-pixel output mode, if the OB clamp level is lowered according to the time constant of the capacitor C and the second discharge resistor R2, the vertical blanking period is reached. This eliminates the problem that the OB clamp level that is appropriate for the target cannot be reached. Therefore, an image in which the lower part is darkened is not generated, and a stable image 8 can always be recorded.

  Further, after the still image capturing process is performed, the through image is output to the display 48 again. Therefore, the CCD imager 16 is switched from the all-pixel output mode to the 4-pixel addition output mode. However, in the clamp circuit 30, the CPU 34 accumulates electric charge in the capacitor C so as to reach the OB clamp level in the 4-pixel addition output mode without performing the switching control of the switch SW2.

  A process executed by the CPU 108 for the clamp circuit 106 when the above-described 4-pixel addition output mode and all-pixel addition output mode are switched will be described with reference to the flowchart of FIG. Steps denoted by the same reference numerals as those in FIG. 8 in the flowchart of FIG. 14 are the same as the processes based on the flowchart of FIG. 8 described in the first embodiment.

  When the power button of the operation unit 52 is pressed, the main body is turned on. Then, the CPU 108 sets the analog video signal output from the CCD imager 16 to be output in the through image mode, that is, by adding four pixels, in order to display the through image on the display 48 in step S1. That is, control is performed so that the charge readout pulse, vertical transfer pulse, and horizontal transfer pulse of the timing generator (TG) are added and output by four pixels.

  In step S23, the switch SW2 in the clamp circuit 106 is switched so that the capacitor C and the first discharge resistor R1 are connected.

  Then, the process proceeds to step S5, and it is determined whether or not the capture of one screen has been completed. If “YES” is determined here, the process proceeds to a step S7 to determine whether or not a switching operation has been performed in the still image mode, that is, the all-pixel output mode. An example of this switching operation is whether or not the shutter button of the operation unit 52 has been pressed.

  If NO is determined in step S7, the process proceeds to step S5, and it is determined again whether or not one screen has been captured. If YES is determined, the process proceeds to step S9.

  In step S9, in order to output a still image, an analog video signal output from the CCD imager 16 is set to be output in all pixels. That is, control is performed so that the charge readout pulse, vertical transfer pulse, and horizontal transfer pulse of the timing generator (TG) are output from all pixels.

  In step S25, the switch SW2 in the clamp circuit 106 is switched so that the capacitor C and the first discharge resistor R1 are connected.

  Then, the process proceeds to step S13, and it is determined whether or not the capture of one screen has been completed. If YES is determined, the process proceeds to step S15, and the through image mode (4-pixel addition output mode) is set again. Then, the process returns to step S5.

  As described above, in this embodiment, when the analog video signal output from the CCD imager 16 is switched from the 4-pixel addition output mode to the all-pixel output mode, the capacitor C is discharged once, so that the vertical blanking period The capacitor C can be charged to reach the OB clamp level. Therefore, an appropriate OB clamp level can always be maintained in the clamping process, and an image in which the lower portion is blackened is not generated, and a stable image can always be recorded.

It is a block diagram which shows the structure of the camera of 1st Example which concerns on this invention. It is a block diagram which shows a part of structure of the camera of 1st Example which concerns on this invention. It is an illustration figure which shows the structure of the image pick-up element of the 1st Example-3rd Example camera which concerns on this invention. It is an illustration figure which shows the color filter with which the image pick-up element of the 1st Example-3rd Example camera which concerns on this invention was equipped. It is an illustration figure which shows the OB clamp level of the camera of 1st Example which concerns on this invention. It is an illustration figure which shows the relationship between the output mode of the image pick-up element of the camera of 1st Example which concerns on this invention, and OB clamp level. It is a flowchart in 1 part of the control procedure which CPU of the camera of 1st Example which concerns on this invention performs. It is a block diagram which shows the structure of the camera of 2nd Example which concerns on this invention. It is a block diagram which shows a part of structure of the camera of 2nd Example which concerns on this invention. It is an illustration figure which shows the relationship between the imaging mode and OB clamp level of the camera of 2nd Example which concerns on this invention. It is a flowchart in 1 part of the control procedure which CPU of the camera of 2nd Example which concerns on this invention performs. It is a block diagram which shows a part of structure of the camera of 3rd Example based on this invention. It is an illustration figure which shows the relationship between the output mode of the image pick-up element of the camera of 3rd Example which concerns on this invention, and OB clamp level. It is a flowchart in 1 part of the control procedure which CPU of the camera of 3rd Example concerning this invention performs. It is an illustration figure which shows the relationship between the output mode of the image pick-up element of the conventional camera, and OB clamp level. It is an illustration figure which shows the relationship between the imaging mode of the conventional camera, and OB clamp level.

Explanation of symbols

10 ... Camera body 16 ... CCD imager 18 ... Timing generator (TG)
DESCRIPTION OF SYMBOLS 20 ... AFE circuit 22 ... CDS circuit 24 ... AGC circuit 26 ... Subtractor 28 ... A / D converter 30 ... Clamp circuit 30a ... Digital filter 30b ... Control circuit 30c ... D / A converter 30d ... Register 34 ... CPU
60 ... Camera body 62 ... CMOS imager unit 64 ... CMOS imager 66 ... CPU
68 ... Timing generator (TG)
70 ... Subtractor 72 ... A / D converter 74 ... Clamp circuit 74a ... Digital filter 74b ... Control circuit 74c ... D / A converter 74d ... Register 100 ... AFE circuit 106 ... Clamp circuit 106a ... Digital filter 106b ... D / A Converter SW1 ... Switch SW2 ... Switch SW3 ... Switch C ... Capacitor R1 ... First discharge resistor R2 ... Second discharge resistor

Claims (9)

An image sensor that outputs an image signal from a plurality of pixels formed adjacent to an optical black area and an effective area according to a plurality of output modes including a first output mode and a second output mode;
A first clamp level is detected based on the optical black area of the first image signal output in the first output mode, and the first image signal is clamped with the first clamp level as a reference black level. First clamping means for applying;
A second clamp level is detected based on the optical black area of the second image signal output in the second output mode, and the second image signal is clamped with the second clamp level as a reference black level. Second clamping means for applying
Mode switching means for switching between the first output mode and the second output mode;
When switching from the first output mode to the second output mode by the switching means, the time required for the level change for changing the reference black level from the first clamp level to the second clamp level is controlled within a predetermined period. A camera comprising control means for executing   2. The camera according to claim 1, wherein in the level change in the control means, a reset process for lowering the first clamp level to be lower than a predetermined level is performed, and then the camera is changed to the second clamp level.   2. The first clamp level and the second clamp level are levels based on a register value, and the clamp processing reduces an analog signal obtained by converting the register value into the analog video signal. The camera according to 2 or 2.   The first clamp level and the second clamp level are levels based on a charge amount due to charging / discharging of a capacitor, and the clamp processing reduces the charge amount held by the capacitor in the image signal. The camera according to claim 1.   5. The camera according to claim 4, wherein the reset processing at the first clamp level discharges so that a charge amount of the capacitor is lower than a threshold value. 6.   The camera according to claim 1, wherein the predetermined period is a vertical blanking period when the image sensor outputs an image signal. An image sensor that outputs an analog video signal from a plurality of pixels in which an optical black area and an effective area are formed adjacent to each other;
First A / D conversion means for performing a first A / D conversion process on the analog video signal and outputting a first digital image signal having a first number of bits;
Second A / D conversion means for performing a second A / D conversion process on the analog video signal and outputting a second digital image signal having a second number of bits;
Switching means for switching between the first A / D conversion process and the second A / D conversion process;
A digital filter that performs a filtering process for obtaining a digital black signal corresponding to a specific pixel in an optical black area on the first digital image signal and the second digital image signal;
Clamping means for performing clamp processing on the analog video signal with a clamp level based on the digital black signal subjected to the filtering processing as a reference black level;
A camera comprising: initialization means for performing initialization processing on the digital filter when the first A / D conversion processing and the second A / D conversion processing are switched by the switching means.   The camera according to claim 7, further comprising a reset process that resets the clamp level when the initialization process is performed.   9. The camera according to claim 8, wherein the clamp means includes a register, and the reset process sets a value of the register to zero.

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