JP2008072512A - Photographing apparatus and its control method, and photographing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively expand a dynamic range in a dynamic range expansion area on which high-luminance light is incident. <P>SOLUTION: A photographing apparatus has a unit pixel 15 which has a photodiode 2 that photoelectrically converts light to signal charges, a floating diffusion layer 7 that temporarily stores the signal charges stored in the photodiode 2, reset switches 4 and 10 that remove the signal charges stored in the floating diffusion layer 7, and an output part that converts the signal charges transferred from the photodiode 2 to the floating diffusion layer 7 to a voltage and outputs it. In addition, the photographing apparatus also has a comparator 8 which compares the signal charges stored in the floating diffusion layer 7 with a specified value. The reset switches 4 and 10 reset the floating diffusion layer 7 at different reset levels SVDD1 and SVDD2 based on a comparison result of the comparator 8. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an imaging apparatus having a photoelectric conversion element, a control method therefor, and an imaging system.

  2. Description of the Related Art Conventionally, there is an imaging apparatus such as a digital camera that records or reproduces an image captured by an imaging element such as a CCD image sensor or a CMOS image sensor using a memory card having a memory element as a recording medium. In particular, a CMOS image sensor is widely used as an image pickup element mounted on an image pickup apparatus from the viewpoint of low voltage and low power consumption.

  6 to 8 are diagrams showing the configuration and driving timing of a conventional CMOS image sensor.

  FIG. 6 is a circuit diagram showing a configuration of a conventional CMOS image sensor. The unit pixel 1 includes a photodiode 2, a transfer switch 3, a reset switch 4, a row selection switch 5, a source follower amplifier 6, and a floating diffusion layer (floating diffusion) 7.

  The photodiode 2 is a photoelectric conversion element and converts light into signal charges. The signal charge generated by the photodiode 2 is transferred to the floating diffusion layer 7 through the transfer switch 3 driven by the pulse PTX and accumulated in the floating diffusion layer 7. The floating diffusion layer 7 is reset to the level of the potential SVDD by a reset pulse PRES applied to the reset switch 4 connected to the gate of the source follower amplifier 6. The charge accumulated in the floating diffusion layer 7 is amplified by the source follower amplifier 6. The row selection switch 5 is selected by a selection pulse PSEL from a vertical scanning circuit (not shown). When the row selection switch 5 is selected, the output of the source follower amplifier 6 is output to the vertical output line 22 by the source follower circuit constituted by the row selection switch 5 and the load current source 21. The signal output to the vertical output line 22 is accumulated in the transfer capacitor CTS 27 through the transfer gate 25 driven by the signal output pulse PTS, and is accumulated in the transfer capacitor CTN 26 through the transfer gate 24 driven by the noise output pulse PTN. Next, the noise component is accumulated in the capacitor CHN30 and the signal component is accumulated in the capacitor CHS31 through transfer switches 28 and 29 driven by control signals PHS and PHN from a horizontal scanning circuit (not shown). The difference between the noise component and the signal component is output as a pixel signal by the differential amplifier 32.

  FIG. 7 is a diagram illustrating the drive timing of the imaging apparatus of FIG.

  First, along with the fall of the signal HD indicating the start of one horizontal scanning period, the vertical output line 22 is reset to the set potential by a circuit (not shown).

  During the period of T1, the PRES signal is at a high level (hereinafter referred to as “H”), and the reset switch 4 is turned on in response to this and accumulated in the floating diffusion layer 7 connected to the gate of the source follower amplifier 6. The charge is reset to the set potential SVDD.

  In the period of T2, the PRES signal is at a low level (hereinafter referred to as “L”), and the reset switch 4 is turned off accordingly. Further, the PSEL signal becomes H, and in response to this, the source follower circuit constituted by the row selection switch 5 and the load current source 21 is activated, and the reset potential of the floating gate of the source follower amplifier 6 on the vertical output line 22. A noise output corresponding to is performed. Further, the PTN signal becomes H, the transfer capacitor CTN 26 is connected to the vertical output line 22, and a noise component signal is accumulated in the transfer capacitor CTN 26.

  Next, a mixed signal of signal charges and noise components generated in the photodiode 2 is accumulated.

  First, the vertical output line 22 is reset to a set potential by a circuit (not shown).

  During the period T3, the PTX signal becomes H, the transfer switch 3 is turned on in response to this, and the signal charge accumulated in the photodiode 2 is transferred to the floating gate of the source follower amplifier 6.

  During the period T 4, the PSEL signal becomes H, and in response to this, the source follower circuit composed of the row selection switch 5 and the load current source 21 is activated, and the floating gate of the source follower amplifier 6 is placed on the vertical output line 22. A noise output corresponding to the reset potential is made. Further, the PTS signal becomes H, and the transfer capacitor CTS 27 that accumulates “optical signal component + noise component” is connected to the vertical output line 22, and the signal “optical signal component + noise component” is held in the transfer capacitor CTS 27.

  As described above, the noise component for one row and the “light signal component + noise component” generated by the photodiode are accumulated in the transfer capacitor CTN26 and the transfer capacitor CTS27, respectively.

  Next, these two signals are transferred to the capacitors CHN30 and CHS31 by a control pulse PH controlled by a horizontal scanning circuit (not shown). The noise component and “optical signal component + noise component” accumulated in the capacitors CHN30 and CHS31 are output by the differential amplifier 32 as (optical signal component + noise component) −noise component, that is, an optical signal component.

  FIG. 8 shows the signal amount with respect to the incident light amount of “optical signal component + noise component” (hereinafter referred to as “S signal”) and noise component (hereinafter referred to as “N signal”) in the imaging apparatus using the CMOS image sensor described above. It is a figure showing transition of. In FIG. 8, the S signal generally increases monotonically in proportion to the amount of incident light up to or near the saturation level Vsat, and when the amount of light equal to or greater than the amount of incident light Esat reaching the saturation level Vsat is incident. Vsat is output. That is, in such an imaging apparatus, an incident light quantity that is greater than or equal to Esat cannot be captured. The N signal is a signal amount corresponding to the level of the potential SVDD that resets the floating diffusion layer 7 using the reset pulse PRES, regardless of the amount of incident light.

  In an imaging apparatus using a CMOS image sensor or a CCD image sensor having such a structure, proposals have been made to expand the dynamic range in order to capture a large amount of light. Conventionally, the dynamic range is expanded by dropping the gradation in a high luminance range such as near the saturation point.

  However, in the conventional method, for example, after recording an image signal, even if an attempt is made to make an image centered on a signal in a higher luminance range by level correction or the like, the image is recorded with a reduced gradation. Therefore, a satisfactory image may not be obtained. That is, with such a technique, it has been difficult to obtain a satisfactory image in a wide luminance region from high luminance to low luminance.

  The present invention has been made in view of the above problems, and an object of the present invention is to enable effective expansion of a dynamic range even in a dynamic range expansion region where a high-intensity light amount is incident.

  According to a first aspect of the present invention, there is provided a photoelectric conversion element that photoelectrically converts light into a signal charge, a storage unit that temporarily stores the signal charge stored in the photoelectric conversion element, and a signal charge stored in the storage unit And a comparison unit that compares a signal charge amount accumulated in the accumulation unit with a set value, and the reset unit includes a comparison result of the comparison unit. Based on the above, the storage unit is reset at a different reset level.

  A second aspect of the present invention relates to an imaging system, and includes an optical system and the imaging device described above.

  According to a third aspect of the present invention, there is provided a photoelectric conversion element that photoelectrically converts light into a signal charge, a storage unit that temporarily stores the signal charge stored in the photoelectric conversion element, and a signal charge stored in the storage unit. A comparison step of comparing a signal charge amount stored in the storage portion with a set value, and a comparison result in the comparison step And a resetting step of resetting the storage unit at a different reset level.

  According to the present invention, it is possible to effectively expand a dynamic range even in a dynamic range expansion region where a high-luminance light amount is incident.

  Preferred embodiments of the present invention will be described below with reference to the drawings. 1 to 3 are diagrams showing a configuration and driving timing of a CMOS image sensor according to a preferred embodiment of the present invention.

  FIG. 1 is a circuit diagram showing a configuration of a CMOS image sensor according to a preferred embodiment of the present invention. Components similar to those in FIG. 4 are denoted by the same reference numerals. The unit pixel 15 includes a photodiode 2, a photodiode 2, a transfer switch 3, a reset switch 4, a row selection switch 5, a source follower amplifier 6, a floating diffusion layer 7, a comparator 8, a latch unit 9, and a reset switch 10. The unit pixel 15 also includes an AND gate 11, an OR gate 12, an AND gate 13, and an inverter 14.

  The photodiode 2 is a photoelectric conversion element and converts light into signal charges. The signal charge generated by the photodiode 2 is transferred to the floating diffusion layer 7 through the transfer switch 3 driven by the pulse PTX. The transferred charge is accumulated in the floating diffusion layer 7. The floating diffusion layer 7 is reset to the level of the potential SVDD1 or SVDD2 by the reset pulse PRES applied to the reset switch 4 connected to the gate of the source follower amplifier 6. The charge accumulated in the floating diffusion layer 7 is amplified by the source follower amplifier 6. The row selection switch 5 is selected by a control pulse PSEL from the vertical scanning circuit 220 in FIG. The comparator 8 monitors the output of the source follower amplifier 6 and compares the level (potential) with a predetermined reference level Ref (potential). The latch unit 9 fixes the output of the comparator 8 for one horizontal period. The reset switch 10 is composed of a MOS transistor, and resets the potential of the floating diffusion layer 7 to the level of the potential SVDD2. When the row selection switch 5 is selected, the output of the source follower amplifier 6 is output to the vertical output line 22 by the source follower circuit constituted by the row selection switch 5 and the load current source 21. The vertical output line 22 corresponds to one of VSIG1 to VSIGn in FIG. The signal output to the vertical output line 22 is accumulated in the transfer capacitor CTS 27 through the transfer gate 25 driven by the signal output pulse PTS, and is accumulated in the transfer capacitor CTN 26 through the transfer gate 24 driven by the noise output pulse PTN. Next, the N signal is accumulated in the capacitor CHN30 and the signal component is accumulated in the capacitor CHS31 through the transfer switches 28 and 29 driven by the control pulses PHS and PHN from the horizontal scanning circuit of FIG. The difference between the S signal and the N signal is output as a pixel signal by the differential amplifier 32. The output amplifier 33 is an output amplifier for monitoring the storage capacity of the capacitor CHN30.

  FIG. 2 is a diagram illustrating the drive timing of the imaging apparatus of FIG. In FIG. 2, the horizontal scanning period H1 represents a transition when the incident light amount is equal to or higher than a predetermined level during the accumulation period, and the horizontal scanning period H2 represents a transition when the incident light amount is less than the predetermined level. It is.

  First, along with the fall of the signal HD indicating the start of the horizontal scanning period H1, the vertical output line 22 is reset to the set potential by a circuit (not shown).

  In the period of T1, the PRES signal is H and the output of the latch unit 9 is L. Therefore, H is input to the two input terminals of the AND gate 11. As a result, the AND gate 11 outputs H, the reset switch 4 is turned ON, and the floating diffusion layer 7 connected to the gate of the source follower amplifier 6 is reset to the set first potential SVDD1. Thereafter, the PRES signal becomes L, the AND gate 11 outputs L, and the reset switch 4 is turned OFF.

  During the period T2, the PTX signal becomes H, and the transfer switch 3 is turned on in response to this, and the signal charge accumulated in the photodiode 2 is transferred to the floating gate of the source follower amplifier 6 and accumulated in the floating diffusion layer 7. The The PTX signal is maintained at a high level during the signal charge accumulation period, and the amount of signal charge accumulated in the floating diffusion layer 7 is monitored by the comparator 8. If the signal charge amount accumulated in the floating diffusion layer 7 is equal to or larger than the set value, the output of the comparator 8 becomes H. When the output of the comparator 8 becomes H, the OR gate 12 outputs H, the reset switch 10 is turned ON, and the floating diffusion layer 7 is reset to the second potential SVDD2. The output of the latch unit 9 is fixed to H in one horizontal period H1 when the output of the comparator 8 becomes H. After the accumulation period T2, by setting the PTX signal to a low level, the transfer switch 3 is turned off, and the transfer of signal charges from the photodiode 2 is stopped.

  In the period T3, the PSEL signal becomes H, and the source follower circuit composed of the row selection switch 5 and the load current source 21 is activated according to this. Then, an S signal corresponding to the potential of the floating gate of the source follower amplifier 6 is output on the vertical output line 22. Further, the PTS signal becomes H, the transfer capacitor CTS27 is connected to the vertical output line 22, and the S signal is accumulated in the transfer capacitor CTS27.

  Next, the N signal is transferred. As described above, since the signal charge amount accumulated in the floating diffusion layer 7 is equal to or greater than the set value and the output of the comparator 8 is H during the period T2, the output of the latch unit 9 is fixed at a high level. Has been.

  Therefore, in the period T4, the PRES signal is H, and the output of the latch unit 9 is H. Therefore, the AND gate 4 outputs L and the AND gate 11 outputs H. As a result, the reset switch 4 is turned off, the reset switch 10 is turned on, and the floating diffusion layer 7 is reset to the second potential SVDD2.

  During the period T5, the PSEL signal becomes H, and the source follower circuit composed of the row selection switch 5 and the load current source 21 is activated in response to this, and the floating gate of the source follower amplifier 6 is placed on the vertical output line 22. N signal corresponding to the reset potential is output. Further, the PTN signal becomes H, the transfer capacitor CTN26 for storing the N signal is connected to the vertical output line 22, and the N signal is held in the transfer capacitor CTN26.

  As described above, the N signal and the S signal generated by the photodiodes for one row are accumulated in the transfer capacitor CTN26 and the transfer capacitor CTS27, respectively.

  Next, these two signals are transferred to the capacitors CHN30 and CHS31 by the control pulses PHS and PHN controlled by the horizontal scanning circuit 222 of FIG. The N signal and the S signal accumulated in the capacitors CHN30 and CHS31 are output by the differential amplifier 32 as an S signal-N signal, that is, an optical signal component.

  Next, the vertical output line 22 is reset to the set potential by a circuit (not shown) with the fall of the signal HD indicating the start of the horizontal scanning period H2.

  In the period of T11, the PRES signal is H and the output of the latch unit 9 is L, so that H is input to the two input terminals of the AND gate 11. As a result, the AND gate 11 outputs H, the reset switch 4 is turned ON, and the floating diffusion layer 7 connected to the gate of the source follower amplifier 6 is reset to the set first potential SVDD1. Thereafter, the PRES signal becomes L, the AND gate 11 outputs L, and the reset switch 4 is turned OFF.

  In the period of T12, the PTX signal becomes H, the transfer switch 3 is turned on in response to this, the signal charge accumulated in the photodiode 2 is transferred to the floating gate of the source follower amplifier 6, and is accumulated in the floating diffusion layer 7. The The PTX signal is maintained at a high level during the signal charge accumulation period, and the amount of signal charge accumulated in the floating diffusion layer 7 is monitored by the comparator 8. If the signal charge amount accumulated in the floating diffusion layer 7 is equal to or larger than the set value, the output of the comparator 8 becomes H. However, in the period T12, the signal charge amount accumulated in the floating diffusion layer 7 is less than the set value, and the output of the comparator 8 is fixed to L. After the accumulation period T12, the transfer switch 3 is turned off by setting the PTX signal to the low level, and the transfer of the signal charge from the photodiode 2 is stopped.

  During the period T13, the PSEL signal becomes H, and in response to this, the source follower circuit constituted by the row selection switch 5 and the load current source 21 is activated, and the floating gate of the source follower amplifier 6 is placed on the vertical output line 22. The S signal corresponding to the potential is output. Further, the PTS signal becomes H, the transfer capacitor CTS27 is connected to the vertical output line 22, and the S signal is accumulated in the transfer capacitor CTS27.

  Next, the N signal is transferred. As described above, since the signal charge amount accumulated in the floating diffusion layer 7 is less than the set value and the output of the comparator 8 is L during the period T12, the output of the latch unit 9 is at a low level. It is fixed.

  Therefore, in the period T14, the PRES signal becomes H and the output of the latch unit 9 is L. Therefore, the AND gate 4 outputs H and the AND gate 11 outputs L. As a result, the reset switch 4 is turned on, the reset switch 10 is turned off, and the floating diffusion layer 7 is reset to the first potential SVDD1.

  In the period of T15, the PSEL signal becomes H, and the source follower circuit composed of the row selection switch 5 and the load current source 21 is activated in response to this. A noise output corresponding to the reset potential of the floating gate of the source follower amplifier 6 is output on the vertical output line 22. Further, the PTN signal becomes H, the transfer capacitor CTN26 for storing the N signal is connected to the vertical output line 22, and the N signal is held in the transfer capacitor CTN26.

  As described above, also in the horizontal scanning period H2, as in the horizontal scanning period H1, the N signal for one row and the S signal generated by the photodiode are accumulated in the transfer capacitor CTN26 and the transfer capacitor CTS27, respectively.

  Next, these two signals are transferred to the capacitors CHN30 and CHS31 by a control pulse PH controlled by a horizontal scanning circuit (not shown). The N signal and the S signal accumulated in the capacitors CHN30 and CHS31 are output by the differential amplifier 32 as an S signal-N signal, that is, an optical signal component.

  FIG. 3 is a diagram illustrating the transition of the signal amount with respect to the incident light amounts of the S signal and the N signal in the imaging apparatus using the above-described CMOS image sensor. In FIG. 3, the S signal monotonously increases in proportion to the incident light amount in a range below the incident light amount Ejud that reaches a predetermined determination level Vjud. In the range where the incident light quantity is Ejud or more, the reset switch 10 is turned on, and the S signal is once reset to the level of the potential SVDD2. Thereafter, the S signal monotonously increases with the same inclination as before the reset in proportion to the incident light amount after reaching Ejud, that is, the light amount obtained by subtracting Ejud from the total incident light amount. The N signal outputs a signal amount corresponding to the level of the potential SVDD1 in the range less than the incident light amount Ejud, and outputs a signal amount corresponding to the level of SVDD2 in the range where the incident light amount is Ejud or more.

  Accordingly, if the output amplifier 33 monitors the N signal and the output corresponds to the level of the reset potential SVDD1, it is determined that the incident light quantity is small and the reset during the accumulation of the optical signal is not performed. The output of the dynamic amplifier 32 may be used as the optical signal amount as it is.

  On the other hand, when the output of the output amplifier 33 is an output corresponding to the level of the reset potential SVDD2, it is determined that the amount of incident light is large and the reset during the accumulation of the optical signal has been performed. Then, what is obtained by adding a value corresponding to the determination level Vjud to the output of the differential amplifier 32, as indicated by a dotted line in the figure, may be used as the optical signal amount.

  As described above, according to the imaging apparatus according to the preferred embodiment of the present invention, it is possible to capture an incident light amount equal to or greater than the incident light amount Estat reaching saturation shown in FIG. it can. Even in the expanded dynamic range region, the amount of incident light can be captured with the same sensitivity as in the normal case, so that gradation is not lost.

  In the present embodiment, the configuration in which the reset potential is switched only once has been described as an example, but the present invention is not limited to this. For example, a configuration may be used in which the signal charge is reset a plurality of times each time the amount of incident light reaches a predetermined determination level Vjud. In this case, as means for knowing the number of times of resetting, means for preparing three or more types of reset levels may be used, or means for separately preparing a counter and counting the number of resets may be used. .

  FIG. 4 is a schematic view of an imaging unit using the above-described CMOS image sensor. B11 to Bmn (m and n are integers; the same applies hereinafter) are pixels 15 arranged two-dimensionally on the imaging surface. The vertical scanning circuit 220 outputs a control pulse for reading an electrical signal from the pixel for each of the horizontal output lines VSEL1 to VSELm. The electrical signals of the respective pixels selected by the horizontal output lines VSEL1 to VSELm are read by the vertical output lines VSIG1 to VSIGn and accumulated in the adding circuit 221. The electrical signals accumulated in the adder circuit 221 are sequentially read and scanned by the horizontal scanning circuit 222 and output in time series. The electric signal of each pixel selected by the control pulse of the horizontal output line is read out to the adding circuit 221 by the control pulse of the vertical output lines VSIG1 to VSIGn.

  FIG. 5 is a diagram showing an outline of an imaging system using the imaging unit of FIG. Reference numeral 501 denotes a lens portion (referred to as “lens” in FIG. 5) as an optical system, 502 denotes a lens driving portion, 503 denotes a mechanical shutter (noted as mechanical shutter), and 504 denotes a mechanical shutter driving portion (“shutter driving portion” in FIG. 5). 505) denotes an A / D converter. Reference numeral 200 denotes an imaging unit having the configuration shown in FIG. Reference numeral 506 denotes an imaging signal processing circuit, 507 denotes a timing generation unit, 508 denotes a memory unit, 509 denotes a control unit, 510 denotes a recording medium control interface unit (indicated as “recording medium control I / F unit” in FIG. 5), 511. Indicates a display. Reference numeral 512 denotes a recording medium, 513 denotes an external interface unit (indicated as “external I / F unit” in FIG. 5), 514 denotes a photometric unit, and 515 denotes a distance measuring unit. The imaging signal processing circuit 506 includes a WB circuit 516 that performs white balance processing based on a signal from the A / D converter 505.

  The subject image that has passed through the lens unit 501 is formed in the vicinity of the imaging unit 200. A subject image formed in the vicinity of the imaging unit 200 is captured by the imaging unit 200 as an image signal. The imaging signal processing circuit 506 amplifies the image signal output from the imaging unit 200, converts the analog signal into a digital signal (A / D conversion), and converts the R, G, G, and B signals after A / D conversion. obtain. The imaging signal processing circuit 506 performs various corrections, compression of image data, and the like.

  The lens unit 501 is driven and controlled by a lens driving unit 502 such as zoom, focus, and diaphragm. The mechanical shutter 503 is a shutter mechanism having only a curtain corresponding to the rear curtain of a focal plane type shutter used in a single-lens reflex camera. The mechanical shutter 503 is driven and controlled by a shutter driving unit 504. The timing generation unit 507 outputs various timing signals to the imaging unit 200 and the imaging signal processing circuit 506. A control unit 509 performs control of the entire imaging system and various calculations. The memory unit 508 temporarily stores image data. The recording medium control interface unit 510 records image data on the recording medium 512 and reads or reads image data from the recording medium 512. The display unit 511 displays image data. The recording medium 512 is a detachable storage medium such as a semiconductor memory, and records image data. The external interface unit 513 is an interface for communicating with an external computer or the like. The photometry unit 514 detects the brightness information of the subject, and the distance measurement unit 515 detects the distance information to the subject. Reference numeral 516 denotes a white balance circuit (WB circuit). Note that the operation mode of the imaging apparatus is set by the operation unit 517.

1 is a circuit diagram showing a configuration of a CMOS image sensor according to a preferred embodiment of the present invention. It is a figure which shows the drive timing of the imaging device which concerns on suitable embodiment of this invention. It is a figure showing transition of the signal level in the imaging device concerning a suitable embodiment of the present invention. It is a general-view figure of the image pick-up part using a CMOS image sensor. It is a figure which shows the outline of the imaging system using the imaging part of FIG. It is a circuit diagram which shows the structure of the conventional CMOS image sensor. It is a figure which shows the drive timing of the conventional imaging device. It is a figure showing transition of the signal level in the conventional imaging device.

Explanation of symbols

2 Photodiode 4, 10 Reset switch 7 Floating diffusion layer 8 Comparator 15 Unit pixel SVDD1, SVDD2 Reset level

Claims (7)

A pixel having a photoelectric conversion element that photoelectrically converts light into a signal charge, a storage unit that temporarily stores the signal charge stored in the photoelectric conversion element, and a reset unit that removes the signal charge stored in the storage unit An imaging device comprising:
A comparison unit that compares a signal charge amount accumulated in the accumulation unit with a set value;
The image pickup apparatus, wherein the reset unit resets the storage unit at a different reset level based on a comparison result of the comparison unit.   The reset unit resets the storage unit to a first reset level when the signal charge amount stored in the storage unit is less than the set value, and the signal charge amount stored in the storage unit is 2. The imaging apparatus according to claim 1, wherein the storage unit is reset to a second reset level different from the first reset level when the set value is exceeded. The pixel further includes an output unit that converts the signal charge transferred from the photoelectric conversion element to the storage unit into a voltage and outputs the voltage.
The imaging device
A first accumulator that accumulates signal charges including an optical signal component and a noise component of the accumulator output from the output unit;
A second accumulator that accumulates signal charges including noise components at the time of reset of the accumulator output from the output unit;
A differential output unit that outputs a differential signal between a signal based on the signal charge accumulated in the first accumulation unit and a signal based on the signal charge accumulated in the second accumulation unit;
The imaging apparatus according to claim 2, further comprising:   The imaging apparatus according to claim 3, further comprising a noise signal monitor unit that outputs a signal based on the signal charge accumulated in the second accumulation unit.   When the level of the output signal from the noise signal monitoring unit is the first reset level, the output signal of the differential output unit is output as it is, and the level of the output signal from the noise signal monitoring unit is the second level. When the storage unit is at the reset level, a signal based on the signal charge stored in the storage unit is added to the output signal of the differential output unit when the storage unit is reset to the second reset level. The image pickup apparatus according to claim 4, further comprising a signal output unit that performs the operation. Optical system,
An imaging device according to any one of claims 1 to 5,
An imaging system comprising: A pixel having a photoelectric conversion element that photoelectrically converts light into a signal charge, a storage unit that temporarily stores the signal charge stored in the photoelectric conversion element, and a reset unit that removes the signal charge stored in the storage unit An imaging apparatus control method comprising:
A comparison step of comparing a signal charge amount accumulated in the accumulation unit with a set value;
A reset step of resetting the storage unit at a different reset level based on a comparison result in the comparison step;
A method for controlling an imaging apparatus, comprising:

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