JP2005012408A - Clamping circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that an abnormal pixel called as a white point and an OPB part are irradiated with strong light, and an average value shifts when light leaks if the number of pixels to be averaged is small when outputs of the OPB part are simply accumulated and the average value is used. <P>SOLUTION: A loop for feeding back a difference between an offset value (clamp value) added in an offset adjusting unit 11 and a clamping setting value which is previously stored in a storage part 14 to the offset adjusting unit 11 is formed by a loop digital filter 13, an adder 15 and a digital filter 16. The offset value is adjusted by feedback control. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

となる。
【００２７】
ここで、ｎはｎ番目の画素の信号を、ｘ［ｎ］，ｙ［ｎ］はそれぞれのフィルタの入力および出力を、ａは任意の係数を、Ｔは遅延を表している。それぞれ、クランプパルスがＨｉ，Ｌｏのときにフィルタを切り替えるようにしている。特に、ｃｌａｍｐ↓_−０はクランプパルスが立ち下がる直前を意味している。
【００２８】
さらに、図１のＡＤ変換器１２の後に任意の係数ｂを用いて、
ｙ［ｎ］＝ｂ・ｘ［ｎ］
で表されるデジタルアンプが追加されているとする。このように、デジタルアンプを追加しても本特許の本質は変わらない。
【００２９】
上述した具体例において、図１のブロック図を信号線図で表現したものが図２および図３である。ちなみに、オフセット調整器１１とＡＤ変換器１２は、単に信号の変換をするだけなので信号線図には影響がない。
【００３０】
クランプ設定値と実際に出力されたクランプ値をそれぞれｖ［ｎ］，ｗ［ｎ］とおくと、クランプパルスがＬｏのときは、クランプ設定値ｖ［ｎ］とクランプ値ｗ［ｎ］の関係、次のような差分方程式で表される。
ｗ［ｎ］／ｂ＝ｖ［ｎ］＋ａ・Ｔ・（ｗ［ｎ］／ｂ）
⇔ｗ［ｎ］＝ｂ・ｖ［ｎ］＋ａ・ｗ［ｎ］
【００３１】
また、クランプパルスがＨｉのときは、デジタルフィルタ１６の出力は、クランプパルスが立ち下がる直前の値、即ち前の画素の値を保持しているため、フィードバックループが切れた状態になり、クランプ値の制御が行われない。この状態では、クランプ設定値ｖ［ｎ］とクランプ値ｗ［ｎ］の関係は下記の式のようになる。

【００３２】
この例でのクランプパルス、クランプ設定値および実際に出力されたクランプ値の関係を示したのが図４の波形図である（ａ＝０．８８，ｂ＝０．１２）。固体撮像装置がＯＰＢ部の映像信号を出力している期間に合わせて、クランプパルスをＬｏにしている。その場合、図２の信号線図になり、クランプ値がクランプ設定値に近づくようにクランプ回路に制御がかかる。クランプパルスがＨｉのときは、図３の信号線図に示すようにクランプ回路の制御を切り、クランプ値の制御を行わないため、クランプ値は一定値を保っている。
【００３３】
さらに、クランプパルスがＬｏになるたびにクランプ回路の制御が行われ、クランプ値の制御を開始して４行目でクランプ値の変化が終了し、クランプ値が安定する。通常の使用時では、このように数行から数十行に亘ってクランプ値を安定させる方法を用いる（本明細書中では、このような動作を「通常クランプモード」と記す）。これはクランプ値による変化のため、画面に急激な変化をもたらさないためである。
【００３４】
同じ信号線図において、ａ＝−０．５，ｂ＝１．５の場合のクランプパルス、クランプ設定値および実際に出力されたクランプ値の関係を示したのが図５の波形図である。この場合、図４の波形図に比べてクランプ値の変化は激しくリンギングしているが、その分だけ収束が速くなり、数行目でクランプ値が安定する。通常、クランプ値が大きく変化するのは、電源投入時やスタンバイからの復帰時など急激に動作状態にした場合（本明細書中では、このような動作時を「初期動作時」と記す）や、ＰＧＡ（プログラマブルゲインアンプ）の増幅率を切り替えてオフセット値が変化したときであるから、その場合には、このようにクランプ値の収束を速くすれば良い（本明細書中では、このような動作モードを「高速クランプモード」と記す）。
【００３５】
固体撮像装置を撮像デバイスとして用いたデジタルスチルカメラなどでの撮影の際には、リアルタイムで撮影した映像を確認するモニタリングモードと、実際に映像をメモリなどに取り込むスチルモードとを切り替えることがある。このとき、モニタリングモードでは被写体に追従するため高速クランプモードでのクランプ値の制御を行い、スチルモードでは同一の画面でクランプ値が変化するのを防ぐために通常クランプモードでの制御を行うようにすれば良い。また、ＯＰＢ部の雑音に対してはクランプ値の制御を行わないようにする。
【００３６】
この高速クランプモードと通常クランプモードの切り替えは、図６に示すように、例えば後段の信号処理系から与えられるフラグ信号によって行うことができる。なお、図６と図１２の対応関係において、オフセット調整器１１は、ＰＧＡ１０２が持つ機能の一部としての位置付けとなる。固体撮像装置１７のＯＰＢ部から出力され、オフセット調整器１１でオフセット値が付加されたアナログ映像信号は、ＡＤ変換器１２でデジタル変換された後、ＤＳＰ１８で各種の信号処理が施されることになる。
【００３７】
図６の例では、高速クランプモードと通常クランプモードの切り替えを外部から与えられるフラグ信号によって行うとしたが、ループデジタルフィルタ１３の入力ｘ［ｎ］に基づいて自動的にクランプ値の制御の切り替えを行うこともできる。そのクランプ制御の具体例を図７のフローチャートを用いて説明する。
【００３８】
図７のフローチャートにおいて、クランプパルスがＬｏのときにクランプ制御を開始し、先ず、ループデジタルフィルタ１３の入力ｘ［ｎ］がある閾値ｔｈよりも大きいか否かを判断し（ステップＳ１１）、入力がｘ［ｎ］閾値ｔｈよりも大きい場合は、クランプ値の制御を行わない（ステップＳ１２）。具体的には、ｘ［ｎ］＞ｔｈのとき、ループデジタルフィルタ１３からはある値ｆｌａｇが出力される。その場合、デジタルフィルタ１６では、図３の信号線図に示すようにクランプ回路の制御を切り、クランプ値の制御を行わないようにする。
【００３９】
このように、ループデジタルフィルタ１３の入力ｘ［ｎ］をある閾値ｔｈで判定し、閾値ｔｈよりも大きいときにはクランプ値の制御を行わず、クランプ値を変化させないようにするのは、固体撮像装置のＯＰＢ部に白点や光の漏れ込みなどがあり、固体撮像装置から明らかに異常な雑音（出力）があった際にこの雑音の影響をなくすためである。
【００４０】
ループデジタルフィルタ１３の入力ｘ［ｎ］が閾値ｔｈ以下のときには、初期動作時であるか、あるいはＰＧＡの増幅率が変化したか否かを判断し（ステップＳ１３）、初期動作時あるいはＰＧＡの増幅率変化であれば、被写体に追従するため高速クランプモードでのクランプ値の制御に切り替え（ステップＳ１４）、そうでなければ同一の画面でクランプ値が変化するのを防ぐために通常クランプモードでのクランプ値の制御に切り替える（ステップＳ１５）。
【００４１】
このように、ループデジタルフィルタ１３の入力ｘ［ｎ］に基づいて自動的にクランプ値の制御の切り替えを行うことにより、雑音などの影響でＯＰＢ部の信号が急激に変化した際にはクランプ値が変化しないようにすることができるとともに、デジタルスチルカメラなどでの撮影の際は、モニタリングモードやスチルモードの各動作モードに対応した最適なクランプ値を設定することができることになる。
【００４２】
この場合のデジタルフィルタ１６およびループデジタルフィルタ１３の各出力ｙ［ｎ］はそれぞれ月の差分方程式で表される。
デジタルフィルタ１６については、
▲１▼クランプパルスが低レベル（以下、「Ｌｏ」と記す）かつｘ［ｎ］≠ｆｌａｇのとき、
ｙ［ｎ］＝ｘ［ｎ］
▲２▼クランプパルスが高レベル（以下、「Ｈｉ」と記す）もしくはｘ［ｎ］＝ｆｌａｇのとき、
ｙ［ｎ］＝ｘ［ｃｌａｍｐ↓_−０］
となる。
【００４３】
ループデジタルフィルタ１３については、
▲１▼クランプパルスがＨｉもしくはＬｏかつｘ［ｎ］≦閾値ｔｈのとき、

▲２▼クランプパルスがＬｏかつｘ［ｎ］＞閾値ｔｈのとき、
ｙ［ｎ］＝ｆｌａｇ
となる。
【００４４】
また、上記の例では、ループデジタルフィルタ１３の入力ｘ［ｎ］に基づいてクランプ値の制御の切り替えを行うとしたが、撮影した被写体や画像に基づいてクランプ値を制御することも可能である。例えば、ＤＳＰ１７などにおいて、撮影した被写体や画像の信号レベルの平均値とある基準値とを比較し、平均値が基準値よりも高い場合は通常のクランプ値で、平均値が基準値よりも低い場合にはクランプ値にオフセットを余分に与えることで、信号処理やディスプレイでの表示、プリントアウトなどでは通常黒くつぶれてしまう暗い被写体や画像を、黒くつぶれないようにし、鮮明な画像を得ることができる。
【００４５】
具体的には、図６に示すように、後段の信号処理系から与えられるフラグ信号をループデジタルフィルタ１３、加算器１５およびデジタルフィルタ１６にそれぞれ与え、信号処理で平均化した信号レベルを基準値と比較し、その大小に応じてフラグ信号を切り替えることにより、クランプ値のオフセットを調整することができる。
【００４６】
さらに、固体撮像装置には通常信号と高ダイナミックレンジ信号の２種類の信号を出力できる構成のものがあるが、その際にもフラグ信号をたてることで、通常信号と高ダイナミックレンジ信号を切り替えることができる。その際に、図８に示すように、固体撮像装置１７の動作を制御するコントローラ１９からのフラグ信号を用いて、通常信号出力時と高ダイナミックレンジ信号出力時で、ループデジタルフィルタ１３、加算器１５およびデジタルフィルタ１６の各動作を切り替えることにより、それぞれの出力に応じたクランプ値の制御をかけることができる。
【００４７】
このフラグ信号による制御は、明るい被写体と暗い被写体を同時に撮影した際に、暗い被写体など画面の一部分のみについて増幅率を変える場合などにも適応できる。
【００４８】
図９は、図１の構成を伝達関数で表した信号線図であり、図中、図１と同等部分には同一符号を付して示している。ここで、加算器１５に入力されるループデジタルフィルタ１３の出力に負号をつけているが、ループデジタルフィルタ１３の伝達関数に負号をつけることと等価であるため、本特許の本質性が失われることはない。
【００４９】
デジタルフィルタ１６、オフセット調整器１１／ＡＤ変換器１２、ループデジタルフィルタ１３の伝達関数をそれぞれ、Ａ，Ｂ，Ｇとおくと、クランプ設定値ｘと実際に出力されるクランプ値ｙとの関係ｆは、
【数１】

と表すことができる。
【００５０】
ここで、オフセット調整器１１／ＡＤ変換器１２の伝達関数が、Ｂ→Ｂ＋ΔＢに変化したとすると、ｆの変化分Δｆは、
【数２】

となる。
【００５１】
そのため、
【数３】

となる。
【００５２】
ここで、
【数４】

とすると、
【数５】

となる。
【００５３】
その結果、デジタルフィルタ１６の伝達関数Ａを十分大きくとればαが十分小さくなるため、オフセット調整器１１／ＡＤ変換器１２の特性に誤差があったとしても、当該誤差がクランプ値の変化に影響を及ぼすことはない。
【００５４】
上述したように、第１実施形態に係るクランプ回路においては、経年変化、温度変化、バラツキなどがないループデジタルフィルタ１３およびデジタルフィルタ１６を含むループでのフィードバック制御の回路構成を採っているため、経年変化、温度変化、バラツキなどに強く、被写体などの状況に応じたクランプをかけることができるクランプ回路を実現できる。
【００５５】
特に、ループを形成する各回路部、即ちループデジタルフィルタ１３、加算器１５およびデジタルフィルタ１６などの特性に誤差があったとしても、フィードバック制御であることから、適切なクランプ処理を行うことができる。また、アナログアンプ構成のオフセット調整器１１でクランプ補正を行う構成を採っているため、後段のＡＤ変換器１２のダイナミックレンジを狭めることもない。ちなみに、デジタル演算でクランプ補正を行う場合には、映像信号がクランプ補正によって直流電位がレベルシフトした分だけ、後段のＡＤ変換器１２のダイナミックレンジを狭めることになる。
【００５６】
ただし、本発明は、アナログ処理でクランプ補正を行う構成に限られるものではなく、オフセット調整手段の前段に、入力される映像信号をデジタル変換するＡＤ変換器を設けて、当該オフセット調整手段においてデジタル演算でクランプ補正を行う構成を採ることも可能である。この場合でも、ループ内にデジタルフィルタを含むことに伴う上記効果や、フィードバック制御であることに伴う上記効果を得ることができる。
【００５７】
［第２実施形態］
図１０は、本発明の第２実施形態に係るクランプ回路の構成を示すブロック図であり、図中、図１と同等部分には同一符号を付して示している。
【００５８】
本実施形態に係るクランプ回路は、ループデジタルフィルタ１３およびデジタルフィルタ１６をそれぞれ含む例えば２つのフィードループを有する構成となっている。具体的には、格納部１４とオフセット調整器１１との間に、加算器１５−１、デジタルフィルタ１６−１、加算器１５−２およびデジタルフィルタ１６−２が直列に接続され、ＡＤ変換器１２の出力がループデジタルフィルタ１３−１，１３−２を介して加算器１５−１に供給されるとともに、ループデジタルフィルタ１３−２を介して加算器１５−２に供給される構成となっている。
【００５９】
上記構成の第２実施形態に係るクランプ回路は、第１実施形態に係るクランプ回路とはフィードバックループを２つ有する点で相違するものの、基本的な回路動作は同じである。ただし、フィードバックループを２つ持っている分だけ、第１実施形態に係るクランプ回路に比べてより多彩な制御を行うことができる。例えば、白点がＯＰＢ部に存在した際の動作例を示す図１１から明らかなように、突発的な白点が存在したとしても、２つのフィードバックループによってクランプ値の制御を行うことで、より安定したクランプ値を得ることができる。
【００６０】
なお、本実施形態では、フィードバックループを２つ設ける場合を例に挙げて説明したが、これに限られるものではなく、３つ以上設けても良く、その数が多くなる程、より多彩な制御を行うことができる。
【００６１】
また、上記各実施形態では、オフセット調整器１１に入力されるアナログ映像信号として、固体撮像装置のＯＰＢ部から出力される映像信号を用いる場合を例に挙げて説明したが、本発明はこの適用例に限られるものではなく、映像信号のクランプ回路全般に適用することができる。
【００６２】
【発明の効果】
以上説明したように、本発明によるクランプ回路によれば、経年変化、温度変化、バラツキなどがないデジタルフィルタを含むループでのフィードバック制御の回路構成を採っていることで、経年変化、温度変化、バラツキなどに強く、被写体などの状況に応じたクランプをかけることができ、しかもループを形成する各回路部の特性に誤差があったとしても、フィードバック制御であることから、適切なクランプ処理を行うことができる。
【図面の簡単な説明】
【図１】本発明の第１実施形態に係るクランプ回路の構成を示すブロック図である。
【図２】第１実施形態に係るクランプ回路におけるクランプパルス＝Ｌｏのときの信号線図である。
【図３】第１実施形態に係るクランプ回路におけるクランプパルス＝Ｈｉのときの信号線図である。
【図４】ａ＝０．８８，ｂ＝０．１２のときのクランプパルス、クランプ設定値および実際のクランプ値の関係を示す波形図である。
【図５】ａ＝０．５，ｂ＝１．５のときのクランプパルス、クランプ設定値および実際のクランプ値の関係を示す波形図である。
【図６】外部からフラグ信号でクランプ制御を行う場合の構成例を示すブロック図である。
【図７】ループデジタルフィルタの入力ｘ［ｎ］に基づいてクランプ制御を行う場合の手順の一例を示すフローチャートである。
【図８】コントローラからフラグ信号でクランプ制御を行う場合の構成例を示すブロック図である。
【図９】第１実施形態に係るクランプ回路を伝達関数で表記したブロック図である。
【図１０】本発明の第２実施形態に係るクランプ回路の構成を示すブロック図である。
【図１１】第２実施形態に係るクランプ回路において、白点がＯＰＢ部に存在した際の動作例でのクランプパルス、クランプ設定値および実際のクランプ値の関係を示す波形図である。
【図１２】固体撮像装置の信号処理系の一般的な構成例を示すブロック図である。
【図１３】固体撮像装置の入射光量と映像信号との関係を示す特性図である。
【図１４】固体撮像装置のＯＰＢ部についての説明図である。
【図１５】映像信号とクランプパルスとの関係を示す波形図である。
【図１６】ＯＰＢ部が周期的な場合のクランプ前およびクランプ後の映像信号を示す波形図である。
【符号の説明】
１１…オフセット調整器、１２…ＡＤ変換器、１３，１３−１，１３−２…ループデジタルフィルタ、１４…格納部、１５，１５−１，１５−２…加算器、１６，１６−１，１６−２…デジタルフィルタ、１７…固体撮像装置、１８…ＤＳＰ、１９…コントローラ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clamp circuit for a video signal, and more particularly to a clamp circuit suitable for use in taking an offset variation of a video signal output from a light-shielded pixel portion of a solid-state imaging device.
[0002]
[Prior art]
2. Description of the Related Art In recent years, solid-state imaging devices represented by CCD (Charge Coupled Device) image sensors and CMOS image sensors have been widely used as image input devices such as various portable terminal devices, digital still cameras, and digital video cameras. In particular, since a solid-state imaging device is superior in portability compared to a conventional imaging tube, it may be used for shooting every scene with a single unit.
[0003]
In general, in imaging with a solid-state imaging device, as shown in FIG. 12, a video signal captured by the solid-state imaging device 101 is amplified by a programmable gain amplifier (PGA) 102 or the like disposed at the subsequent stage of the solid-state imaging device 101. The digital signal is converted into a digital signal by the AD converter 103, and then various signal processing is performed by a DSP (Digital Signal Processor) 104 or the like.
[0004]
In the solid-state imaging device 101, in order to shoot a bright subject from a dark subject, such as shooting a dark subject indoors illuminated by indirect lighting or the like, or shooting a bright subject outdoors under sunlight, etc. The amplification factor of the PGA 102 may range from −several dB to hundreds of tens of dB.
[0005]
In the video signal of the solid-state imaging device 101, primary colors (R (red), G (green), B (blue)) corresponding to the color filter of the solid-state imaging device 101, and complementary colors (C (cyan), M (magenta)). , Y (yellow)), the black level of the luminance signal obtained by signal processing, and the colorless level of the color difference signal need to be fixed to a certain reference value. This is because, if the reference value is not fixed, for example, when the same black subject is photographed, the appearance of black is different.
[0006]
By the way, if the amplification factor of the PGA 102 is changed according to the subject to be photographed, the offset value of the solid-state imaging device 101, the offset value of the PGA 102 itself, or the like changes. FIG. 13 shows the relationship between the amount of light input to the solid-state imaging device 101 and the video signal. As is clear from the figure, when the amplification factor is large, the offset value of the solid-state imaging device 101 is also amplified. For this reason, the black level or the like in the above-described color signal is shifted due to a change in the amplification factor of the PGA 102, and there is no problem when the amplification factor of the PGA 102 is small. The subject may appear whitish.
[0007]
Furthermore, solid-state imaging devices are manufactured in the semiconductor manufacturing process, but there are individual differences in the offset values of the solid-state imaging devices due to manufacturing variations such as etching and lithography in each circuit, or the same solid-state imaging device. Even if it exists, there is a problem that the offset value varies every time it is used due to temperature change, aging change, noise, and the like.
[0008]
Usually, in order to prevent such a problem of deterioration of a captured image due to an offset value, as shown in FIG. 14, in a pixel unit 106 in which pixels 105 are two-dimensionally arranged in a matrix, some pixels 105 are made of aluminum or the like. A portion (hereinafter referred to as an “OPB (optical black) portion”) 107 shielded from light by the wiring layer is prepared, and the video signal from the OPB portion 107 is offset with respect to the video signal so that the video signal is always a constant value. Measures to add a value (hereinafter referred to as “clamp value”) are taken. By taking such a measure, the video signal of the OPB unit 107 always has a certain reference value, so that it is possible to prevent deterioration of the captured image due to a change in the black level or the like in the color signal as described above.
[0009]
A circuit that adds a clamp value (offset value) to a video signal is called a clamp circuit. FIG. 15 shows the waveforms of the nth row and the (n + 1) th row of the video signal on the time axis. In the clamp circuit, a process of adding a clamp value is performed so that the signal of the OPB unit 112 that is shielded from light is used as a reference of the video signal. Usually, the signal of the OPB unit 107 is provided in the blanking period of the video signal. Then, a period (indicated by a low level period in FIG. 15) in which a clamp value is applied by a clamp pulse synchronized with the blanking period is set.
[0010]
Conventionally, in this type of clamp circuit, the outputs from the individual pixels in the OPB section are simply integrated to average the variation between the pixels in the OPB section, and then the clamp value to be added to the video signal is calculated from this average value. The obtained clamp value is added to the video signal (for example, see Patent Document 1).
[0011]
[Patent Document 1]
Japanese Patent Laid-Open No. 10-79893 (particularly paragraphs 0009 to 0012 and FIG. 1)
[0012]
[Problems to be solved by the invention]
However, since the clamp circuit according to the above-described conventional example uses an average value obtained by simply integrating the outputs of the OPB portion, if the number of pixels to be averaged is small, the OPB portion is always at a maximum due to a leakage current or the like. Abnormal pixels that continue to output signal values (referred to as white spots because the signal value is large like a white object) or the OPB part is exposed to strong light and the light leaks out. There is. Therefore, in order to obtain a correct clamp value (average value), more pixels must be secured as the OPB portion. In this case, the OPB part must be read for a long time in order to obtain the clamp value, and it takes time to converge the clamp value.
[0013]
Further, in the clamp by normal integration, there is only one method of applying the clamp value. For example, when the gain of the PGA changes abruptly and the clamp value changes accordingly, the clamp attempts to follow this. If the value is changed abruptly (for example, the integration parameter is reduced), the clamp value also changes abruptly when the signal of the OPB section changes due to the influence of noise or the like. For example, such a problem may occur when there is periodicity in the variation between pixels in the OPB portion, and when the periodicity also appears in the clamp value.
[0014]
FIG. 16 shows a waveform when clamping is performed when the video output of the OPB portion becomes periodic for each row in the nth row and the (n + 1) th row. If a different clamp value is added for each row, the output of the effective pixel portion in which the pixel signal is actually used as a video signal becomes periodic, causing a problem that a striped pattern is formed in the video. However, when the change of the clamp value is moderated, the captured image is deteriorated without being able to follow the change of the gain of the PGA.
[0015]
In particular, in the clamp circuit described in Patent Document 1, the average of one line is obtained by calculating the signal level of the input video signal in the OPB period with an accumulator, and the average of the obtained signal level in the OPB period is obtained by using an IIR filter. Since there is a feed forward configuration that subtracts the calculation result from the input video signal with a subtractor, if there is an error in the characteristics of the accumulator, IIR filter or subtractor, an appropriate clamping process is performed. This cannot be performed, and the video signal after the clamping process includes an error.
[0016]
The present invention has been made in view of the above problems, and its object is to provide a clamp circuit that is resistant to secular change, temperature change, variation, and the like and can be clamped according to the situation of the subject. It is to provide.
[0017]
[Means for Solving the Problems]
The clamp circuit according to the present invention includes an offset adjustment unit that adds an offset value to an input video signal, a first digital filter that performs a filtering process on the video signal to which the offset value is added by the offset adjustment unit, An adding means for adding a preset clamp setting value and the output of the first digital filter; and a second digital filter for filtering the output of the adding means; and an output of the second digital filter. The offset value added by the offset adjusting means is controlled based on the above.
[0018]
In the clamp circuit having the above configuration, the first digital filter, the adding unit, and the second digital filter are feedback for feeding back the difference between the offset value (clamp value) added by the offset adjusting unit and the clamp setting value to the offset adjusting unit. A loop is formed. Since the digital filter forming this loop has no secular change, temperature change, variation, etc., it is strong against secular change, temperature change, variation, etc., and can be clamped according to the situation of the subject. In addition, even if there is an error in the characteristics of each circuit unit forming the loop, since the feedback control is performed, an appropriate clamping process can be performed while correcting the error.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0020]
[First Embodiment]
FIG. 1 is a block diagram showing a configuration of a clamp circuit according to the first embodiment of the present invention. As is clear from FIG. 1, the clamp circuit according to the present embodiment includes an offset adjuster 11, an AD converter 12, a loop digital filter 13, a storage unit 14, an adder 15, and a digital filter 16. . Here, a case where a video signal output from a light-shielded pixel unit (OPB unit) of the solid-state imaging device is used as an analog video signal input to the offset adjuster 11 will be described as an example.
[0021]
The offset adjuster 11 includes an operational amplifier OP, an input resistor R11 that applies an analog video signal to the inverting (−) input terminal of the operational amplifier OP, and a feedback resistor R12 that is connected between the output terminal and the inverting input terminal of the operational amplifier OP. The offset setting unit 110 is connected to the non-inverting (+) input terminal of the operational amplifier OP, and the offset value set by the offset setting unit 17 is added to the input analog video signal. .
[0022]
The AD converter 12 digitally converts the analog video signal to which the offset value is added by the offset adjuster 11. The loop digital filter 13 performs a filtering process for giving a certain characteristic to the output of the AD converter 12. The storage unit 14 includes a ROM, a register, and the like, and stores a preset clamp setting value. The adder 15 adds (including subtraction) the clamp setting value stored in the storage unit 14 and the output of the loop digital filter 13. The digital filter 16 performs a filtering process for giving a certain characteristic to the output of the adder 15 and supplies it to the offset adjuster 11.
[0023]
As described above, the clamp circuit according to the present embodiment that realizes the clamp process by feedback control in a loop including the two digital filters of the loop digital filter 13 and the digital filter 16 is configured. A clamp pulse is input to both the loop digital filter 13 and the digital filter 16. Here, the loop digital filter 13 and the digital filter 16 are arbitrary filter circuits configured by logic circuits.
[0024]
In the offset adjuster 11, for example, the offset setting unit 110 is connected between the current source I11 connected between the power supply Vdd and the inverting input terminal of the operational amplifier OP, and between the inverting input terminal of the operational amplifier OP and the ground. And an offset value is set in accordance with the output of the digital filter 16. Specifically, when the output of the digital filter 16 is smaller than 0, a current is supplied to the inverting input terminal of the operational amplifier OP by the current source I11. Conversely, when the output of the digital filter 16 is larger than 0, the current source By extracting current from the inverting input terminal of the operational amplifier OP with I12, an offset value to be added to the input analog video signal is set.
[0025]
Next, the operation principle of the clamp circuit according to this embodiment shown in FIG. 1 will be described. Here, the case where the digital filter 16 and the loop digital filter 13 are each expressed by the following difference equation will be specifically described as an example.
[0026]
For the digital filter 16,
(1) When the clamp pulse is low level (hereinafter referred to as “Lo”)
y [n] = x [n]
(2) When the clamp pulse is at a high level (hereinafter referred to as “Hi”)
y [n] = x [clamp ↓ _-0 ]
As for the loop digital filter 13,

It becomes.
[0027]
Here, n represents the signal of the nth pixel, x [n] and y [n] represent the input and output of each filter, a represents an arbitrary coefficient, and T represents the delay. Each filter is switched when the clamp pulse is Hi or Lo. In particular, clamp ↓ _-0 Means just before the clamp pulse falls.
[0028]
Furthermore, an arbitrary coefficient b is used after the AD converter 12 in FIG.
y [n] = b · x [n]
It is assumed that a digital amplifier represented by is added. Thus, even if a digital amplifier is added, the essence of this patent does not change.
[0029]
In the specific example described above, the block diagram of FIG. 1 is represented by a signal diagram in FIGS. 2 and 3. Incidentally, since the offset adjuster 11 and the AD converter 12 simply convert signals, the signal diagram is not affected.
[0030]
When the clamp set value and the actually output clamp value are set as v [n] and w [n], respectively, when the clamp pulse is Lo, the relationship between the clamp set value v [n] and the clamp value w [n]. It is expressed by the following differential equation.
w [n] / b = v [n] + a.T. (w [n] / b)
⇔w [n] = b · v [n] + a · w [n]
[0031]
When the clamp pulse is Hi, the output of the digital filter 16 holds the value immediately before the clamp pulse falls, that is, the value of the previous pixel, so that the feedback loop is cut off, and the clamp value Is not controlled. In this state, the relationship between the clamp setting value v [n] and the clamp value w [n] is as follows.

[0032]
FIG. 4 is a waveform diagram (a = 0.88, b = 0.12) showing the relationship between the clamp pulse, the clamp set value, and the actually output clamp value in this example. The clamp pulse is set to Lo in accordance with the period during which the solid-state imaging device outputs the video signal of the OPB unit. In that case, the signal diagram of FIG. 2 is obtained, and the clamp circuit is controlled so that the clamp value approaches the clamp setting value. When the clamp pulse is Hi, the clamp circuit is not controlled as shown in the signal diagram of FIG. 3 and the clamp value is not controlled. Therefore, the clamp value is kept constant.
[0033]
Further, every time the clamp pulse becomes Lo, the clamp circuit is controlled, the clamp value control is started, the change of the clamp value is finished in the fourth row, and the clamp value is stabilized. In normal use, a method of stabilizing the clamp value over several lines to several tens of lines is used (in this specification, such an operation is referred to as “normal clamp mode”). This is because a change due to the clamp value does not cause a sudden change in the screen.
[0034]
In the same signal diagram, the waveform diagram of FIG. 5 shows the relationship between the clamp pulse, the clamp set value, and the actually output clamp value when a = −0.5 and b = 1.5. In this case, the change in the clamp value is ringing more intensely than in the waveform diagram of FIG. 4, but the convergence becomes faster by that amount, and the clamp value is stabilized in the several lines. Usually, the clamp value changes greatly when the power supply is turned on or when the operation state is abruptly restored such as when returning from standby (in this specification, such operation time is referred to as “initial operation time”). , When the offset value changes by switching the gain of the PGA (programmable gain amplifier), in this case, the convergence of the clamp value may be accelerated (in this specification, The operation mode is described as “High-speed clamp mode”).
[0035]
When shooting with a digital still camera or the like using a solid-state imaging device as an imaging device, a monitoring mode for checking a video shot in real time and a still mode for actually reading the video into a memory may be switched. At this time, in the monitoring mode, the clamp value is controlled in the high-speed clamp mode in order to follow the subject, and in the still mode, the control in the normal clamp mode is performed to prevent the clamp value from changing on the same screen. It ’s fine. Also, the clamp value is not controlled for the noise in the OPB section.
[0036]
The switching between the high-speed clamp mode and the normal clamp mode can be performed by, for example, a flag signal given from a subsequent signal processing system as shown in FIG. 6 and 12, the offset adjuster 11 is positioned as a part of the function of the PGA 102. The analog video signal output from the OPB unit of the solid-state imaging device 17 and added with the offset value by the offset adjuster 11 is digitally converted by the AD converter 12 and then subjected to various signal processing by the DSP 18. Become.
[0037]
In the example of FIG. 6, the high-speed clamp mode and the normal clamp mode are switched by a flag signal given from the outside, but the clamp value control is automatically switched based on the input x [n] of the loop digital filter 13. Can also be done. A specific example of the clamp control will be described with reference to the flowchart of FIG.
[0038]
In the flowchart of FIG. 7, the clamp control is started when the clamp pulse is Lo. First, it is determined whether or not the input x [n] of the loop digital filter 13 is larger than a certain threshold th (step S11). Is greater than the x [n] threshold th, the clamp value is not controlled (step S12). Specifically, when x [n]> th, the loop digital filter 13 outputs a certain value flag. In that case, in the digital filter 16, as shown in the signal diagram of FIG. 3, the control of the clamp circuit is cut off so that the clamp value is not controlled.
[0039]
As described above, the solid-state imaging device is configured to determine the input x [n] of the loop digital filter 13 with a certain threshold value th and not to control the clamp value when the value is larger than the threshold value th and not to change the clamp value. This is to eliminate the influence of this noise when there is a white spot or light leaking in the OPB portion of the solid-state imaging device and there is clearly abnormal noise (output) from the solid-state imaging device.
[0040]
When the input x [n] of the loop digital filter 13 is less than or equal to the threshold th, it is determined whether it is during initial operation or whether the PGA gain has changed (step S13), and during initial operation or PGA amplification. If the rate changes, the control is switched to the clamp value control in the high-speed clamp mode in order to follow the subject (step S14). Otherwise, the clamp value in the normal clamp mode is used to prevent the clamp value from changing on the same screen. Switch to value control (step S15).
[0041]
In this way, by automatically switching the control of the clamp value based on the input x [n] of the loop digital filter 13, when the signal of the OPB section changes suddenly due to noise or the like, the clamp value is changed. Can be prevented from changing, and an optimum clamp value corresponding to each operation mode of the monitoring mode or the still mode can be set when photographing with a digital still camera or the like.
[0042]
In this case, each output y [n] of the digital filter 16 and the loop digital filter 13 is expressed by a monthly difference equation.
For the digital filter 16,
(1) When the clamp pulse is at a low level (hereinafter referred to as “Lo”) and x [n] ≠ flag,
y [n] = x [n]
(2) When the clamp pulse is at a high level (hereinafter referred to as “Hi”) or x [n] = flag,
y [n] = x [clamp ↓ _-0 ]
It becomes.
[0043]
For the loop digital filter 13,
(1) When the clamp pulse is Hi or Lo and x [n] ≦ threshold th,

(2) When the clamp pulse is Lo and x [n]> threshold th,
y [n] = flag
It becomes.
[0044]
In the above example, the control of the clamp value is switched based on the input x [n] of the loop digital filter 13, but the clamp value can also be controlled based on the photographed subject or image. . For example, in the DSP 17 or the like, the average value of the signal level of the photographed subject or image is compared with a certain reference value. If the average value is higher than the reference value, it is a normal clamp value, and the average value is lower than the reference value. In some cases, an extra offset can be added to the clamp value to prevent dark subjects and images that would normally be crushed black during signal processing, display on the display, printout, etc., and obtain a clear image. it can.
[0045]
Specifically, as shown in FIG. 6, the flag signal given from the signal processing system at the subsequent stage is given to the loop digital filter 13, the adder 15 and the digital filter 16, respectively, and the signal level averaged by the signal processing is used as a reference value. The offset of the clamp value can be adjusted by switching the flag signal according to the magnitude of the signal.
[0046]
Furthermore, some solid-state imaging devices have a configuration capable of outputting two types of signals, a normal signal and a high dynamic range signal. In this case, a normal signal and a high dynamic range signal are switched by generating a flag signal. be able to. At that time, as shown in FIG. 8, using a flag signal from the controller 19 that controls the operation of the solid-state imaging device 17, a loop digital filter 13 and an adder are used when a normal signal is output and when a high dynamic range signal is output. By switching the operations of the digital filter 15 and the digital filter 16, it is possible to control the clamp value according to the respective outputs.
[0047]
The control by the flag signal can be applied to a case where the amplification factor is changed only for a part of the screen such as a dark subject when a bright subject and a dark subject are simultaneously photographed.
[0048]
FIG. 9 is a signal diagram showing the configuration of FIG. 1 as a transfer function. In FIG. 9, the same parts as those in FIG. Here, a negative sign is attached to the output of the loop digital filter 13 input to the adder 15, but this is equivalent to attaching a negative sign to the transfer function of the loop digital filter 13. There is no loss.
[0049]
When the transfer functions of the digital filter 16, the offset adjuster 11 / AD converter 12, and the loop digital filter 13 are respectively A, B, and G, the relationship between the clamp setting value x and the clamp value y that is actually output f Is
[Expression 1]

It can be expressed as.
[0050]
Here, if the transfer function of the offset adjuster 11 / AD converter 12 changes from B to B + ΔB, the change Δf in f is
[Expression 2]

It becomes.
[0051]
for that reason,
[Equation 3]

It becomes.
[0052]
here,
[Expression 4]

Then,
[Equation 5]

It becomes.
[0053]
As a result, if the transfer function A of the digital filter 16 is sufficiently large, α is sufficiently small. Therefore, even if there is an error in the characteristics of the offset adjuster 11 / AD converter 12, the error affects the change in the clamp value. Will not affect.
[0054]
As described above, the clamp circuit according to the first embodiment employs a circuit configuration for feedback control in a loop including the loop digital filter 13 and the digital filter 16 that are free from secular change, temperature change, variation, and the like. A clamp circuit that is resistant to changes over time, temperature changes, variations, and the like and can be clamped according to the situation of the subject or the like can be realized.
[0055]
In particular, even if there is an error in the characteristics of each circuit unit forming the loop, that is, the loop digital filter 13, the adder 15, and the digital filter 16, since the feedback control is performed, an appropriate clamping process can be performed. . In addition, since the offset correction unit 11 having an analog amplifier configuration performs the clamp correction, the dynamic range of the AD converter 12 at the subsequent stage is not narrowed. Incidentally, when the clamp correction is performed by digital calculation, the dynamic range of the AD converter 12 at the subsequent stage is narrowed by the amount that the DC potential of the video signal is level-shifted by the clamp correction.
[0056]
However, the present invention is not limited to a configuration in which clamp correction is performed by analog processing, and an AD converter that digitally converts an input video signal is provided before the offset adjustment unit, and the offset adjustment unit performs digital conversion. It is also possible to adopt a configuration for performing clamp correction by calculation. Even in this case, it is possible to obtain the above-described effect associated with including a digital filter in the loop and the above-described effect associated with feedback control.
[0057]
[Second Embodiment]
FIG. 10 is a block diagram showing a configuration of a clamp circuit according to the second embodiment of the present invention. In FIG. 10, the same parts as those in FIG.
[0058]
The clamp circuit according to this embodiment is configured to have, for example, two feed loops each including the loop digital filter 13 and the digital filter 16. Specifically, an adder 15-1, a digital filter 16-1, an adder 15-2, and a digital filter 16-2 are connected in series between the storage unit 14 and the offset adjuster 11, and an AD converter 12 outputs are supplied to the adder 15-1 via the loop digital filters 13-1 and 13-2, and are also supplied to the adder 15-2 via the loop digital filter 13-2. Yes.
[0059]
The clamp circuit according to the second embodiment configured as described above is different from the clamp circuit according to the first embodiment in that it has two feedback loops, but the basic circuit operation is the same. However, since there are two feedback loops, more various controls can be performed as compared with the clamp circuit according to the first embodiment. For example, as is clear from FIG. 11 showing an operation example when a white spot exists in the OPB portion, even if a sudden white spot exists, the clamp value is controlled by two feedback loops. A stable clamp value can be obtained.
[0060]
In the present embodiment, the case where two feedback loops are provided has been described as an example. However, the present invention is not limited to this, and three or more may be provided. It can be performed.
[0061]
In each of the above-described embodiments, the case where the video signal output from the OPB unit of the solid-state imaging device is used as the analog video signal input to the offset adjuster 11 has been described as an example. The present invention is not limited to the example, and can be applied to a video signal clamping circuit in general.
[0062]
【The invention's effect】
As described above, according to the clamp circuit according to the present invention, by adopting a circuit configuration of feedback control in a loop including a digital filter free from aging, temperature change, variation, etc., aging, temperature change, Resistant to variations, etc., can be clamped according to the situation of the subject, etc., and even if there is an error in the characteristics of each circuit section forming the loop, it is feedback control, so appropriate clamping processing is performed be able to.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a clamp circuit according to a first embodiment of the present invention.
FIG. 2 is a signal line diagram when a clamp pulse = Lo in the clamp circuit according to the first embodiment.
FIG. 3 is a signal line diagram when clamp pulse = Hi in the clamp circuit according to the first embodiment;
FIG. 4 is a waveform diagram showing a relationship between a clamp pulse, a clamp set value, and an actual clamp value when a = 0.88 and b = 0.12.
FIG. 5 is a waveform diagram showing a relationship between a clamp pulse, a clamp set value, and an actual clamp value when a = 0.5 and b = 1.5.
FIG. 6 is a block diagram illustrating a configuration example in the case where clamp control is performed with a flag signal from the outside.
FIG. 7 is a flowchart illustrating an example of a procedure for performing clamp control based on an input x [n] of a loop digital filter.
FIG. 8 is a block diagram showing a configuration example when clamp control is performed by a flag signal from a controller.
FIG. 9 is a block diagram representing a clamp circuit according to the first embodiment by a transfer function.
FIG. 10 is a block diagram showing a configuration of a clamp circuit according to a second embodiment of the present invention.
FIG. 11 is a waveform diagram showing a relationship between a clamp pulse, a clamp setting value, and an actual clamp value in an operation example when a white spot is present in an OPB portion in the clamp circuit according to the second embodiment.
FIG. 12 is a block diagram illustrating a general configuration example of a signal processing system of a solid-state imaging device.
FIG. 13 is a characteristic diagram illustrating a relationship between an incident light amount of a solid-state imaging device and a video signal.
FIG. 14 is an explanatory diagram of an OPB unit of the solid-state imaging device.
FIG. 15 is a waveform diagram showing a relationship between a video signal and a clamp pulse.
FIG. 16 is a waveform diagram showing video signals before and after clamping when the OPB section is periodic.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Offset adjuster, 12 ... AD converter, 13, 13-1, 13-2 ... Loop digital filter, 14 ... Storage part, 15, 15-1, 15-2 ... Adder, 16, 16-1, 16-2 ... Digital filter, 17 ... Solid-state imaging device, 18 ... DSP, 19 ... Controller

Claims (6)

Offset adjusting means for adding an offset value to the input video signal;
A first digital filter for filtering the video signal to which the offset value is added by the offset adjusting means;
Adding means for adding a preset clamp setting value and the output of the first digital filter;
A second digital filter for filtering the output of the adding means,
A clamp circuit, wherein the offset value added by the offset adjusting means is controlled based on an output of the second digital filter. 2. The clamp circuit according to claim 1, further comprising AD conversion means for digitally converting the video signal to which the offset value is added by the offset adjustment means, following the offset adjustment means. The loop composed of the first digital filter, the adding means, and the second digital filter includes a first mode for converging the offset value over a predetermined time, and the offset faster than the first mode. 2. The clamp circuit according to claim 1, wherein a second mode for converging the value can be selected. 2. The clamp circuit according to claim 1, comprising a plurality of loops composed of the first digital filter, the adding means, and the second digital filter. The clamp circuit according to claim 1, wherein the input video signal is a video signal output from a light-shielded pixel portion of a solid-state imaging device. 2. The clamp circuit according to claim 1, further comprising an AD converting unit that converts the inputted video signal into a digital signal and supplies the converted video signal to the offset adjusting unit before the offset adjusting unit.

Images