JP2002026065A - Method for mounting semiconductor element and circuit board - Google Patents
Method for mounting semiconductor element and circuit boardInfo
- Publication number
- JP2002026065A JP2002026065A JP2001171828A JP2001171828A JP2002026065A JP 2002026065 A JP2002026065 A JP 2002026065A JP 2001171828 A JP2001171828 A JP 2001171828A JP 2001171828 A JP2001171828 A JP 2001171828A JP 2002026065 A JP2002026065 A JP 2002026065A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- circuit board
- conductive paste
- bumps
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75251—Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子の回路
基板に高信頼性、高密度でフリップチップ型半導体素子
を実装する半導体素子の実装方法及び回路基板に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a circuit board for mounting a flip-chip type semiconductor element with high reliability and high density on a circuit board of the semiconductor element.
【０００２】[0002]
【従来の技術】従来の半導体素子の実装方法を図面に基
づいて説明する。 （従来例１）図16に従来例１における半導体素子を回路
基板に実装した断面図を示す。2. Description of the Related Art A conventional method for mounting a semiconductor device will be described with reference to the drawings. (Conventional Example 1) FIG. 16 is a cross-sectional view showing a semiconductor device of Conventional Example 1 mounted on a circuit board.
【０００３】図16において、１は半導体素子であり、半
導体素子１上に電極２が形成され、電極２上に、ワイヤ
ボンディング法によって金、銅、アルミニウム、半田な
どからなる突起バンプ（金属ボールバンプ）15が形成さ
れている。In FIG. 16, reference numeral 1 denotes a semiconductor element. An electrode 2 is formed on the semiconductor element 1, and a projection bump (metal ball bump) made of gold, copper, aluminum, solder, or the like is formed on the electrode 2 by a wire bonding method. 15) are formed.
【０００４】また４は絶縁性基体からなる回路基板であ
り、この回路基板４上に配線となる銅箔５が形成され、
また回路基板４上に銅メッキされた外部電極端子６が形
成され、回路基板内の導通をとるため、回路基板４内に
形成された孔部８に、導電性ペースト７が充填されてい
る。[0004] Reference numeral 4 denotes a circuit board made of an insulating substrate, on which a copper foil 5 serving as wiring is formed.
Further, copper-plated external electrode terminals 6 are formed on the circuit board 4, and holes 8 formed in the circuit board 4 are filled with a conductive paste 7 in order to establish conduction within the circuit board 4.
【０００５】また22はフェノールやエポキシ系樹脂に
銀、金、ニッケル、カーボンなどの導電粉末を均一分散
した導電性ペースト（導電性接着剤）であり、回路基板
４の外部電極端子６と半導体素子１の電極２を、突起バ
ンプ15を介して電気的に接続しており、また回路基板４
上と半導体素子１間にはエポキシ系樹脂20が充填されて
いる。Reference numeral 22 denotes a conductive paste (conductive adhesive) obtained by uniformly dispersing a conductive powder of silver, gold, nickel, carbon or the like in phenol or epoxy resin. The first electrode 2 is electrically connected via the bump 15 and the circuit board 4
An epoxy resin 20 is filled between the upper part and the semiconductor element 1.
【０００６】以上のように構成された半導体素子の実装
方法を説明する。半導体素子１の各電極２上に形成され
た突起バンプ15に転写法により導電性ペースト22を転写
した後、実装すべき回路基板４の外部電極端子６に合致
されるように積載し、その後加熱し、導電性ペースト22
を硬化し、半導体素子１の電極２と回路基板４の外部電
極端子６とを電気的に接続している。そして、接続後に
半導体素子１と回路基板４の間隔にエポキシ系樹脂20を
充填し、その硬化収縮力を利用して、導電性ペースト22
の導電粉末の連続的な接触が得られるようにし、電気
的、機械的信頼性を確保している。 （従来例２）図17に従来例２における半導体素子を回路
基板に実装した断面図を示す。上記図16の構成と同一の
構成には同一の符号を付して説明を省略する。[0006] A method of mounting the semiconductor device configured as described above will be described. After transferring the conductive paste 22 to the projecting bumps 15 formed on the respective electrodes 2 of the semiconductor element 1 by a transfer method, the conductive paste 22 is mounted so as to match the external electrode terminals 6 of the circuit board 4 to be mounted, and then heated. And conductive paste 22
Is cured to electrically connect the electrode 2 of the semiconductor element 1 and the external electrode terminal 6 of the circuit board 4. After the connection, the space between the semiconductor element 1 and the circuit board 4 is filled with an epoxy resin 20, and the curing and shrinking force is used to form the conductive paste 22.
To ensure continuous contact of the conductive powder, and secure electrical and mechanical reliability. (Conventional Example 2) FIG. 17 is a cross-sectional view of a semiconductor device of Conventional Example 2 mounted on a circuit board. The same components as those in FIG. 16 are denoted by the same reference numerals, and description thereof is omitted.
【０００７】図17において、23は電極２上に電気メッキ
法によって形成された金属バンプであり、金属バンプ23
上に、たとえば銅メッキが施され、その上に金メッキ24
が施されている。25は外部電極端子、16は半導体素子１
のアクティブ面を保護するパシベーション膜である。In FIG. 17, reference numeral 23 denotes a metal bump formed on the electrode 2 by electroplating.
On top, for example, copper plating is applied, on which gold plating 24
Is given. 25 is an external electrode terminal, 16 is a semiconductor element 1
Is a passivation film for protecting the active surface of
【０００８】以上のように構成された半導体素子の実装
方法を説明する。半導体素子１の各電極２上に形成され
た金属バンプ23に転写法により導電性ペースト22を転写
した後、実装すべき回路基板４の外部電極端子25に合致
されるように積載し、その後加熱し、導電性ペースト22
を硬化し、半導体素子１の電極２と回路基板４の外部電
極端子25とを電気的に接続している。そして、接続後に
半導体素子１と回路基板４の間隔にエポキシ系樹脂20を
充填し、その硬化収縮力を利用して、導電性ペースト22
の導電粉末の連続的な接触が得られるようにし、電気
的、機械的信頼性を確保している。 （従来例３）図18に従来例３における半導体素子を回路
基板に実装した断面図を示す。上記図16，図17の構成と
同一の構成には同一の符号を付して説明を省略する。A method for mounting the semiconductor device having the above-described structure will be described. After transferring the conductive paste 22 to the metal bumps 23 formed on the respective electrodes 2 of the semiconductor element 1 by a transfer method, the conductive paste 22 is mounted so as to match the external electrode terminals 25 of the circuit board 4 to be mounted, and then heated. And conductive paste 22
Is cured to electrically connect the electrode 2 of the semiconductor element 1 and the external electrode terminal 25 of the circuit board 4. After the connection, the space between the semiconductor element 1 and the circuit board 4 is filled with an epoxy resin 20, and the curing and shrinking force is used to form the conductive paste 22.
To ensure continuous contact of the conductive powder, and secure electrical and mechanical reliability. (Conventional Example 3) FIG. 18 is a cross-sectional view showing a semiconductor element of Conventional Example 3 mounted on a circuit board. The same components as those in FIGS. 16 and 17 are denoted by the same reference numerals, and description thereof is omitted.
【０００９】図18において、３は電極２の上にメッキ法
により形成された突起バンプ（突起電極）、26は絶縁性
接着剤フィルムであり、絶縁性接着剤フィルム26内には
ニッケル、半田、カーボンなどからなる導電粒子27が均
一に分散されている。In FIG. 18, reference numeral 3 denotes a bump (protrusion electrode) formed on the electrode 2 by plating, 26 denotes an insulating adhesive film, and nickel, solder, Conductive particles 27 made of carbon or the like are uniformly dispersed.
【００１０】以上のように構成された半導体素子の実装
方法を説明する。絶縁接着剤フィルム26を半導体素子１
および回路基板４の外部電極端子25に挟んで位置合わせ
して、加熱、加圧を同時に行なう。これにより、接着剤
フィルム26は溶融し電極25間のスペースに流動してい
き、導電粒子27は突起バンプ３と外部電極端子25により
固定保持され導通する。一方、スペースでは導電粒子27
が接着剤中に分散された状態を保つために絶縁性が確保
される。接着剤フィルム26は冷却すると硬化し、半導体
素子１と回路基板４を固定し、接続信頼性を確保する。A method for mounting the semiconductor device having the above configuration will be described. Insulating adhesive film 26 for semiconductor element 1
Then, heating and pressurization are performed simultaneously while positioning with the external electrode terminals 25 of the circuit board 4 interposed therebetween. As a result, the adhesive film 26 melts and flows into the space between the electrodes 25, and the conductive particles 27 are fixed and held by the protruding bumps 3 and the external electrode terminals 25 to conduct. On the other hand, in the space, conductive particles 27
Is maintained in a state of being dispersed in the adhesive, thereby ensuring insulation. The adhesive film 26 hardens when cooled, and fixes the semiconductor element 1 and the circuit board 4 to ensure connection reliability.
【００１１】[0011]
【発明が解決しようとする課題】しかし、上記従来例１
（または従来例２）の半導体素子の実装方法では、図19
に示すように、転写法によって導電性ペースト膜28を突
起バンプ15に転写し、バンプ15を回路基板４の外部電極
６に接合する際に、転写導電性ペースト22の量のコント
ロールが困難であり、少しでも多いと電極２間が導電性
ペースト22により接続されショート回路30が形成されて
しまうという問題があった。また、回路基板４が少しで
も反っていると、半導体素子１の電極２と回路基板４の
外部電極端子６が導電性ペースト22を介して接触せず、
電気的にオープン状態になるという問題があった。However, the above conventional example 1
In the mounting method of the semiconductor element of the related art (or the conventional example 2), FIG.
As shown in (1), when the conductive paste film 28 is transferred to the bumps 15 by the transfer method and the bumps 15 are bonded to the external electrodes 6 of the circuit board 4, it is difficult to control the amount of the transferred conductive paste 22. If the number is too small, there is a problem that the electrodes 2 are connected by the conductive paste 22 and the short circuit 30 is formed. If the circuit board 4 is slightly warped, the electrodes 2 of the semiconductor element 1 do not contact the external electrode terminals 6 of the circuit board 4 via the conductive paste 22.
There was a problem that it became electrically open.
【００１２】また、図20に示すように、エポキシ系樹脂
20を半導体素子１と回路基板４の隙間に充填する際に、
シリンジ31に封入されたエポキシ系樹脂20を半導体素子
１の周辺部より注入していくため、注入時間が約１０分
以上かかり、半導体素子１の生産ラインのタクトタイム
の短縮の障害になるという問題があった。Further, as shown in FIG.
When filling 20 into the gap between the semiconductor element 1 and the circuit board 4,
Since the epoxy resin 20 sealed in the syringe 31 is injected from the periphery of the semiconductor element 1, the injection time takes about 10 minutes or more, which is an obstacle to shortening the tact time of the production line of the semiconductor element 1. was there.
【００１３】また上記従来例３の半導体素子の実装方法
では、導電粒子27を半導体素子１の電極２と回路基板４
の電極25間に固定保持することにより導通されるため、
図21に示すように、回路基板４に少しでも反り・うねり
Ａがあれば、導電粒子27が接着剤26中に分散されたまま
の状態で半導体素子１の突起バンプ３と回路基板４の電
極25に接触せず、電気的にオープン状態になるという問
題点があった。なお、従来例３の実装方法は、反り・う
ねりの少ないガラス基板を対象として用いられており、
樹脂基板には用いられていないのが現状である。In the method of mounting a semiconductor device according to the conventional example 3, the conductive particles 27 are connected to the electrode 2 of the semiconductor device 1 and the circuit board 4.
Because it is conducted by fixedly holding between the electrodes 25,
As shown in FIG. 21, if the circuit board 4 has any warpage or undulation A, the bumps 3 of the semiconductor element 1 and the electrodes of the circuit board 4 are kept in a state where the conductive particles 27 are dispersed in the adhesive 26. There was a problem in that it was not in contact with 25 and was electrically opened. Note that the mounting method of Conventional Example 3 is used for a glass substrate with little warpage and undulation,
At present, it is not used for a resin substrate.
【００１４】そこで本発明は、電極間でのショートやオ
ープンといった不良は発生せず、電気的信頼性の高い実
装が行え、封止工程の時間の大幅な削減ができ、半導体
素子生産ラインのタクトタイムの短縮を可能とする半導
体素子の実装方法を提供することを目的とする。Therefore, the present invention does not cause defects such as short-circuit or open between the electrodes, can perform mounting with high electrical reliability, can greatly reduce the time of the sealing process, and can reduce the tact time of the semiconductor device production line. It is an object of the present invention to provide a method for mounting a semiconductor element that can reduce time.
【００１５】[0015]
【課題を解決するための手段】上記目的を達成するため
本発明の半導体素子の実装方法は、回路基板の回路と半
導体素子の電極とを接続する前記回路基板の箇所に、孔
部を形成する工程と、前記孔部に導電性ペーストを充填
し外部電極端子を形成する工程と、前記半導体素子の電
極に突起バンプを形成する工程と、前記外部電極端子と
半導体素子の電極に形成された突起バンプを位置決めす
る工程と、前記半導体素子を押圧し、前記孔部内の前記
導電性ペーストに前記突起バンプを埋め込み、前記半導
体素子の前記電極と前記回路基板の前記外部電極端子と
を電気的に接続する工程とを有することを特徴とするも
のである。In order to achieve the above object, a method of mounting a semiconductor device according to the present invention comprises forming a hole in a portion of the circuit board connecting a circuit of the circuit board and an electrode of the semiconductor device. Forming an external electrode terminal by filling the hole with a conductive paste; forming a projection bump on the electrode of the semiconductor element; and forming a projection on the external electrode terminal and the electrode of the semiconductor element. Positioning a bump, pressing the semiconductor element, embedding the bump in the conductive paste in the hole, and electrically connecting the electrode of the semiconductor element and the external electrode terminal of the circuit board. And a step of performing
【００１６】上記半導体素子の実装方法により、回路基
板の孔部内の充填された導電性ペーストに半導体素子の
電極に形成した突起バンプを埋め込み、前記半導体素子
の電極と回路基板の外部電極端子とを電気的に接続する
ことによって、電極間でのショートやオープンといった
不良は発生せず、電気的信頼性の高い実装が行える。ま
た、スルーホールのような貫通孔である孔部に設けた導
電性ペーストに突起バンプを埋め込むので、突起バンプ
の埋め込みの際に不要な導電性ペーストを、孔部を通し
て除去でき、押圧する半導体素子や突起バンプに無駄な
力が作用することなく、半導体素子や突起バンプの変形
などを防止できる。また、しっかりと突起バンプを導電
性ペーストに埋め込むことが可能となり接合強度も向上
する。According to the semiconductor element mounting method described above, the bumps formed on the electrodes of the semiconductor element are embedded in the conductive paste filled in the holes of the circuit board, and the electrodes of the semiconductor element and the external electrode terminals of the circuit board are connected. The electrical connection does not cause a defect such as a short circuit or an open between the electrodes, so that mounting with high electrical reliability can be performed. Further, since the bumps are buried in the conductive paste provided in the holes which are through holes such as through holes, unnecessary conductive paste can be removed through the holes when the bumps are buried. The semiconductor element and the bumps can be prevented from being deformed without applying unnecessary force to the bumps and the bumps. Further, the bumps can be firmly embedded in the conductive paste, and the bonding strength can be improved.
【００１７】[0017]
【発明の実施の形態】本発明の請求項１に記載の発明
は、回路基板の回路と半導体素子の電極とを接続する前
記回路基板の箇所に、孔部としてのスルーホールを形成
する工程と、前記スルーホールに導電性ペーストを充填
し外部電極端子を形成する工程と、前記半導体素子の電
極に突起バンプを形成する工程と、前記外部電極端子と
半導体素子の電極に形成された突起バンプを位置決めす
る工程と、前記半導体素子を押圧し、前記スルーホール
内の前記導電性ペーストに前記突起バンプを埋め込み、
前記半導体素子の前記電極と前記回路基板の前記外部電
極端子とを電気的に接続する工程とを有することを特徴
とする半導体素子の実装方法であり、突起バンプが回路
基板の孔部であるスルーホール内で導電性ペーストと接
触し、電気的に接続されるため、オープンやショートの
発生が無いという作用を有する。DETAILED DESCRIPTION OF THE INVENTION The invention according to claim 1 of the present invention comprises a step of forming a through hole as a hole at a location on the circuit board connecting a circuit of the circuit board and an electrode of a semiconductor element. Forming an external electrode terminal by filling the through hole with a conductive paste, forming a projecting bump on the electrode of the semiconductor element, and projecting the projecting bump formed on the external electrode terminal and the electrode of the semiconductor element. Positioning step, pressing the semiconductor element, embedding the bumps in the conductive paste in the through holes,
Electrically connecting the electrodes of the semiconductor element and the external electrode terminals of the circuit board, wherein the through bumps are holes in the circuit board. Since the conductive paste comes into contact with the conductive paste in the hole and is electrically connected, there is an effect that there is no occurrence of an open or a short circuit.
【００１８】請求項２に記載の発明は、請求項１記載の
半導体素子の実装方法にあって、半導体素子の電極に形
成されている突起バンプは、ワイヤボンディング法によ
って形成される金属ボールバンプであることを特徴とす
る半導体素子の実装方法であり、突起バンプを電気メッ
キ法により形成した場合、最大でも２５μｍ程度の高さ
の低いバンプしか形成できないのに対して、ワイヤボン
ディング法によると５０μｍ以上の高さの高いバンプが
形成できるため、回路基板のスルーホールの導電性ペー
ストに埋もれるバンプの量が多くなり、より信頼性の高
い実装が行えるという作用を有する。According to a second aspect of the present invention, in the method of mounting a semiconductor device according to the first aspect, the bumps formed on the electrodes of the semiconductor element are metal ball bumps formed by a wire bonding method. This is a method of mounting a semiconductor element, in which when a bump is formed by electroplating, only a bump having a height as low as about 25 μm can be formed at the maximum, but 50 μm or more according to a wire bonding method. Since the bumps having a high height can be formed, the amount of the bumps buried in the conductive paste in the through holes of the circuit board increases, which has an effect that more reliable mounting can be performed.
【００１９】請求項３に記載の発明は、請求項１または
２に記載の半導体素子の実装方法であって、半導体素子
を押圧し、回路基板のスルーホールの導電性ペーストと
半導体素子電極上の突起バンプを接触させた後、加熱ツ
ールにて前記半導体素子または回路基板の少なくとも一
方を加熱し、前記導電性ペーストの硬化を行う工程を付
加することを特徴とする半導体素子の実装方法であり、
導電性ペーストを硬化することにより、半導体素子と回
路基板との固定がより強固となり、より信頼性の高い接
合が行えるとともに、従来導電性ペーストの硬化は、モ
ジュールをオープン炉に入れバッチ処理していたのに対
して、接合と同時に同一設備で行えるため、半導体素子
の生産ラインのタクトタイム短縮につながるという作用
を有する。According to a third aspect of the present invention, there is provided the method of mounting a semiconductor device according to the first or second aspect, wherein the semiconductor element is pressed, and the conductive paste in the through hole of the circuit board and the semiconductor element electrode are formed. After the projecting bumps are brought into contact, a heating tool is used to heat at least one of the semiconductor element or the circuit board, and a method for mounting the semiconductor element, characterized by adding a step of curing the conductive paste,
By curing the conductive paste, the fixation of the semiconductor element and the circuit board becomes stronger and more reliable bonding can be performed.Conventionally, the conductive paste is cured by placing the module in an open furnace and performing batch processing. On the other hand, since the bonding can be performed with the same equipment at the same time as the bonding, there is an effect that the tact time of the production line of the semiconductor element is reduced.
【００２０】請求項４に記載の発明は、請求項１〜請求
項３のいずれかに記載の半導体素子の実装方法であっ
て、半導体素子の電極と回路基板の外部電極端子を接続
した後、前記半導体素子と前記回路基板との隙間にエポ
キシ系樹脂を流入し、封止する工程を付加することを特
徴とする半導体素子の実装方法であり、半導体素子のア
クティブ面および電極の表面がエポキシ系樹脂により保
護されるため、より接続の信頼性が増すという作用を有
する。According to a fourth aspect of the present invention, there is provided a method of mounting a semiconductor device according to any one of the first to third aspects, wherein after the electrodes of the semiconductor device are connected to the external electrode terminals of the circuit board, A method of mounting a semiconductor element, comprising adding an epoxy resin into a gap between the semiconductor element and the circuit board and sealing the resin, wherein the active surface of the semiconductor element and the surface of the electrode are epoxy-based. Since the connection is protected by the resin, the connection reliability is further increased.
【００２１】以下、本発明の実施の形態を図面に基づい
て説明する。なお、従来例の図16〜図18の構成と同一の
構成には同一の符号を付して説明を省略する。 （実施の形態１）図１は本発明の実施の形態１における
半導体素子を実装した回路基板の断面図である。Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same components as those of the conventional example shown in FIGS. 16 to 18 are denoted by the same reference numerals, and description thereof is omitted. (Embodiment 1) FIG. 1 is a sectional view of a circuit board on which a semiconductor element according to Embodiment 1 of the present invention is mounted.
【００２２】図示するように、半導体素子１の電極２上
に形成された突起バンプ３は、回路基板４の孔部８に充
填された導電性ペースト７に埋もれる形で、接触してお
り、回路基板４の外部電極端子６と半導体素子１の電極
２が電気的に接続されている。図２の工程図にしたがっ
て本発明の半導体素子の実装方法を説明する。As shown in the figure, the bumps 3 formed on the electrodes 2 of the semiconductor element 1 are in contact with the conductive paste 7 filled in the holes 8 of the circuit board 4 so as to be in contact therewith. The external electrode terminal 6 of the substrate 4 and the electrode 2 of the semiconductor element 1 are electrically connected. A method for mounting a semiconductor device according to the present invention will be described with reference to the process chart of FIG.
【００２３】まず、回路基板４の外部電極端子６と半導
体素子１の電極２を接続する、回路基板４の箇所に、孔
部８を形成し、図２(a) に示すように、導電性ペースト
７を、スキージ９を移動さすことにより前記回路基板４
の孔部８に印刷・充填し、回路基板４の外部電極端子33
を形成する。First, a hole 8 is formed in a portion of the circuit board 4 where the external electrode terminal 6 of the circuit board 4 and the electrode 2 of the semiconductor element 1 are connected, and as shown in FIG. The paste 7 is transferred to the circuit board 4 by moving the squeegee 9.
Is printed and filled in the holes 8 of the external electrodes 33 of the circuit board 4.
To form
【００２４】次に、図２(b) に示すように、半導体素子
１を吸着ノズル10に吸着させ、突起バンプ３と、孔部８
に充填された導電性ペースト７により形成された回路基
板４の外部電極端子33との位置合わせを行う。Next, as shown in FIG. 2B, the semiconductor element 1 is sucked by the suction nozzle 10, and the bumps 3 and the holes 8 are formed.
Is aligned with the external electrode terminals 33 of the circuit board 4 formed by the conductive paste 7 filled in the conductive paste 7.
【００２５】次に、図２(c) に示すように、半導体素子
１を吸着ノズル10により押圧し、図２(d) に示すよう
に、突起バンプ３を回路基板４の孔部８に充填された導
電性ペースト７に埋め込む。Next, as shown in FIG. 2C, the semiconductor element 1 is pressed by the suction nozzle 10, and the bumps 3 are filled in the holes 8 of the circuit board 4 as shown in FIG. Embedded in the conductive paste 7.
【００２６】その結果、半導体素子１の突起バンプ３が
回路基板４の孔部内で導電性ペースト７と接触し、電気
的に接続される。また、回路基板４は図３に示すよう
に、インナービアホールにより、基板内層間の導通がと
られた多層基板であっても、図４に示すようにスルーホ
ールによって、層間の導通がとられた多層基板であって
も良い。また、空洞のまま両端が開放されたスルーホー
ルのような貫通孔である孔部に設けた導電性ペーストに
突起バンプを埋め込むので、突起バンプの埋め込みの際
に不要な導電性ペーストを、孔部を通して除去でき、押
圧する半導体素子や突起バンプに無駄な力が作用するこ
となく、半導体素子や突起バンプの変形などを防止でき
る。また、しっかりと突起バンプを導電性ペーストに埋
め込むことが可能となり接合強度も向上する。As a result, the bumps 3 of the semiconductor element 1 come into contact with the conductive paste 7 in the holes of the circuit board 4 and are electrically connected. Also, as shown in FIG. 3, even when the circuit board 4 is a multi-layer board in which conduction between layers in the board is achieved by inner via holes, conduction between layers is achieved by through holes as shown in FIG. It may be a multilayer substrate. In addition, since the projecting bumps are embedded in the conductive paste provided in the holes which are through holes such as through holes whose both ends are opened as a cavity, unnecessary conductive paste when embedding the projecting bumps is filled in the holes. The semiconductor element or the bump can be prevented from being deformed without applying unnecessary force to the semiconductor element or the bump to be pressed. Further, the bumps can be firmly embedded in the conductive paste, and the bonding strength can be improved.
【００２７】この実施の形態１によれば、半導体素子１
の電極２上に形成された突起バンプ３が、回路基板４の
孔部８内で導電性ペースト７に埋もれて接触し、電気的
に接続されるため、ショートが発生せず、また回路基板
４の反り、うねりに対する許容範囲も広がり、オープン
が発生せず、高い信頼性をもって半導体素子１と回路基
板４を接合することができる。 （実施の形態２）図５は本発明の実施の形態２における
ワイヤボンディング法を用いた、半導体素子の電極上の
突起バンプの形成方法を示す工程図であり、図５を参照
しながらワイヤボンディング法を説明する。According to the first embodiment, the semiconductor device 1
The bumps 3 formed on the electrodes 2 are buried in the conductive paste 7 in the holes 8 of the circuit board 4 and are in contact with and electrically connected to each other. The semiconductor device 1 and the circuit board 4 can be bonded with high reliability without causing an open area, and with an increased tolerance to warpage and undulation. (Embodiment 2) FIG. 5 is a process chart showing a method of forming a bump on an electrode of a semiconductor element using a wire bonding method according to Embodiment 2 of the present invention. Explain the law.
【００２８】まず、図５(a) に示すように、金、銅、ア
ルミニウム、半田などで製作された金属ワイヤ11をセラ
ミックやルビーで作られたキャピラリー13に通し、通し
た金属ワイヤ11の先端とトーチと呼ばれる電極14との間
で放電し、金属ボール12を形成する。First, as shown in FIG. 5 (a), a metal wire 11 made of gold, copper, aluminum, solder, or the like is passed through a capillary 13 made of ceramic or ruby, and the tip of the passed metal wire 11 is passed through. And an electrode 14 called a torch discharges to form a metal ball 12.
【００２９】次に、図５(b) に示すように、予熱されて
いる半導体素子１の電極２の上に前記金属ボール12を押
圧し、超音波振動を加え、温度、圧力、超音波振動の作
用によって、金属ボール12を電極２に接合する。Next, as shown in FIG. 5 (b), the metal ball 12 is pressed onto the electrode 2 of the semiconductor element 1 which has been preheated, and ultrasonic vibration is applied. The metal ball 12 is joined to the electrode 2 by the action of (1).
【００３０】次に、図５(c) に示すように、キャピラリ
ー13を鉛直方向に上昇させ、金属ワイヤ11を引きちぎっ
て図６に示す、金属ボールによるバンプ15を形成する。
そして図５(d) に示すように、キャピラリー13を上昇さ
せた後、金属ワイヤ１１を引きちぎらず、キャピラリー
13を横にずらせて下降させ、金属ワイヤ11を金属ボール
12上に接触させ、温度、圧力、あるいは、温度、圧力、
超音波振動の作用によって金属ワイヤ11を金属ボール12
に接合する。Next, as shown in FIG. 5 (c), the capillary 13 is raised in the vertical direction, and the metal wire 11 is torn off to form a bump 15 made of a metal ball as shown in FIG.
Then, as shown in FIG. 5 (d), after raising the capillary 13, the capillary 13 is not broken without breaking the metal wire 11.
Slide 13 downward to lower the metal wire 11
12 on temperature, pressure, or temperature, pressure,
The metal wire 11 is turned into the metal ball 12 by the action of ultrasonic vibration.
To join.
【００３１】次に、図５(e) に示すように、キャピラリ
ー13を上昇させ、金属ワイヤ11を引きちぎって、図５
(f) および図７に示す、金属ボールによる２段突起形状
バンプ15を形成する。Next, as shown in FIG. 5 (e), the capillary 13 is raised, and the metal wire 11 is torn off.
(f) and a two-step bump 15 made of a metal ball as shown in FIG. 7 is formed.
【００３２】上記方法により半導体素子１の電極２上に
金属ボールによる突起バンプ15を形成した後、図８に示
す方法により、半導体素子１と回路基板４との接合を行
う。図８の実装方法は上記実施の形態１で説明した方法
と同様であり、説明を省略する。After the bumps 15 made of metal balls are formed on the electrodes 2 of the semiconductor element 1 by the above method, the semiconductor element 1 and the circuit board 4 are joined by the method shown in FIG. The mounting method in FIG. 8 is the same as the method described in the first embodiment, and the description is omitted.
【００３３】この実施の形態２によれば、実施の形態１
での効果に加えて、突起バンプを電気メッキ法により形
成した場合、最大でも２５μｍ程度の高さの低いバンプ
しか形成できないのに対して、ワイヤボンディング法を
使用することにより５０μｍ以上の高さの高いバンプを
形成でき、よって図８(e) に示すように、回路基板４の
孔部８の導電性ペースト７に埋もれるバンプ15の量が多
くなり、回路基板４の反り、うねりに対する許容範囲が
広くなり、より信頼性の高い実装を行うことができる。 （実施の形態３）本発明の実施の形態３における半導体
素子の実装方法を図９を参照にしながら説明する。According to the second embodiment, the first embodiment
In addition to the effect of the above, when the bumps are formed by electroplating, only bumps having a height as low as about 25 μm can be formed at the maximum, whereas the bumps having a height of 50 μm or more can be formed by using the wire bonding method. As shown in FIG. 8E, the bumps 15 buried in the conductive paste 7 in the holes 8 of the circuit board 4 are increased, and the allowable range for warpage and undulation of the circuit board 4 is increased. Wider and more reliable mounting is possible. Embodiment 3 A method for mounting a semiconductor device according to Embodiment 3 of the present invention will be described with reference to FIG.
【００３４】図９は、半導体素子１を吸着ノズル10に吸
着し、突起バンプ15と孔部８に充填された導電性ペース
ト７により形成された回路基板４の外部電極端子と位置
合わせを行なった後、押圧し、突起バンプ15が導電性ペ
ースト７に埋め込まれた状態を示している。その際、吸
着ノズル10は、内蔵されているヒータ17により加熱され
ており、押圧と同時に導電性ペースト７の硬化を行って
いる。FIG. 9 shows that the semiconductor element 1 is sucked by the suction nozzle 10 and is aligned with the external electrode terminals of the circuit board 4 formed by the bumps 15 and the conductive paste 7 filled in the holes 8. Thereafter, a state is shown in which the bump 15 is embedded in the conductive paste 7 by pressing. At that time, the suction nozzle 10 is heated by the built-in heater 17, and the conductive paste 7 is cured at the same time as the pressing.
【００３５】この実施の形態３によれば、上記実施の形
態１，２での効果に加えて、導電性ペースト７を硬化す
ることにより、半導体素子１と回路基板４との固定がよ
り強固となり、より信頼性の高い接合が行えるととも
に、従来、導電性ペースト７の硬化は、モジュールをオ
ーブン炉に入れバッチ処理していたのに対して、接合と
同時に同一設備で行えるため、半導体素子１の生産ライ
ンのタクトタイム短縮を行うことができる。 （実施の形態４）本発明の実施の形態４における半導体
素子の実装方法を図10を参照にしながら説明する。According to the third embodiment, in addition to the effects of the first and second embodiments, by hardening the conductive paste 7, the fixing between the semiconductor element 1 and the circuit board 4 becomes stronger. In addition to the fact that the bonding of the conductive paste 7 can be performed with the same equipment at the same time as the bonding while the module is placed in an oven furnace and batch-processed, the bonding of the conductive paste 7 can be performed. The tact time of the production line can be reduced. (Embodiment 4) A method of mounting a semiconductor device according to Embodiment 4 of the present invention will be described with reference to FIG.
【００３６】図10は、半導体素子１を吸着ノズル10に吸
着し、突起バンプ15と孔部８に充填された導電性ペース
ト７により形成された回路基板４の外部電極端子33と位
置合わせを行なった後、押圧し、突起バンプ15が導電性
ペースト７に埋め込まれた状態を示している。その際、
回路基板４を保持しているステージ18は、内蔵されてい
るヒータ17により加熱されており、半導体素子１の押圧
時に熱を加えることにより、押圧と同時に導電性ペース
ト７の硬化を行っている。FIG. 10 shows that the semiconductor element 1 is sucked by the suction nozzle 10 and is aligned with the external electrode terminals 33 of the circuit board 4 formed by the bumps 15 and the conductive paste 7 filled in the holes 8. After pressing, the bump 15 is embedded in the conductive paste 7. that time,
The stage 18 holding the circuit board 4 is heated by a built-in heater 17, and by applying heat when the semiconductor element 1 is pressed, the conductive paste 7 is cured at the same time as the pressing.
【００３７】この実施の形態４によれば、上記実施の形
態１，２での効果に加えて、導電性ペースト７を硬化す
ることにより、半導体素子１と回路基板４との固定がよ
り強固となり、より信頼性の高い接合が行えるととも
に、従来、導電性ペースト７の硬化は、モジュールをオ
ーブン炉に入れバッチ処理していたのに対して、接合と
同時に同一設備で行えるため、半導体素子１の生産ライ
ンのタクトタイム短縮を行うことができる。 （実施の形態５）本発明の実施の形態５における半導体
素子の実装方法を図11を参照にしながら説明する。According to the fourth embodiment, in addition to the effects of the first and second embodiments, by curing the conductive paste 7, the fixing between the semiconductor element 1 and the circuit board 4 is further strengthened. In addition to the fact that the bonding of the conductive paste 7 can be performed with the same equipment at the same time as the bonding while the module is placed in an oven furnace and batch-processed, the bonding of the conductive paste 7 can be performed. The tact time of the production line can be reduced. (Embodiment 5) A method of mounting a semiconductor device according to Embodiment 5 of the present invention will be described with reference to FIG.
【００３８】図11に示すように実施の形態５では、半導
体素子１を押圧し、回路基板４の孔部８の導電性ペース
ト７と半導体素子１の電極２上の突起バンプ15を接触さ
せた後、モジュール（回路基板４および半導体素子１）
をコンベア32にのせ、移動させながらモジュール全体を
ヒーター19によって加熱し、導電性ペースト７の硬化を
行う。As shown in FIG. 11, in the fifth embodiment, the semiconductor element 1 is pressed to bring the conductive paste 7 in the hole 8 of the circuit board 4 into contact with the bump 15 on the electrode 2 of the semiconductor element 1. Later, the module (circuit board 4 and semiconductor element 1)
Is placed on a conveyor 32, and the entire module is heated by the heater 19 while being moved to cure the conductive paste 7.
【００３９】この実施の形態５によれば、上記実施の形
態１，２での効果に加えて、導電性ペースト７の硬化
を、モジュール全体をコンベア32にのせ、移動させなが
ら加熱するリフロー方式で行うため、実装と同一生産ラ
イン上での硬化が可能となり、半導体素子１の生産ライ
ンのタクトには影響を与えず、半導体素子１と回路基板
４との固定をより強固にでき、より信頼性の高い接合を
行うことができる。 （実施の形態６）本発明の実施の形態６における半導体
素子の実装方法を図12を参照しながら説明する。According to the fifth embodiment, in addition to the effects of the first and second embodiments, the hardening of the conductive paste 7 is performed by a reflow method in which the entire module is placed on the conveyor 32 and heated while moving. Therefore, curing can be performed on the same production line as mounting, and the tact of the production line of the semiconductor element 1 is not affected, and the semiconductor element 1 and the circuit board 4 can be more firmly fixed, and the reliability can be improved. High bonding can be performed. (Embodiment 6) A method of mounting a semiconductor device according to Embodiment 6 of the present invention will be described with reference to FIG.
【００４０】図12に示すように実施の形態６では、上記
実施の形態１〜５の実装の工程において、回路基板４に
半導体素子１を実装した後に、半導体素子１と回路基板
４との間隔にシリンジ31を用いて、エポキシ系樹脂20を
充填する。As shown in FIG. 12, in the sixth embodiment, in the mounting steps of the first to fifth embodiments, after the semiconductor element 1 is mounted on the circuit board 4, the distance between the semiconductor element 1 and the circuit board 4 is increased. The epoxy resin 20 is filled using a syringe 31.
【００４１】この実施の形態６によれば、上記実施の形
態１〜５での効果に加えて、図13に示すように、エポキ
シ系樹脂20の充填により、半導体素子１のアクティブ面
および電極２の表面が保護されるため、たとえば、モジ
ュールが高温高湿などの環境にさらされても、電極２お
よび突起バンプ３の腐食を防ぐことができ、より信頼性
の高い接続を行うことができる。 （実施の形態７）本発明の実施の形態７における半導体
素子の実装方法を図14を参照にしながら説明する。According to the sixth embodiment, in addition to the effects of the first to fifth embodiments, the active surface of the semiconductor element 1 and the electrode 2 are filled with the epoxy resin 20 as shown in FIG. For example, even if the module is exposed to an environment such as high temperature and high humidity, corrosion of the electrodes 2 and the bumps 3 can be prevented, and more reliable connection can be performed. (Embodiment 7) A method of mounting a semiconductor device according to Embodiment 7 of the present invention will be described with reference to FIG.
【００４２】まず、図14(a) に示すように、回路基板４
の孔部８に導電性ペースト７を充填し、外部電極端子33
を形成した後、回路基板４上に熱硬化系、または熱可塑
系、または熱硬化と熱可塑の混合系樹脂からなる接着剤
シート21を配置する。First, as shown in FIG.
Is filled with the conductive paste 7 and the external electrode terminals 33 are filled.
Is formed, an adhesive sheet 21 made of a thermosetting resin, a thermoplastic resin, or a mixed resin of thermosetting and thermoplastic is disposed on the circuit board 4.
【００４３】なお、接着剤シート21には、ニッケル、半
田、カーボン、金めっきプラスチック粒子などを均一に
分散させておいても良い。次に、図14(b) に示すよう
に、半導体素子１を吸着ノズル10に吸着し、突起バンプ
15と孔部８に充填された導電性ペースト７により形成さ
れた回路基板４の外部電極端子33と位置合わせを行な
う。The adhesive sheet 21 may have nickel, solder, carbon, gold-plated plastic particles and the like dispersed uniformly. Next, as shown in FIG. 14 (b), the semiconductor element 1 is sucked by the suction nozzle 10 and
Positioning is performed with the external electrode terminals 33 of the circuit board 4 formed by the conductive paste 7 filled in the holes 15 and the holes 8.
【００４４】次に、図14(c) に示すように、半導体素子
１を押圧し、突起バンプ15により接着剤シート21を突き
破り、導電性ペースト７に突起バンプ１５を埋め込む。
その際、吸着ノズル10は、内蔵されているヒータ17によ
り加熱されており、押圧と同時に接着剤シート21の溶融
・硬化が行われる。Next, as shown in FIG. 14C, the semiconductor element 1 is pressed, the adhesive sheet 21 is pierced by the bumps 15, and the bumps 15 are embedded in the conductive paste 7.
At this time, the suction nozzle 10 is heated by the built-in heater 17, and the adhesive sheet 21 is melted and hardened simultaneously with the pressing.
【００４５】この実施の形態７によれば、上記実施の形
態１，２での効果に加えて、図14(d) に示すように、接
着剤シート21が溶融・硬化し、半導体素子１のアクティ
ブ面および電極の２表面を保護するため、より接続の信
頼性が増すとともに、接着剤シート21の場合、加圧・硬
化に要する時間が約３０秒と、エポキシ系樹脂の硬化時
間約４時間に対して大幅に短いため、半導体素子１の生
産ラインのタクトタイム短縮が可能となる。 （実施の形態８）本発明の実施の形態８における半導体
素子の実装方法を図15を参照にしながら説明する。According to the seventh embodiment, in addition to the effects of the first and second embodiments, the adhesive sheet 21 is melted and cured as shown in FIG. In order to protect the active surface and the two surfaces of the electrodes, the connection reliability is further increased. In the case of the adhesive sheet 21, the time required for pressing and curing is about 30 seconds, and the curing time of the epoxy resin is about 4 hours. , The cycle time of the production line of the semiconductor element 1 can be shortened. (Eighth Embodiment) A method for mounting a semiconductor device according to an eighth embodiment of the present invention will be described with reference to FIG.
【００４６】まず、図15(a) に示すように、半導体素子
１の電極２上に突起バンプ15を形成した後、予め突起バ
ンプ15上に熱硬化系、または熱可塑系、または熱硬化と
熱可塑の混合系樹脂からなる接着剤シート21を配置す
る。なお、接着剤シート21には、ニッケル、半田、カー
ボン、金めっきプラスチック粒子などを均一に分散させ
ておいても良い。First, as shown in FIG. 15A, after a bump 15 is formed on the electrode 2 of the semiconductor element 1, a thermosetting, thermoplastic, or thermosetting bump is formed on the bump 15 in advance. An adhesive sheet 21 made of a thermoplastic mixed resin is arranged. Note that nickel, solder, carbon, gold-plated plastic particles, and the like may be uniformly dispersed in the adhesive sheet 21.
【００４７】その後、図15(b) に示すように、半導体素
子１を吸着ノズル10に吸着し、突起バンプ15と孔部８に
充填された導電性ペースト７により形成された回路基板
４の外部電極端子33と位置合わせを行なった後、押圧
し、突起バンプ15により接着剤シート21を突き破り、導
電性ペースト７に突起バンプ15を埋め込む。その際、吸
着ノズル10は、内蔵されているヒータ17により加熱され
ており、押圧と同時に接着剤シート21の溶融・硬化が行
われる。Thereafter, as shown in FIG. 15B, the semiconductor element 1 is sucked by the suction nozzle 10, and the outside of the circuit board 4 formed by the bumps 15 and the conductive paste 7 filled in the holes 8. After the alignment with the electrode terminals 33, pressing is performed, the adhesive sheet 21 is pierced by the bumps 15, and the bumps 15 are embedded in the conductive paste 7. At this time, the suction nozzle 10 is heated by the built-in heater 17, and the adhesive sheet 21 is melted and hardened simultaneously with the pressing.
【００４８】この実施の形態８によれば、上記実施の形
態１，２での効果に加えて、実施の形態７と同様、接着
剤シート21が溶融・硬化し、半導体素子１のアクティブ
面および電極２の表面を保護するため、より接続の信頼
性が増すとともに、接着剤シート21の場合、加圧・硬化
に関する時間が約３０秒と、エポキシ系樹脂の硬化時
間、約４時間に対して大幅に短いため、半導体素子１の
生産ラインのタクトタイム短縮が可能となる。According to the eighth embodiment, in addition to the effects of the first and second embodiments, similarly to the seventh embodiment, the adhesive sheet 21 is melted and hardened, and the active surface of the semiconductor element 1 and the In order to protect the surface of the electrode 2, the connection reliability is further increased, and in the case of the adhesive sheet 21, the time required for pressing and curing is about 30 seconds, and the curing time of the epoxy resin is about 4 hours. Since it is significantly shorter, the takt time of the production line of the semiconductor device 1 can be reduced.
【００４９】[0049]
【発明の効果】以上のように本発明によれば、半導体素
子の電極上に形成された突起バンプを、回路基板の孔部
としてのスルーホール内の導電性ペーストに接触させ、
半導体素子の電極と回路基板の外部電極端子とを電気的
に接続することにより、電極間でのショートを回避で
き、また回路基板の反り、うねりに対する許容範囲が広
いことから電極間でのオープンを回避でき、電気的信頼
性の高い実装を行うことができる。As described above, according to the present invention, the projecting bump formed on the electrode of the semiconductor element is brought into contact with the conductive paste in the through hole as the hole of the circuit board,
By electrically connecting the electrodes of the semiconductor element and the external electrode terminals of the circuit board, a short circuit between the electrodes can be avoided, and since the circuit board has a wide tolerance for warpage and undulation, it is necessary to open the electrodes between the electrodes. It is possible to avoid this, and to implement mounting with high electrical reliability.
【００５０】また、スルーホールのような貫通孔である
孔部に設けた導電性ペーストに突起バンプを埋め込むの
で、突起バンプの埋め込みの際に不要な導電性ペースト
を、孔部を通して除去でき、押圧する半導体素子や突起
バンプに無駄な力が作用することなく、半導体素子や突
起バンプの変形などを防止できる。また、しっかりと突
起バンプを導電性ペーストに埋め込むことが可能となり
接合強度も向上する。Also, since the bumps are buried in the conductive paste provided in the holes which are through holes such as through holes, unnecessary conductive paste can be removed through the holes when the bumps are buried. The semiconductor element and the bumps can be prevented from being deformed without applying unnecessary force to the semiconductor element and the bumps. Further, the bumps can be firmly embedded in the conductive paste, and the bonding strength can be improved.
【図面の簡単な説明】[Brief description of the drawings]
【図１】本発明の実施の形態１における実装後の半導体
素子と回路基板の接合断面図である。FIG. 1 is a cross-sectional view of a junction between a semiconductor element and a circuit board after mounting according to a first embodiment of the present invention.
【図２】本発明の実施の形態１における実装の工程を順
に示す図である。FIG. 2 is a diagram sequentially illustrating a mounting process according to the first embodiment of the present invention.
【図３】本発明の実施の形態１における実装後の半導体
素子と回路基板の接合断面図である。FIG. 3 is a cross-sectional view of the bonding between the semiconductor element and the circuit board after mounting according to the first embodiment of the present invention.
【図４】本発明の実施の形態１における実装後の半導体
素子と回路基板の接合断面図である。FIG. 4 is a cross-sectional view of the semiconductor device and the circuit board after mounting according to the first embodiment of the present invention.
【図５】本発明の実施の形態２におけるワイヤボンディ
ング法の工程を順に示す図である。FIG. 5 is a diagram sequentially illustrating steps of a wire bonding method according to a second embodiment of the present invention.
【図６】本発明の実施の形態２におけるワイヤボンディ
ング法により形成された突起バンプの側面図である。FIG. 6 is a side view of a projection bump formed by a wire bonding method according to a second embodiment of the present invention.
【図７】本発明の実施の形態２におけるワイヤボンディ
ング法により形成された２段突起形状突起バンプの側面
図である。FIG. 7 is a side view of a two-stage projection-shaped projection bump formed by a wire bonding method according to a second embodiment of the present invention.
【図８】本発明の実施の形態２における実装の工程を順
に示す図である。FIG. 8 is a diagram sequentially illustrating a mounting process according to the second embodiment of the present invention.
【図９】本発明の実施の形態３における実装の工程を示
す図である。FIG. 9 is a diagram illustrating a mounting process according to a third embodiment of the present invention.
【図10】本発明の実施の形態４における実装の工程を示
す図である。FIG. 10 is a diagram illustrating a mounting process according to a fourth embodiment of the present invention.
【図11】本発明の実施の形態５における実装の工程を示
す図である。FIG. 11 is a diagram illustrating a mounting process according to a fifth embodiment of the present invention.
【図12】本発明の実施の形態６における実装の工程を示
す図である。FIG. 12 is a diagram illustrating a mounting process according to a sixth embodiment of the present invention.
【図13】本発明の実施の形態６における実装後の半導体
素子と回路基板の接合断面図である。FIG. 13 is a cross-sectional view of a junction between a semiconductor element and a circuit board after mounting according to a sixth embodiment of the present invention.
【図14】本発明の実施の形態７における実装の工程を順
に示す図である。FIG. 14 is a diagram sequentially illustrating a mounting process according to the seventh embodiment of the present invention.
【図15】本発明の実施の形態８における実装の工程を順
に示す図である。FIG. 15 is a diagram sequentially illustrating a mounting process according to the eighth embodiment of the present invention.
【図16】従来の半導体素子の実装方法による実装後の半
導体素子と回路基板の接合断面図である。FIG. 16 is a cross-sectional view of a junction between a semiconductor element and a circuit board after being mounted by a conventional method for mounting a semiconductor element.
【図17】従来の半導体素子の実装方法による実装後の半
導体素子と回路基板の接合断面図である。FIG. 17 is a cross-sectional view of a semiconductor element and a circuit board after being mounted by a conventional method for mounting a semiconductor element.
【図18】従来の半導体素子の実装方法による実装後の半
導体素子と回路基板の接合断面図である。FIG. 18 is a cross-sectional view of a junction between a semiconductor element and a circuit board after being mounted by a conventional method for mounting a semiconductor element.
【図19】従来の実装の工程を順に示す図である。FIG. 19 is a diagram sequentially illustrating a conventional mounting process.
【図20】従来の実装方法の課題を説明する図である。FIG. 20 is a diagram illustrating a problem of a conventional mounting method.
【図21】従来の実装方法の課題を説明する図である。FIG. 21 is a diagram illustrating a problem of a conventional mounting method.
１ 半導体素子 ２ 電極 ３ 突起バンプ（メッキ法による） ４ 回路基板 ５ 銅箔 ６ 外部電極端子 ７ 導電性ペースト ８ 孔部 ９ スキージ 10 吸着ノズル 11 金属ワイヤ 12 金属ボール 13 キャピラリー 14 電極 15 突起バンプ（ワイヤボンディング法による） 16 パシベーション膜 17，19 ヒータ 18 ステージ 20 エポキシ系樹脂 21 樹脂シート 31 シリンジ 32 コンベヤ 33 外部電極端子 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Electrode 3 Protrusion bump (by plating method) 4 Circuit board 5 Copper foil 6 External electrode terminal 7 Conductive paste 8 Hole 9 Squeegee 10 Suction nozzle 11 Metal wire 12 Metal ball 13 Capillary 14 Electrode 15 Protrusion bump (wire) (By bonding method) 16 Passivation film 17, 19 Heater 18 Stage 20 Epoxy resin 21 Resin sheet 31 Syringe 32 Conveyor 33 External electrode terminal
Claims (5)
接続する前記回路基板の箇所に、スルーホールを形成す
る工程と、 前記スルーホールに導電性ペーストを充填し外部電極端
子を形成する工程と、 前記半導体素子の電極に突起バンプを形成する工程と、 前記外部電極端子と半導体素子の電極に形成された突起
バンプを位置決めする工程と、 前記半導体素子を押圧し、前記スルーホール内の前記導
電性ペーストに前記突起バンプを埋め込み、前記半導体
素子の前記電極と前記回路基板の前記外部電極端子とを
電気的に接続する工程とを有することを特徴とする半導
体素子の実装方法。1. A step of forming a through hole in a portion of the circuit board connecting a circuit of a circuit board and an electrode of a semiconductor element, and a step of forming an external electrode terminal by filling the through hole with a conductive paste. Forming a protruding bump on the electrode of the semiconductor element; positioning the protruding bump formed on the external electrode terminal and the electrode of the semiconductor element; pressing the semiconductor element; Embedding the bumps in a conductive paste and electrically connecting the electrodes of the semiconductor element and the external electrode terminals of the circuit board.
バンプは、ワイヤボンディング法によって形成される金
属ボールバンプであることを特徴とする請求項１記載の
半導体素子の実装方法。2. The method according to claim 1, wherein the bumps formed on the electrodes of the semiconductor element are metal ball bumps formed by a wire bonding method.
ホールの導電性ペーストと半導体素子電極上の突起バン
プを接触させた後、加熱ツールにて前記半導体素子また
は回路基板の少なくとも一方を加熱し、前記導電性ペー
ストの硬化を行う工程を付加することを特徴とする請求
項１または請求項２に記載の半導体素子の実装方法。3. A semiconductor element is pressed and a conductive paste in a through hole of a circuit board is brought into contact with a bump on a semiconductor element electrode. Then, at least one of the semiconductor element or the circuit board is heated by a heating tool. 3. The method according to claim 1, further comprising a step of curing the conductive paste.
端子を接続した後、前記半導体素子と前記回路基板との
隙間にエポキシ系樹脂を流入し、封止する工程を付加す
ることを特徴とする請求項１〜請求項３のいずれかに記
載の半導体素子の実装方法。4. The method according to claim 1, further comprising, after connecting an electrode of the semiconductor element and an external electrode terminal of the circuit board, injecting an epoxy resin into a gap between the semiconductor element and the circuit board to perform sealing. The method for mounting a semiconductor device according to claim 1.
と、前記半導体素子の電極を接続する箇所にスルーホー
ルを有する回路基板と、前記スルーホールに充填され外
部電極端子を形成する導電性ペーストとを備え、前記ス
ルーホール内の導電性ペーストに前記突起バンプを埋め
込み、前記半導体素子の前記電極と前記回路基板の前記
外部電極端子とを電気的に接続する半導体素子を実装し
た回路基板。5. A semiconductor element having a bump on an electrode, a circuit board having a through-hole at a place where the electrode of the semiconductor element is connected, and a conductive paste filled in the through-hole to form an external electrode terminal. A circuit board, comprising: a semiconductor element for embedding the protruding bumps in a conductive paste in the through-hole and electrically connecting the electrodes of the semiconductor element to the external electrode terminals of the circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001171828A JP2002026065A (en) | 2001-06-07 | 2001-06-07 | Method for mounting semiconductor element and circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001171828A JP2002026065A (en) | 2001-06-07 | 2001-06-07 | Method for mounting semiconductor element and circuit board |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14524196A Division JP3610999B2 (en) | 1996-06-07 | 1996-06-07 | Mounting method of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002026065A true JP2002026065A (en) | 2002-01-25 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP2001171828A Pending JP2002026065A (en) | 2001-06-07 | 2001-06-07 | Method for mounting semiconductor element and circuit board |
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|---|---|
| JP (1) | JP2002026065A (en) |
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- 2001-06-07 JP JP2001171828A patent/JP2002026065A/en active Pending
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