JP2002009858A - Device and method for demodulating digital satellite broadcast - Google Patents

Abstract

PROBLEM TO BE SOLVED: To securely detect the synchronism of digital satellite broadcast signals whose modulation systems dynamically change and to securely detect synchronism even in an inferior reception environment. SOLUTION: In a BS digital broadcast demodulation device, the symbol timing of transmission data on digital satellite broadcast is synchronized and a synchronous word included in transmission data of digital satellite broadcast is detected so as to synchronize the frame timing. Then, at least the reception phase of the synchronous word is detected based on the frame synchronous timing and a carrier synchronism processing is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital satellite broadcast demodulator for demodulating digital satellite broadcasts and a digital satellite broadcast demodulation method.

[0002]

2. Description of the Related Art FIG. 19 is a block diagram showing a general transmission model for transmitting digital data by performing digital quadrature modulation.

The transmitting system Tx includes a data generator 11, a serial / parallel (S / P) converter 12, and a local oscillator 1
3, a -90 degree phase shifter 14, a first multiplier 15, a second multiplier 16, an adder 17, and a waveform shaping filter 1
8 is provided.

The data generator 11 of the transmission system Tx generates digital data obtained by serializing I signal data and Q signal data. The generated digital data is supplied to a serial / parallel (S / P) converter 12.

The S / P converter 12 performs level conversion of the input digital data from (0, 1) data to (1, -1) data, and performs serial / parallel conversion together therewith. , I signal data to a first multiplier 15 and the Q signal data to a second multiplier 16.

The local oscillator 13 generates a carrier wave which is a cosine wave having a frequency fc and an initial phase th. The generated carrier is supplied to the −90 degree phase shifter 14 and the first multiplier 15.

[0007] The -90 degree phase shifter 14 delays the phase of the carrier wave, which is a cos wave, by 90 degrees to generate a -sin wave. The generated −sine wave is supplied to the second multiplier 16.

The first multiplier 15 outputs the I signal data and co
The signal is multiplied by the s-wave and supplied to the addition circuit 17. The second multiplier 16 multiplies the Q signal data by the −sine wave and supplies the result to the addition circuit 17. The adder circuit 17 outputs a cosine wave multiplied by the I signal data and a sin wave multiplied by the Q signal data.
Add the waves. As a result of the addition, a quadrature modulated signal obtained by digital quadrature modulation of the carrier having the frequency fc is generated.

The quadrature-modulated signal is subjected to waveform shaping and amplification by a waveform shaping filter 18 so that the transmission path (C
channel).

The transmission path (Channel) is provided with an adder 19 for adding noise to the transmission signal. The transmission signal transmitted from the transmission system Tx is received by the reception system Rx with noise added by the transmission path.

The receiving system Rx includes a first multiplier 21 and a second multiplier 21.
, A local oscillator 23 and a 90-degree phase shifter 24
A first low-pass filter 25, a second low-pass filter 26, a first analog / digital (A / D) converter 27, a second analog / digital (A / D) converter 28, A carrier correction unit 29, a first waveform shaping filter 30, a second waveform shaping filter 31, a carrier synchronization unit 32, a timing synchronization unit 33, a parallel / serial (P / S) converter 34, a slicer 35.

The received signal is input to a first multiplier 21 and a second multiplier 22.

The local oscillator 23 generates a carrier wave which is a cos wave having a frequency fc 'and an initial phase th'. Frequency f
c 'and the initial phase th' do not generally match the carrier on the transmitting side and have different frequencies and phases. The generated carrier is supplied to the 90-degree phase shifter 24 and the first multiplier 21.

The 90-degree phase shifter 24 advances the phase of the carrier wave, which is a cos wave, by 90 degrees to generate a sine wave. The generated sine wave is supplied to the second multiplier 22.

The first multiplier 21 multiplies the received signal by the cosine wave and quadrature demodulates the I signal. Second multiplier 22
Multiplies the received signal by a sine wave and quadrature demodulates the Q signal. The demodulated I signal is supplied to a first low-pass filter 2
5 removes high-frequency components, and the first A / D converter 27
Supplied to The demodulated Q signal has its second high-pass component removed by a second low-pass filter 26 and has a second A
/ D converter 28.

The first A / D converter 27 digitizes the I signal. Further, the second A / D converter 28 digitizes the Q signal. The first A / D converter 27 and the second A / D converter 28 use the sampling clock CLK output from the timing synchronization unit 33 to output the I signal and the Q signal.
Sample the signal. At this time, the sampling frequency is controlled by the timing synchronization section 33 so that the frequency and the phase are synchronized with the transmission symbol clock on the transmission side. The digitized I signal data and Q signal data are supplied to the carrier correction unit 29, respectively.

The carrier correction unit 29 performs a complex multiplication of the rotational phase correction signals (RI, RQ) output from the carrier synchronization unit 33 on the I signal data and the Q signal data. The I signal data and the Q signal data are converted to the rotational phase correction signals (RI, R
Q) is complex-multiplied to obtain the frequency fc ′ and phase th ′ of the carrier generated by the local oscillator 23 on the receiving side and the frequency fc and phase th of the carrier of the received signal.
Is corrected. The phase-corrected I signal data is supplied to the P / S converter 34 after the waveform is shaped by the first waveform shaping filter 30. The phase-corrected Q signal data is supplied to a P / S converter 34 after being subjected to waveform shaping by a second waveform shaping filter 31.

The carrier synchronizer 32 calculates a rotation phase correction signal (RI, RQ) which is a signal having a frequency and a phase corresponding to the carrier frequency error and the phase error of the received data. The carrier frequency error and the phase error of the received data are caused by the frequency shift and the phase shift of the carrier of the local oscillator 23. The calculated rotational phase correction signal (RI,
RQ) is supplied to the carrier correction unit 29.

The timing synchronization section 33 detects a clock error of the received data and generates a sampling clock such that the clock error becomes zero, that is, a sampling clock synchronized with the symbol clock of the transmission symbol on the transmission side. The generated sampling clock is the first A
/ D converter 27 and a second A / D converter 28.

The P / S converter 34 selects received data in the order of I signal data and Q signal data, and converts the data into serial data. The generated serial data is stored in slicer 3
5 is supplied.

The slicer 35 outputs 0 when the input data is larger than a predetermined value, and outputs 1 when the input data is smaller than a predetermined value.

Then, the transmission data is reproduced from the slicer 35.

In such digital data transmission,
On the receiving side, the demodulation process is performed by reproducing the transmission symbol clock generated on the transmitting side. The reproduction of the transmission symbol clock is called timing reproduction. On the receiving side, a correct demodulation result can be obtained by correcting the symbol clock of the received signal by some means instead of reproducing the transmission symbol clock. A process of obtaining a correct demodulation result by correcting a transmission symbol, including performing a timing reproduction and performing a demodulation process, is called timing synchronization.

On the receiving side, the coordinate system defining the transmission symbol space generated on the transmitting side is reproduced to perform demodulation processing. The reproduction of the coordinate system in the transmission symbol space is called carrier wave reproduction. On the receiving side, instead of reproducing the coordinate system that defines the transmission symbol space,
Correcting the coordinate system that defines the symbol space of the received signal by some means makes it possible to obtain a correct demodulation result. Obtaining a correct demodulation result by correcting the coordinate system defining the transmission symbol space, including reproducing the coordinate system defining the transmission symbol space and performing demodulation processing, is referred to as carrier synchronization.

[0025]

By the way, in the CS digital broadcasting service already started in Japan, all transmission signals are QPSK-modulated. QPSK
20A is defined in the symbol space shown in FIG. 20A, for example, and the eye pattern of the received signal after passing through the waveform shaping filter is shown in FIG. Become like That is, in the QPSK modulation method, 1-bit information is assigned to each of the I signal and the Q signal, and data for modulating the I signal and the Q signal can be defined independently of each other.

On the other hand, in the BS digital broadcasting system in Japan, three types of modulation systems, BPSK, QPSK and 8PSK, are adopted, and each modulation system changes dynamically.

The signal point arrangement of 8PSK is shown in FIG.
The eye pattern of the received signal defined on the symbol space shown in (A) and having passed through the waveform shaping filter is as shown in FIG. 21B for both the I and Q axes. Therefore, in the case of 8PSK, when the 0-crossing method is applied to perform timing synchronization, the detection level is lower than that of the QPSK signal, and the noise component of the detection result becomes large.

Here, if there is a phase error in the carrier generated from the local oscillator between the transmitting side and the receiving side, the received signal rotates by an angle corresponding to the error phase with respect to the transmitted signal. Will be received. When a frequency error exists in the carrier, the received signal is received after being rotated at an angular velocity corresponding to the error frequency with respect to the transmitted signal.

Therefore, on the receiving side, when performing carrier wave synchronization, usually, the phase error amount is detected from the received signal point, and the correction amount corresponding to the error phase amount and the frequency error amount is fed back to thereby obtain the phase error and the frequency error. Is corrected.

However, in the QPSK modulation system, the phase error detection range is 45 degrees, whereas in the 8PSK modulation system used in the BS digital broadcasting system, the phase error detection range is halved to 22.5 degrees. In this case, the phase detection accuracy is deteriorated.

Further, in the case of BS digital broadcasting, in terms of the transmission environment, TMC transmitted by the BPSK modulation method is used.
Standardization of the C data has been established so as to ensure reliability at C / N = 0 dB, and it is necessary to take measures against a very poor reception environment.

The present invention provides a digital satellite broadcast receiving apparatus for reliably detecting carrier synchronization of a digital satellite broadcast signal in which each modulation scheme changes dynamically, and for reliably detecting synchronization even in a poor reception environment. It is intended to provide a receiving method.

[0033]

In the digital satellite broadcast demodulator according to the present invention, a timing synchronizing means for synchronizing symbol timing of transmission data and a synchronization word are detected from the transmission data synchronized with the timing. ,
Frame synchronization means for detecting frame synchronization timing of transmission data; carrier synchronization for identifying at least the symbol position of the synchronization word based on the frame timing, detecting the reception phase of each symbol of the synchronization word, and performing carrier wave synchronization processing Means.

This digital satellite broadcast demodulator performs synchronization processing of the symbol timing of the digital satellite broadcast transmission data, and subsequently detects the synchronization word included in the digital satellite broadcast transmission data, thereby detecting the frame timing. A synchronization process is performed, and subsequently, at least a reception phase of a synchronization word is detected based on the frame synchronization timing, and a carrier synchronization process is performed.

That is, in this digital satellite broadcast demodulator, the carrier synchronization processing is performed after the frame synchronization processing.

Further, the digital satellite broadcast demodulator according to the present invention detects the difference data between the symbols of the transmission data when setting the frame synchronization timing, and determines the difference between the difference data of the transmission data and the difference data of the synchronization word. Has a correlation.

Further, in the digital satellite broadcast demodulator according to the present invention, when setting the frame synchronization timing, the correlation value between the difference data of the transmission data and the difference data of the synchronization word is filtered at the frame period. The filtering is performed by, for example, IIR (Infinite Impull
se Response) Filtering is performed using a filter.

In the digital satellite broadcast demodulator according to the present invention, after the frame synchronization is established, filtering is performed only on the symbol at the position where the synchronization word occurs. At the time of frame synchronization pull-in, filtering is performed using a decoding memory such as an error correction memory or a memory such as a deinterleaver which is not used before frame synchronization is established. Filtering is performed using a delay memory having a data capacity of.

In the digital satellite broadcast demodulator according to the present invention, the synchronous position is detected by comparing the correlation value data with a predetermined value, and the interval between the synchronous position and the interval between the synchronous positions is determined. The synchronization interval is detected by comparison. Then, using a symbol counter for counting the number of symbols of the transmission data in one frame period, after the above-mentioned synchronization interval becomes one frame interval continuously for a predetermined number of times, the count value is set as an initial value. Is set to a predetermined value, a frame start signal is issued.

In the digital satellite broadcast demodulator according to the present invention, the count value of the symbol counter is transmitted based on the synchronization position detected by the synchronization position detection unit and the synchronization interval obtained by the synchronization interval detection unit. The frame synchronization process is controlled using a state machine that transitions between a synchronization pull-in state for synchronizing with data and a synchronization holding state for maintaining a state in which the count value of the symbol counter is synchronized with the transmission data. ing.

Further, in the digital satellite broadcast demodulator according to the present invention, the carrier data error is corrected by complexly multiplying the transmission data consisting of the orthogonal coordinate signals by a rotation correction signal, and the transmission data in which the carrier error has been corrected. , A rotation correction signal corresponding to the phase rotation error amount is generated, a phase rotation error amount of the transmission data in which the carrier error is corrected is calculated based on the modulation method of the synchronization word, and the frame synchronization is calculated. Counting the number of symbols from the timing, specifying at least the symbol position of the synchronization word, filtering the phase rotation error amount of the specified symbol, and controlling the frequency and phase according to the filtered phase rotation error amount. A carrier synchronization process is performed by generating a rotation correction signal.

In the digital satellite broadcast demodulating method for demodulating a digital satellite broadcast signal according to the present invention, a synchronization process of symbol timing of transmission data is performed, and a synchronization word is detected from the transmission data synchronized in timing. Detecting the frame synchronization timing of the transmission data, identifying at least the symbol position of the synchronization word based on the frame timing, detecting the reception phase of each symbol of the synchronization word, and performing the synchronization processing of the carrier. .

That is, in this digital satellite broadcast demodulation method, the carrier synchronization processing is performed after the frame synchronization processing.

Further, in the digital satellite broadcast demodulation method according to the present invention, at the time of frame synchronization timing, difference data between symbols of the transmission data is detected, and the difference data between the transmission data and the synchronization word difference data is detected. Has a correlation.

In the digital satellite broadcast demodulation method according to the present invention, when the frame synchronization timing is set, the correlation value between the difference data of the transmission data and the difference data of the synchronization word is filtered at the frame period. The filtering is performed by, for example, IIR (Infinite Impull
se Response) Filtering is performed using a filter.

In the digital satellite broadcast demodulation method according to the present invention, after the frame synchronization is established, filtering is performed only on the symbol at the position where the synchronization word occurs. At the time of frame synchronization pull-in, filtering is performed using a decoding memory such as an error correction memory or a memory such as a deinterleaver which is not used before frame synchronization is established. Filtering is performed using a delay memory having a data capacity of.

In the digital satellite broadcast demodulating method according to the present invention, the synchronous position is detected by comparing the correlation value data with a predetermined value, and further, the interval between the synchronous positions and the interval between the synchronous positions are determined. The synchronization interval is detected by comparison. Then, using a symbol counter for counting the number of symbols of the transmission data in one frame period, after the above-mentioned synchronization interval becomes one frame interval continuously for a predetermined number of times, the count value is set as an initial value. Is set to a predetermined value, a frame start signal is issued.

Further, in the digital satellite broadcast demodulation method according to the present invention, the count value of the symbol counter is transmitted based on the synchronous position detected by the synchronous position detecting section and the synchronous interval obtained by the synchronous interval detecting section. The frame synchronization process is controlled using a state machine that transitions between a synchronization pull-in state for synchronizing with data and a synchronization holding state for maintaining a state in which the count value of the symbol counter is synchronized with the transmission data. ing.

Further, in the digital satellite broadcast demodulation method according to the present invention, the carrier data error is corrected by complexly multiplying the transmission data consisting of orthogonal coordinate signals by a rotation correction signal, and the transmission data having the corrected carrier error is corrected. , A rotation correction signal corresponding to the phase rotation error amount is generated, a phase rotation error amount of the transmission data in which the carrier error is corrected is calculated based on the modulation method of the synchronization word, and the frame synchronization is calculated. Counting the number of symbols from the timing, specifying at least the symbol position of the synchronization word, filtering the phase rotation error amount of the specified symbol, and controlling the frequency and phase according to the filtered phase rotation error amount. A carrier synchronization process is performed by generating a rotation correction signal.

[0050]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a BS according to an embodiment of the present invention will be described.
A digital broadcast receiving device will be described.

[0051] Overall Configuration Figure 1 shows a block diagram of a receiving apparatus of a BS digital broadcast, a description is given of the receiving apparatus of the BS digital broadcasting.

The receiving apparatus 100 includes a demodulation section 101 and a first
A demultiplexer 102, an inner code decoding unit 103,
The second demultiplexer 104 and the deinterleaver 10
5, the main signal inverse energy spreading section 106, the frame reconstructing section 107, the main signal RS decoding section 108, the TMCC
It comprises an inverse energy spreading section 109, a third demultiplexer 110, a TMCCRS decoding section 111, and a TMCC control section 112.

The demodulation section 101 receives, for example, an RF signal received by a parabolic antenna or the like. The demodulation unit 101 multiplies the RF signal by the carrier signal to demodulate the quadrature modulated I and Q signals. The demodulation unit 101 also performs frequency conversion, carrier wave synchronization, timing synchronization, and frame synchronization processing. The demodulation unit 101
Is a TAB signal (synchronization word) modulated by BPSK
, The superframe and the start position of the frame are detected. The demodulated I signal data and Q signal data are sent to the first demultiplexer 102.

The first demultiplexer 102 counts symbols from the frame start position detected by the demodulation section 101, and converts a burst signal at a predetermined symbol position into a burst signal.
Main signal data and TMCC data (including TAB signal)
Separate from The burst signal is read and discarded as it is. The main signal data and the TMCC data are sent to inner code decoding section 103.

The inner code decoding section 104 performs depuncturing and Viterbi decoding according to the modulation scheme and the inner code coding rate of each symbol. The inner code decoded data is sent to the second demultiplexer 104.

The second demultiplexer 104 separates the main signal data from the TMCC data (including the TAB signal). The separated main signal data is supplied to the deinterleaver 1
05. Separated TMCC data (TAB
Signal), the TMCC inverse energy diffusion processor 10
6 is sent.

The deinterleaver 105 deinterleaves the main signal data according to the reverse rule of the interleaving process performed on the transmitting side. The deinterleaved main signal is sent to main signal inverse energy spreading section 106.

The main signal inverse energy spreading section 106
The next sequence pseudo-random sequence (PRBS) is added one bit at a time to the main signal data, and the inverse process to the energy spreading process performed on the transmission side is performed. Note that a pseudo random code sequence (PRBS) is initialized at the beginning of a superframe. Also, although the energy spreading process is not performed on the first byte of each slot, the PRBS continues to be generated during this time. The main signal data subjected to inverse energy spreading is sent to frame reconstructing section 107.

The frame reconstructing unit 107 reconstructs the data structure into a frame structure corresponding to the data frame on the transmission side, such as a process of adding the synchronization word (0x47) of the transport packet (TSP) deleted during transmission. I do. The reconstructed main signal data is sent to the main signal Reed-Solomon decoding unit 108.

The main signal Reed-Solomon decoding unit 108
In units of a transmission packet consisting of 204 bytes, RS (20
4,188), and outputs a TSP.

TMCC inverse energy diffusion processing unit 109
Is the TMCC data for one superframe and TAB
After accumulating the signal in the buffer, the ninth-order pseudo-random sequence (PRBS) is added one bit at a time to the TMCC data and the TAB signal, and inverse processing is performed on the energy spreading processing performed on the transmission side. This pseudo random code sequence (PRBS) is initialized at the beginning of a superframe. Further, energy diffusion is not performed on the TAB signal, but the generation of the PRBS continues. The energy-spread TMCC data and TAB signal are
To the demultiplexer 110.

The third demultiplexer 110 has a TMC
The C data and the TAB signal are separated. TAB isolated
The signal is discarded. The separated TMCC data is sent to TMCC Reed-Solomon decoding section 111.

TMCC Reed-Solomon decoding section 111
Converts the TMCC data consisting of 64 bytes into RS (6
4, 48), and outputs TMCC information. The RS-decoded TMCC information is transmitted to the TMCC controller 1
12 is sent.

The TMCC control unit 112 extracts TMCC data necessary for transmission path decoding from the TMCC information, obtains TMCC information corresponding to each transport stream (TS), and transmits information necessary for decoding to each functional block. To deliver.

The receiving apparatus 100 having the above configuration receives a BS digital broadcast and demodulates a transport stream conforming to the MPEG-2 system.

[0066] Configuration Figure 2 demodulator, showing the configuration of a demodulator 101 of the BS digital receiver 100 will be further described the demodulator 101.

The demodulation section 101 includes a first multiplier 121,
A second multiplier 122, a local oscillator 123, a 90-degree phase shifter 124, a first low-pass filter 125,
, A first analog / digital (A / D) converter 127, a second analog / digital (A / D) converter 128, a carrier correction unit 129,
First waveform shaping filter 130, second waveform shaping filter 131, timing synchronization unit 132, frame synchronization unit 133, carrier synchronization unit 134, third multiplier 1
35, a fourth multiplier 136, a parallel / serial (P / S) converter 137, and a slicer 138.

For example, an RF signal received by a parabolic antenna or the like is input to a first multiplier 121 and a second multiplier 122.

The local oscillator 123 generates a carrier wave which is a cos wave having a frequency fc 'and an initial phase th'. The frequency fc 'and the initial phase th' do not coincide with the carrier on the transmitting side, and have different frequencies. The generated carrier is supplied to the 90-degree phase shifter 124 and the first multiplier 121.

The 90-degree phase shifter 124 advances the phase of the carrier wave, which is a cos wave, by 90 degrees to generate a sine wave. The generated sine wave is supplied to the second multiplier 122.

The first multiplier 121 calculates the cos
The I signal is quadrature-demodulated by multiplying the signal by a wave. Second multiplier 1
Reference numeral 22 multiplies the received signal by the sine wave and quadrature-demodulates the Q signal. The demodulated I signal is supplied to a first A / D converter 127 after a high-frequency component is removed by a first low-pass filter 125. The demodulated Q signal is supplied to a second A / D converter 128 after a high-frequency component is removed by a second low-pass filter 126.

The first A / D converter 127 digitizes the I signal. Further, the second A / D converter 128
Digitize the signal. The first A / D converter 127 and the second A / D converter 128 include a timing synchronization unit 132
I by the sampling clock CLK output from
The signal and the Q signal are sampled. At this time, the sampling frequency is controlled by the timing synchronization unit 132 so that the frequency and the phase are synchronized with the transmission symbol clock on the transmission side. Digitized I signal data and Q
The signal data is supplied to the carrier correction unit 129, respectively.

The carrier correction unit 129 includes the carrier synchronization unit 13
4 outputs the rotational phase correction signals (RI, RQ)
The I signal data and the Q signal data output from the first and second A / D converters 127 and 128 are subjected to complex multiplication.
The I signal data and the Q signal data are subjected to complex multiplication of the rotational phase correction signals (RI, RQ) to obtain the frequency fc 'and phase th' of the carrier generated by the local oscillator 123 on the receiving side and the phase th 'on the transmitting side. The frequency shift and the phase shift occurring between the frequency fc and the phase th of the carrier are corrected. That is, the carrier frequency error and the phase error are corrected. After the corrected I signal data is subjected to waveform shaping by the first waveform shaping filter 130,
Is supplied to the multiplier 135. The phase-corrected Q signal data is supplied to a fourth multiplier 136 after being subjected to waveform shaping by a second waveform shaping filter 131.

The timing synchronization section 132 is a circuit for performing timing synchronization processing by controlling the sampling clock of the A / D converters 127 and 128. The timing synchronizer 132 includes the waveform shaping filters 130 and 13
A clock error of the received data whose waveform has been shaped by 1 is detected, and a sampling clock such that the clock error becomes 0, that is, a sampling clock whose phase and frequency are synchronized with the symbol clock of the transmission symbol on the transmission side is generated. I do. The timing synchronization unit 132 detects a clock error by using, for example, the 0-crossing method. The generated clock is used as a sampling clock for the first A / D converter 127 and the second A / D converter 128.

Note that the timing synchronization section 132 controls the reception C / N = 0 dB even if the I and Q signal data output from the waveform shaping filters 130 and 131 include a carrier frequency error and a phase error. However, it is assumed that they have timing synchronization characteristics enough to obtain predetermined characteristics.

The frame synchronization section 133 is a circuit for performing a frame synchronization process for detecting the start position of a frame by detecting a TAB signal (synchronization word) in the transmission data.

Here, in BS digital broadcasting, a data structure called a super frame is defined. As shown in FIG. 3, the superframe is composed of eight frames (frame # 0 to frame # 7).
Each frame is composed of a control signal section (TMCC signal and TAB signal (synchronization word)) and a main signal section (main signal and burst signal).

As shown in FIG. 4, the main signal section has 48 slots (slot # 0 to slot #) per frame.
47). The main signal section is configured by alternately arranging main signal data of 203 symbols and burst signals of 4 symbols subjected to BPSK modulation (r = １ ／).

The control signal section has a transmission and multiplexing configuration (TMCC) of 8 bytes per frame.
ation Control) signal and a 2-byte TAB signal (synchronization word) added before and after the signal.
The TMCC signal and the TAB signal are each subjected to BPSK modulation (r = １ ／), and in terms of the number of transmission symbols,
128 symbols for TMCC and 32 symbols for TAB signal
Become a symbol. Here, the value of the TAB signal attached to the stage preceding the TMCC is W1 (0x1B95). Also, the TA attached after the TMCC
The value of the B signal is W2 for the first frame # 0.
(0xA340), and the value is W3 (0x5CBF) for the second to eighth frames. W
2 and W3 have a bit-inverted relationship.

Therefore, by detecting the TAB signal (synchronization word), it is possible to synchronize the frames, and by distinguishing and detecting W2 and W3, it is possible to synchronize the superframe. . Note that the 2-byte TAB signal is actually convolutionally coded to be a 32-bit transmission symbol. Among them, the first 12 bits are affected by the last main signal data of the previous frame and the value is undefined, but the latter 20 bits are in a range that is not affected by the previous frame. Become. On the receiving side, this convolutionally coded fixed value (w1 for W1, w2 / w3 for W2 / W3)
Is detected as a synchronization signal.

The frame synchronizing section 133 performs this frame synchronizing process in a state where the timing is synchronized but the carrier is not synchronized. Specifically, a difference operation between symbols is performed on transmission data synchronized with timing. Then, a correlation between the bit string subjected to the difference operation and the synchronization word subjected to the difference operation is obtained. Then, a symbol position having the highest correlation (or a symbol having a correlation value higher than a certain threshold value) is detected, and the symbol position is set as a frame synchronization position. Since the TAB signal W2 and W3 are in a bit-inverted relationship, the value becomes the same when a difference operation between symbols is performed.

The frame synchronizing unit 133 performs such a TA
The B signal is detected, and a frame start flag (FST flag) indicating a frame start position and a superframe start flag (SFST flag) indicating a start position of a superframe are set.
Flag). Also, the frame synchronization unit 133
Not only FST flag and SFST flag, but also SFS
By counting the number of symbols from the T flag, TA
TAB flag indicating the symbol position of B signal (synchronization word), TMC flag indicating the symbol position of TMCC
Flag, which is a flag indicating the symbol position of the main signal
An N flag and a BRST flag indicating the symbol position of the burst signal may also be generated and output. The frame start signal (FST) and the superframe start flag (S
FST) is supplied to the carrier synchronizer 134.

The frame synchronizing section 133 also generates a 180-degree phase inversion signal. Carrier synchronizer 134 described later
Adopts a carrier synchronization method that allows a 180-degree phase uncertainty (a method in which the phase may be rotated by 180 degrees when synchronization is performed and synchronization may be applied). Therefore, the frame synchronization unit 133 uses the synchronization word (TAB
Signal) is detected, and a 180 ° carrier wave phase error is detected. If a 180-degree carrier phase error is detected, the 180-degree phase-inverted signal is output as -1. If no 180-degree carrier-phase error is detected, the 180-degree phase-inverted signal is output as +1. This 180 degree phase inversion signal is supplied to the third multiplier 135 and the fourth multiplier 135.
Is supplied to the multiplier 136.

If the carrier synchronizer 134 can perform carrier synchronization without leaving the phase uncertainty of 180 degrees, 1
Either always keep the 80 degree phase inverted signal +1 or
The third multiplier 135, the fourth multiplier 136, and the 180-degree phase inversion signal may be omitted. Further, the frame synchronization unit 133 performs a frame synchronization operation in a state where the timing is synchronized by the timing synchronization unit 132. Then, it is assumed that the frame synchronization unit 133 has a frame synchronization characteristic enough to obtain a predetermined characteristic even with reception C / N = 0 dB under the condition that carrier wave synchronization is not established. .

The carrier synchronizer 134 generates rotation phase correction signals (RI, RQ) according to the carrier frequency error and the phase error of the received data, and performs the carrier synchronization process. The carrier frequency error and the phase error of the received data are caused by the frequency shift and the phase shift of the carrier of the local oscillator 123.

Specifically, the carrier synchronizer 134 converts the received data in the orthogonal coordinate system into angle data, and detects a rotation phase error indicating how much the angle data is rotated from the original reception point. I do. Then, the rotational phase error is filtered to detect a frequency component and a phase component of the rotational phase error. Then, the carrier synchronizer 134
Generates a rotational phase correction signal (RI, RQ) having a frequency and a phase by the VCO or the like to cancel the frequency component and the phase component of the detected rotational phase error.
The carrier correction unit 129 outputs the rotational phase correction signal (RI,
RQ) is multiplied by the received data to cancel the carrier frequency error and the phase error.

The carrier synchronizer 134 performs a carrier synchronize operation in a state where the timing is synchronized by the timing synchronizer 132 and the frame is synchronized by the frame synchronizer 133. And
The carrier synchronizer 134 receives the C / N signal under the condition that the timing synchronization and the frame synchronization are established.
It is assumed that a carrier synchronization characteristic enough to obtain a predetermined characteristic is obtained even for = 0 dB.

The third multiplier 135 multiplies the I signal data whose waveform has been shaped by the first waveform shaping filter 130 with the 180-degree phase-inverted signal supplied from the frame synchronization section 133. If the 180-degree phase inversion signal is +1, the I signal data is output as it is. If the 180 degree phase inversion signal is -1, the sign of the I signal data is inverted and output. The output I signal data is supplied to the P / S converter 137.

The fourth multiplier 136 multiplies the Q signal data, the waveform of which has been shaped by the second waveform shaping filter 131, by the 180 ° phase-inverted signal supplied from the frame synchronization unit 133. If the 180 degree phase inversion signal is +1 then
The Q signal data is output as it is. If the 180-degree phase inversion signal is -1, the sign of the Q signal data is inverted and output. The output Q signal data is supplied to the P / S converter 137.

The P / S converter 137 outputs the I signal data, Q signal
The received data is selected in the order of the signal data and converted into serial data. The generated serial data is supplied to the slicer 138.

The slicer 138 outputs 0 when the input data is larger than a predetermined value, and outputs 1 when the input data is smaller than a predetermined value.

The demodulated data is output from the slicer 138 and supplied to the inner code decoder 103.

Synchronous Operation Flow of Demodulator FIG. 5 shows a synchronous operation flow of the demodulator, and the synchronous operation of the demodulator will be described.

First, when the system is reset (step S1), the process proceeds to timing synchronization pull-in process (step S2).

In the timing synchronization pull-in process (step S2), the timing synchronization section 132 detects the output signals of the waveform shaping filters 130 and 131 and controls the synchronization of the sampling clocks of the A / D converters 127 and 128. When the timing synchronization is established, a notification that the timing synchronization has been completed is issued, and the process proceeds to the next frame synchronization pull-in process (step S3).

In the timing synchronization pull-in process (step S2), if the frame synchronization pull-in process and the carrier wave synchronization pull-in process are also performed in parallel, it is not necessary to issue a notice that the timing synchronization has been completed. Is also good. However, since the pull-in processing of the frame synchronization and the pull-in processing of the carrier wave cannot be performed unless the timing synchronization is established, these pull-in operations may be stopped. If the operations of the frame synchronization pull-in process and the carrier wave synchronization pull-in process are stopped during the timing synchronization pull-in process, power consumption can be saved. After the timing synchronization is established, the state in which the timing synchronization is established is kept protected.

Subsequently, in the frame synchronization pull-in process (step S3), the frame synchronization section 133 detects the output signals of the waveform shaping filters 130 and 131, and calculates the difference data between the symbols of the output signals and the difference between the synchronization words. The frame synchronization timing is detected by correlating with the data. When the frame synchronization timing is detected, a notification that the frame synchronization has been completed is issued, and the process proceeds to the next carrier synchronization pull-in process (step S4).

In the frame synchronization pull-in process (step S3), when the carrier synchronization pull-in process is performed in parallel, it is not necessary to issue a notification that the frame synchronization has been completed. However, if the frame synchronization timing is not detected, it is difficult to perform the carrier wave synchronization pull-in process. Therefore, the carrier wave synchronization pull-in operation may be stopped. If the operation of the pull-in process for carrier wave synchronization is stopped during the pull-in process for frame synchronization, power consumption can be saved. After the frame synchronization has been established, the state in which the frame synchronization has been established continues to be protected.

Subsequently, in the carrier synchronization pull-in process (step S4), the carrier synchronization unit 134 extracts the frame synchronization unit 1 from the output signals of the waveform shaping filters 130 and 131.
A phase rotation error amount of a symbol specified based on the frame synchronization timing output from the detector 33 is detected, and a phase rotation correction signal of a frequency and a phase for correcting the phase rotation error is generated. The generated phase rotation correction signal is supplied to the carrier correction unit 129, and is subjected to complex multiplication with the transmission data to correct the carrier error.

When the carrier error is corrected and the carrier synchronization is established, the state transits to the state where the timing synchronization protection, the frame synchronization protection and the carrier synchronization are protected (step S5).

If timing synchronization is lost during the above process, the process proceeds to the timing synchronization pull-in process (step S2), and the process is continued from step 2. If the frame synchronization is lost, the process proceeds to the frame synchronization pull-in process (step S3), and the process is continued from step S3. If the carrier is out of synchronization, the process proceeds to the carrier synchronization pull-in process (step S4), and the process is continued from step S4.

As described above, by performing the synchronization operation in the order of timing synchronization, frame synchronization, and carrier wave synchronization, the demodulation section 101 employs a plurality of modulation schemes and digital satellite broadcasting in which each modulation scheme changes dynamically. Can be reliably detected with a simple configuration. Also,
Synchronization can be reliably detected with a small circuit scale even in a poor reception environment.

[0103] frame synchronization unit then performs further detail described frame synchronization unit 133.

FIG. 6 is a block diagram of the frame synchronization unit 133.

The frame synchronization section 133 includes a reception data differential detection circuit 201, a synchronous word differential detection circuit 202,
A frame correlation circuit 203, an IIR filter 204,
Superframe synchronization circuit 205 and synchronization detection circuit 20
6 is provided.

The received data differential detection circuit 201 receives received data for each symbol. The reception data differential detection circuit 201 performs differential detection between symbols by performing complex multiplication of the symbol at the current time and the complex conjugate of the symbol one cycle before. The differential reception data obtained as a result of the differential detection is supplied to the frame correlation circuit 203.

The synchronization word differential detection circuit 202 detects a difference between symbols with respect to a synchronization word indicating a head position of a frame. The differential synchronization word data obtained as a result of the differential detection is supplied to the frame correlation circuit 203.

The frame correlation circuit 203 receives the differential reception data sequentially for each symbol and calculates a correlation between the differential reception data and the differential synchronization word data. The frame correlation circuit 203 outputs the calculated correlation value for each symbol. The correlation value data output from the frame correlation circuit 203 is supplied to the IIR filter 204.

The IIR filter 204 performs IIR filtering on the correlation value data by using a frame period delay memory. The IIR-filtered correlation value data is supplied to the synchronization detection circuit 206.

The superframe synchronization circuit 205 sequentially receives the received data for each symbol and calculates the correlation between the received data and the synchronization word. Here, the superframe synchronization circuit 205 independently calculates the correlation between the synchronization word w1 and the synchronization word w2, and detects whether or not the carrier wave synchronization is rotated by 180 degrees and synchronized. Further, the superframe synchronization circuit 205 independently calculates the correlation between the synchronization word w1 and the synchronization word w2, and detects the frame at the start position of the superframe. The super frame synchronization circuit 205
May be any as long as the operation becomes possible after the synchronization of the carrier.

The synchronization detecting circuit 206 is provided with the IIR filter 2
On the basis of the correlation value data output from step 04, the start position of the frame is detected, and an FST flag indicating the start position of the frame is output. Further, the synchronization detection circuit 206 outputs an SFST flag indicating the start position of the super frame based on the output from the super frame synchronization circuit 205.

Here, in calculating the correlation between the received data and the synchronization word, the reason for making the received data differential is as follows.
It is as follows.

That is, when a carrier frequency error is included in the symbol of the received data, even if noise is not added in the transmission path, the phase component corresponding to the carrier frequency error 1
Proceed for each sample. Even if the phase of an input symbol including such a carrier frequency error is detected for each sample and compared with the synchronization word, the symbol position of the synchronization word cannot be accurately detected. On the other hand, by performing the differential between the symbols, the carrier frequency error included in each sample is removed. Therefore, at this time, a symbol having a phase containing only a constant carrier phase error component for each sample is used. In this case, the synchronization word to be compared with the differential symbol may be similarly differentiated. Therefore,
By making the received data differential, frame synchronization can be achieved with respect to the received data that is not synchronized with the carrier wave but contains a carrier frequency error. Note that w2 and w3 of the synchronization word have a bit-inverted relationship, and therefore have the same value if differentially calculated.

The reason why frame synchronization can be detected by correlating received data with the synchronization word and the reason for filtering the correlation value are as follows.

Regarding the symbols to be transmitted, symbols other than the synchronization word are pseudo-randomized by energy spreading, and are considered to be similarly randomized in the case of differentialization. Therefore, by calculating the correlation between the differential input symbol and the differential synchronization word, the insertion position of the synchronization word can be detected. That is, when the correlation is calculated for each symbol, the correlation result becomes the maximum value at the synchronization word position, and the correlation result becomes almost 0 at positions other than the synchronization word position. It can be said that there is.

However, in actual operation, noise is added on the transmission path, which also affects the correlation result. That is, the correlation result is output smaller than the maximum value regardless of the position where the synchronization word is inserted, or the correlation result is output larger at a position other than the synchronization word position. Therefore, it is important to remove the influence of such noise. Therefore, attention is paid to the fact that the synchronization word is transmitted periodically. Since it is considered that the correlation result is affected by noise as described above, on average,
At the insertion position of the sync word, a large correlation result is output,
The correlation result is almost 0 at positions other than the synchronization word position. By utilizing this property, the noise component can be reduced by filtering the correlation result, and the synchronization word information can be emphasized. That is, for the correlation value at the position of the p-th symbol from the head in one frame, the instantaneous correlation value at the position of a certain p-symbol in the frame is calculated, and the result is calculated as the p-th symbol from the head one frame before. By performing filtering using the output result, an average correlation value at the position of p in the frame can be obtained. By performing this process for all positions in one frame, an average correlation value at each position can be obtained.

Frame synchronization detection method, carrier synchronization 1
The method of removing the phase uncertainty of 80 degrees and the method of detecting the synchronization of the superframe are as follows.

By being subjected to IIR filtering,
Since a large correlation value is output at the frame synchronization position, and the correlation value becomes almost 0 at positions other than the frame synchronization position, the synchronization detection unit 206 may detect the position at which the average of the correlation values is the largest as the synchronization position. Further, since the correlation value becomes almost 0 at positions other than the frame synchronization position, a position where the correlation value becomes larger than a predetermined value may be set as the synchronization position. Here, for simplification of the apparatus, a position where the value of the correlation value is larger than a predetermined value is detected as a synchronous position. At this time, frame synchronization protection is also performed for the purpose of improving the accuracy of the synchronization position detection result and preventing disturbance due to noise.

Further, when the carrier wave synchronization allows the phase uncertainty of 180 degrees, the synchronization detecting circuit 206 also removes the phase uncertainty of 180 degrees. The phase uncertainty of 180 degrees is determined by detecting whether the bit of w1 in the synchronization word is normal or inverted from the received symbol after carrier synchronization.

The synchronization detection circuit 206 also detects the synchronization of the superframe. The superframe synchronization is determined by detecting whether the synchronization word w2 or the synchronization word w3 is added from the received symbols after the carrier synchronization. The frame to which the synchronization word w2 is added becomes the start frame of the super frame.

Next, an example of a circuit configuration of each sub-block constituting the frame synchronization circuit 133 will be described.

(Differential Detection Circuit) FIG. 7 shows a circuit configuration diagram of the reception data differential detection circuit 201.

The reception data differential detection circuit 201 includes a first delay circuit 251, a second delay circuit 252, a first multiplication circuit 253, a second multiplication circuit 254, and an addition circuit 2
55, a third multiplication circuit 256, and a fourth multiplication circuit 25
7 and a subtraction circuit 258.

The first delay circuit 251 stores I signal data for one symbol and delays it by one cycle. The second delay circuit 252 stores one symbol of Q signal data and delays it by one cycle. First multiplication circuit 2
53 multiplies the I signal data at the current time by the I signal data one cycle before stored in the first delay circuit 252. The second multiplication circuit 254 calculates the current time Q
The signal data is multiplied by the Q signal data one cycle before stored in the second delay circuit 253. Addition circuit 2
55 denotes a first multiplication circuit 253 and a second multiplication circuit 254
And the output of. The added output becomes the I signal component (DI) of the differential reception data.

The third multiplication circuit 256 calculates the Q of the current time.
The signal data is multiplied by the I signal data one cycle before stored in the first delay circuit 251. The fourth multiplying circuit 257 multiplies the I signal data at the current time by the Q signal data one cycle before stored in the second delay circuit 252. The subtraction circuit 258 subtracts the output of the fourth multiplication circuit 257 from the output of the third multiplication circuit 256. The subtracted output is the Q signal component (D
Q).

That is, the reception data differential detection circuit 201
Is (DI, DQ) = (I _k , Q _k ) × (I _k−1 , Q _k−1 ) ^? = (I _k × I _k−1 + Q _k × Q _k−1 , Q _k × I _{k −1} −I _k × Q _k−1 ). Here, k is a symbol number, (I
_k-1 , Q _k-1 ) ^? is a complex conjugate of (I _k-1 , Q _k-1 ).

Since the synchronization word is BPSK-modulated, the Q component of the differential result is always zero,
It is not used when calculating the correlation at the subsequent stage. Therefore, the third multiplier 256 and the fourth multiplier 25 surrounded by a dotted line in FIG.
7 and the subtraction circuit 258 may be deleted.

Further, the synchronous word differential detection circuit 202
The circuit configuration is the same as that of the received data differential detection circuit 201. However, since the TAB signal (synchronization word) has a known value, the TAB differential detection circuit 202 does not need to be particularly provided if the differential operation result of the TAB signal is previously stored in the memory.

(Frame Correlation Circuit) FIG. 8A is a circuit configuration diagram of the frame correlation circuit 203.

The frame correlation circuit 203 includes an encoder 301
, Shift register 302 and first TAB memory 30
3, the second TAB memory 304, and the correlation calculator 305
And is provided.

First, the reception data correlation circuit 201
The I signal component (DI) of the differential received data is input for each symbol.

The encoder 301 receives the differential reception data (DI)
Outputs 0 when is a positive number, and outputs 1 when is a negative number. The encoding is performed in order to reduce the circuit scale of the correlation circuit. By performing encoding in this way, it is equivalent to performing a hard decision on the input symbol that has been differentiated, and calculating a correlation using the result of the hard decision. The output of the encoder 301 is input to the shift register 302.

The shift register 302 shifts the differential reception data every cycle. The number of stored symbols is 192 symbols.

The first TAB memory 303 stores a differential synchronization word w1 for 19 symbols. Second TA
The B memory 304 stores a differential synchronization word w for 19 symbols.
2 / w3 is stored.

The first TAB memory 303 and the second TA
The reason that the B memory 304 stores only data for only 19 symbols is as follows.

The synchronization words w1, TMCC and synchronization words w2 / w3 in a state where the symbols are not differentiated are shown in FIG.
As shown in (A), each is composed of 32 symbols, 128 symbols, and 32 symbols. Here, the synchronization words are all known, and their values are known in advance on the receiving side. However, in BS digital broadcasting, convolutional coding or trellis coding with a constraint length of 7 is performed as an inner code coding method. Therefore, the value of the first 12 symbols of the synchronization word is affected by the past data,
Not known. Therefore, the symbols for which correlation can be obtained in the synchronization word are only for the latter 20 symbols. Further, in the correlation circuit, the received data is differentiated between symbols. Therefore, as shown in FIG. 9B, the number of known symbols that can be correlated is reduced by one symbol.

The data of 20 symbols of the synchronization word w1 have the following values. w1 = 1110_1100_1101_0010_10
[0098] When the differential value of w1 is obtained, the following values are obtained. w1 (Diff) = 001 — 1010 — 1011 — 1011
_1100 Data for 20 symbols of the synchronization word w2 has the following values. w2 = 0000 — 1011 — 0110 — 0111 — 01
11 The data for 20 symbols of the synchronization word w3 has the following values. w3 = 1111_0100_1001_1000_10
When the synchronization words w1 and w2 are differentiated, the following values are obtained. w2 (Diff) = w3 (Diff) = 000 — 1110 — 11
01_0100_1100 The correlation calculator 305 includes 19 calculators for calculating the correlation of the synchronization word w1 and 19 calculators for calculating the correlation of the synchronization words w2 / w3. Sync word w
The 19 arithmetic units that calculate the correlation of 1 receive the value stored in the 14th to 33rd symbols of the shift register 302 as i1 and input the value to the first TAB memory 3.
03 (ie, the differential symbol of the synchronization word w1) is input as i2. The w2 operation unit calculates the 173rd symbol of the shift register 302 through the 19th symbol.
The value stored in the two symbols is input as i1,
The value stored in the second TAB memory 304 (ie,
The differential symbol of the synchronization word w2 / w3) is input as i2.

Each computing unit performs a computation as shown in FIG.

That is, S0 = f (i1, i2) + Sif (i1, i2) becomes 1 when i1 = i2, and i
When 1 ≠ i2, the function is −1. Also, i1
Is a value stored in the shift register 302, i2
Is a value stored in the TAB memory.

In other words, the correlation calculator 305 is nothing less than calculating the inner product of the difference reception data and the difference synchronization word as described below. diff (I, Q) ・ diff (TAB) = diff (I, Q) [0] * diff (TAB) [0]
+ diff (I, Q) [1] * diff (TAB) [1] + ... Here, “•” indicates an inner product, and “*” indicates f (i1, i
2) represents the operation.

Then, the operation results of all the 38 arithmetic units are cumulatively added for each cycle, and the cumulative addition value for each cycle is output as correlation value data.

Accordingly, when the correlation is highest, the received data correlation circuit 201 outputs a value of 38 as the correlation value data.

Although the circuit for obtaining the correlation value sequentially for each cycle is shown here,
Alternatively, the calculation may be performed in a tournament type, or a final correlation value may be obtained by repeatedly using a calculator.

(IIR Filter) Next, the IIR filter 204 will be described.

FIG. 10 is a circuit diagram of the IIR filter 204.

The IIR filter 204 includes the first amplifier 3
51, an adder 352, a shift register 353, and a second amplifier 354.

The first amplifier 351 receives the correlation value data output from the frame correlation circuit 205. First
Multiplies the correlation value data by a predetermined gain K. The correlation value data multiplied by the gain K is added to the adder 35.
2 is supplied.

The adder 352 adds the output from the first amplifier 351 and the output from the second amplifier 354.
The addition result is supplied to the shift register 353 and output as a filtering result of the correlation value data.

The shift register 353 is a register having the number of words (39936 words) corresponding to the number of symbols included in one frame. The shift register 353 stores the correlation value data in the order of the input data, and shifts the stored correlation value data every cycle. That is,
The shift register 353 delays the correlation value data by one frame. The correlation value data delayed by one frame stored in the register of the last stage is supplied to the second amplifier 354.

The second amplifier 354 is connected to the shift register 3
The correlation value data output from 53 is multiplied by a gain (1-K). The result of the multiplication is supplied to the adder 532.

In such an IIR filter 204, the correlation value data at the current time and the correlation value data output one frame before are appropriately weighted and added. That is, the correlation value data extracted at each frame interval is weighted appropriately and averaged. The gain K for determining the weight has a function of determining the noise band.

(Synchronization detection circuit) Next, the synchronization detection circuit will be described.

FIG. 11 shows a circuit configuration diagram of the synchronization detection circuit 206, and FIG. 12 shows a state machine for performing flag control of the synchronization detection circuit 206.

The synchronization detection circuit 206 is composed of the logic circuit shown in FIG. 11 and the state machine 550 shown in FIG.
And performs a frame synchronization pull-in operation (backward protection) for detecting a frame start position from the correlation value data filtered by the IIR filter 204, and a frame synchronization protection operation after frame synchronization is established (forward protection). Circuit.

The logic circuit compares the averaged correlation value output from the IIR filter 204 with a predetermined comparison value, and ensures that the current symbol position is the frame synchronization position (synchronization word w1, (a position where w2 / w3 occurs), a synchronization position determination operation for determining whether or not a frame start flag (FST flag) indicating a frame start position, and a superframe start flag (FST flag) indicating a superframe start position. (SFST flag).

In the state machine 550, control is performed by dividing the state into a state in which frame synchronization is being pulled in (backward protection state) and a state in which frame synchronization is maintained (forward protection state). The state machine 550 issues a synchronization establishment flag “lock” indicating whether or not the frame synchronization is held (forward protection state), and supplies it to the logic circuit. This synchronization establishment flag is made valid (1) when synchronization is established, and made invalid (0) when synchronization is being pulled. Further, the state machine 550 issues a load flag ld4 for loading initial values of a counter and a register provided in the logic circuit. This load flag ld4 is effective for the load timing of the initial value (1).
And invalid (0) at other timings.

First, a specific circuit configuration of the logic circuit shown in FIG. 11 will be described.

The synchronization detection circuit 206 is provided for the first comparator 50
1, the selector 502, the main synchronization determination circuit 503, and N
AND circuit 504, symbol counter 505, and second
, A third comparator 507, a register 508, a fourth comparator 509, and a synchronization interval determination circuit 5.
10, the frame counter 511, and the fifth comparator 51
2 and an AND circuit 513.

The first comparator 501 has the averaged correlation value Corr output from the IIR filter 204,
A preset comparison value Th is input. The first comparator 501 compares the correlation value Corr with the comparison value Th, and is effective when Corr ≧ Th (1), and Corr <T
Outputs invalid (0) when h.

The comparison value Th is obtained when the synchronization is pulled in (at the time of backward protection) and when the synchronization is maintained after the synchronization is established (at the time of forward protection).
The value is switched by the selector 502. This switching is controlled by a synchronization establishment flag lock output from the state machine 550. The comparison value Th used during synchronization pull-in is larger than the comparison value Th used during synchronization holding. This is to determine the frame start position under a more severe condition than when synchronizing, and to prevent synchronizing at an incorrect position.

The main synchronization determination circuit 503 determines whether the current symbol position is a frame synchronization position (a position where a synchronization word is generated) or not (ok, n).
g). This main synchronization determination circuit 503
Are a first AND circuit 531 and a second AND circuit 53
And 2. The first AND circuit 531 includes:
An AND logic operation is performed on the comparison result of the first comparator 501 and the determination operation valid flag EN. First AND circuit 53
The operation result of 1 is output as an ok flag. The second AND circuit 531 performs an AND logical operation on the inverted signal of the comparison result of the first comparator 501 and the determination operation valid flag EN. The operation result of the second AND circuit 531 is ng
Output as a flag.

Here, the determination operation valid flag EN is set to NA
Issued from the ND circuit 504. NAND circuit 504
Is a synchronization establishment flag lock and a synchronization position flag Ti that indicates a scheduled position of a synchronization word when synchronization is established.
A NAND operation is performed on the inverted signal of ming, and a determination operation valid flag EN is issued. This determination operation valid flag EN is always valid (1) at the time of synchronization pull-in (at the time of backward protection). In addition, when the synchronization operation is maintained (at the time of forward protection), the determination operation validity flag is made valid (1) only at the position where the synchronization word is to be generated, and is made invalid (0) otherwise.

The synchronization position determination result (ok, ng) issued by the main synchronization determination circuit 503 has the following meaning. (0, 0): No determination operation is performed (synchronization is established, but it is not a synchronization word occurrence position) (0, 1): Not synchronization position (1, 0): Synchronization position ( 1,1): Not defined.

The symbol counter 505 is a counter circuit that counts the number of symbols. Symbol counter 5
05 periodically counts the number of symbols of one frame (0 to 39935). That is, the symbol counter 5
05 increments the symbol clock,
When the value becomes 39935, the counter value becomes 0 next. The symbol counter 5
05 has a counter value loading function. When the load flag ld4 provided from the state machine 550 is set to be valid (1), the symbol counter 505 is “1”, which is the next value of “191” indicating the expected position of the synchronization word (end symbol position of TAB2). 192 "
Load as a counter value. Here, the timing at which the count value “192” is loaded into the symbol counter 505 is determined when the synchronization position is first discovered immediately after the start of the synchronization processing (immediately after the reset) (that is, the main synchronization determination circuit 503 is firstly executed after the reset). Ok flag is valid (1)
And when frame synchronization is established (including when synchronization is once lost and synchronization is established again). In the symbol counter 505, the carry-out flag co becomes valid (1) at the timing when the counter value reaches the final value of "39935".

When the count value of the symbol counter 505 becomes “191”, which is the symbol number of the frame synchronization detection symbol position (end symbol position of TAB2), the second comparator 506 outputs the synchronization position flag Timin.
Let g be valid (1). This synchronous position flag Timin
g is the expected position of the synchronization word (the end symbol position of TAB2) when frame synchronization is established.
Will be shown. In the synchronization position flag Timing, the synchronization establishment flag lock is valid (1).
Is reflected in the determination operation valid flag EN only when

The third comparator 507 validates the FST flag indicating the frame start position when the count value of the symbol counter 505 becomes “0” which is the symbol number of the frame start position (1). The FST flag is invalidated (0) at other symbol timings.

The register 508 has a main synchronization judgment circuit 503.
When the ok flag becomes valid (1), the count value of the symbol counter 505 is fetched and held. That is, the register 508 holds the count value generated by the symbol counter 505 when the main synchronization determination circuit 503 determines that the position is the synchronous position. The register 508 has a register value loading function. When the load flag ld4 from the state machine 550 is set to valid (1), the register 508 indicates the frame synchronization position (the symbol number of the end position of TAB2). 191 "is loaded as the register value.

The fourth comparator 509 compares the count value of the symbol counter 505 with the count value of the register 508. As a result of comparison, if the values match, the output is valid (1), and if the values do not match, the output is invalid (0).

The synchronization interval determination circuit 510 is a circuit for determining whether or not the ok flag is issued at every frame interval (39936 symbols). The synchronization interval determination circuit 510 determines whether the generation interval of the ok flag is one frame period or not (ok2, ok2).
ng2). Specifically, the synchronization interval determination circuit 5
Reference numeral 10 includes a third AND circuit 533 and a fourth AND circuit 534. Third AND circuit 533
Performs an AND logical operation on the comparison result of the fourth comparator 509 and the ok flag. The calculation result of the third AND circuit 533 is output as an ok2 flag. 4th AND
The circuit 534 performs an AND logic operation on the inverted signal of the comparison result of the fourth comparator 509 and the ok flag. Fourth A
The calculation result of the ND circuit 534 is output as an ng2 flag.

The synchronization interval determination result (ok2, ng2) output from the synchronization interval determination circuit 510 is the same as the previous ok
Symbol counter 5 when the flag becomes valid (1)
This is a result of comparing the count value of the symbol counter 05 with the current count value of the symbol counter 505. In other words, the synchronization interval determination circuit 510 determines whether or not the counter value determined as the previous synchronization position matches the counter value determined as the current synchronization position. That is, since the symbol counter 505 generates a count value in one frame period, the synchronization interval determination circuit 510 determines whether or not the synchronization position is generated in one frame period. Here, if the synchronization position continues to be generated in one frame period, it is considered that the synchronization position is likely to be a synchronization position of the frame. Therefore, if the ok2 flag is continuously generated, it can be determined that the transition from the synchronization pull-in state to the synchronization establishment state may be performed. In the state machine 550 described later, when the ok2 flag is issued three times in succession, the state machine 550 is shifted to the forward protection state in which synchronization is established.

On the other hand, the count value and the register value at the time of synchronization pull-in can be used to pull in frame synchronization even if the symbol number of the received data is not synchronized. The circuit configuration is such that values and register values are loaded to correct values. Therefore, even if the synchronization is lost from the synchronization state, the symbol counter 505 does not initialize or stop the count value, continuously counts from the synchronization holding state, and shifts to the synchronization pull-in state. Can be.
Therefore, the correlation value becomes low at the frame synchronization position due to some noise, and even if the frame synchronization is lost, the counter value remains held, or
Even if the determination result is ok at a position other than the synchronization position by accident during re-pulling, the FST flag will continue to be issued correctly.

The synchronization interval determination result (ok2, ng2) issued by the synchronization interval determination circuit 510 has the following meaning. (0, 0): No determination operation is performed (the ok flag is not valid (1) and is not a synchronous position) (0, 1): The interval from the previous ok flag is one frame cycle Not (1, 0): The interval from the previous ok flag is one frame cycle. (1, 1): Not defined.

The frame counter 511 is a counter for counting the carry-out timing of the symbol counter 505 in eight count cycles. The frame counter 511 has a function of resetting a counter value, and outputs an F signal from a superframe synchronization circuit 205 described in detail later.
The counter value is reset to 0 by the ST0 flag (flag indicating frame number 0). After the synchronization of the superframe is established, the count value of the frame counter 511 indicates the frame number.

The fifth comparator 512 is valid (1) when the count value of the frame counter 511 is 0.
Becomes

The AND circuit 513 includes a third comparator 507
And the comparison result from the fifth comparator 512 by AND logic operation of the FST flag output from the
Issues an SFST flag indicating the start position of the superframe. That is, the start position of the frame whose frame number is 0 is output as the start position of the superframe.

As described above, in the synchronization detection circuit 206, the frame start flag (FS) indicating the synchronization position of the frame is set.
T flag) and a super frame flag (SFST flag) indicating the synchronization position of the super frame.

Next, the operation of the synchronization detection circuit 206 will be described with reference to the state machine shown in FIG.

An ok flag, an ng flag, an ok2 flag, an ng2 flag, and a reset flag are input to the state machine 550.

The state machine 550 outputs a synchronization establishment flag lock and a load flag ld4 of a counter value and a register value.

The state machine 550 has the following internal states M and states 0 to 7 as internal states. State M: State immediately after reset State 0: Asynchronous state in synchronous word position search state (backward protection) State 1: Asynchronous state in synchronous word position confirmation state (backward protection) State 2: Synchronous word position confirmation state Asynchronous state (backward protection) State 3: Asynchronous state in synchronization word position confirmation state (backward protection) State 4: Synchronization state in synchronization word position confirmation state (forward protection) State 5: Synchronization word position confirmation Synchronization state in state (forward protection) State 6: Synchronization state in synchronization word position confirmation state (forward protection) State 7: Synchronization state in synchronization word position confirmation state (forward protection).

Hereinafter, each state will be described.

--State M --- First, the state machine 550 makes a transition to state M when a reset flag is input. At this time, the counter value of the symbol counter 505 and the register value of the register 508 are in an undefined state. When the ok flag becomes valid (1), the load flag ld4 becomes valid (1).
And the counter value of the symbol counter 505 is “19”.
2 ”is loaded, and“ 19 ”is
1 ". Then, the state transits to the state 1.

In this state M, the synchronization establishment flag l
Ock is invalid (0), and the comparison value Th for pull-in is input to the first comparator 501. Further, the determination operation valid flag EN input to the synchronous position determination circuit 503 is always valid (1), and the correlation value Corr ≧
If the comparison value is Th, the ok flag is always issued.

--State 1 --- State 1 is a backward protection state of frame synchronization pull-in, and the state changes next according to the synchronization interval determination result (ok2, ng2). When the ok2 flag becomes valid (1), the state transits to the next state 2, and when the ng2 flag becomes valid (1), the state transits to state 0. Here, in this state 1, the counter value of the symbol counter 505 does not always accurately indicate the symbol position of the data being transmitted, but the counter value when the ok flag becomes valid (1). If the counter value matches the previous counter value, the state transitions to the next state. That is, if the issuance cycle of the ok flag is one frame, the synchronization interval determination result ok2 flag is issued, so that the state transits to the next state 2. If the issuance cycle of the ok flag is not one frame, ng2 Since the flag is issued, the state returns to state 0. In this state 1, the load flag ld4 is invalid (0), and the synchronization establishment flag is invalid (0).

-State 2-State 2 is also a backward protection state of frame synchronization pull-in, like state 1, and the synchronization interval determination result (ok2, ng
The state changes next due to 2). When the ok2 flag becomes valid (1), the state transits to the next state 3, and when the ng2 flag becomes valid (1), the state transits to state 0. Also in this state 1, the load flag ld4 is invalid (0) and the synchronization establishment flag is invalid (0).

--State 3 --- State 3 is a backward protection state of frame synchronization pull-in, and the state changes next according to the synchronization interval determination result (ok2, ng2). If the ok2 flag becomes valid (1), the state transits to the next state 4, and if the ng2 flag becomes valid (1), the state transits to state 0.

Here, in this state 3, when the ok flag becomes valid (1), the load flag ld4 is made valid (1), "192" is loaded into the counter value of the symbol counter 505, and the register 508 is set. "191" is loaded to the register value. Further, when transitioning to the next state 4, the synchronization establishment flag lock is made valid (1), and thereafter, the logic circuit 500 is operated in the synchronization established state. That is, in the state machine 550, if the ok flag issuance position has the same count value three times in a row, it is determined that frame synchronization has been established. Transition to the protection state. After that, the synchronization establishment state (state 4, state 5,
In states 6 and 7), it is determined that the counter value of the symbol counter 505 accurately indicates the symbol position of the data being transmitted, and the subsequent processing is performed.

--State 4 --- State 4 is a forward protection state when frame synchronization is established, and the state changes next according to the synchronization position determination result (ok, ng). When the ok flag becomes valid (1), this state 4 is repeated, and when the ng flag becomes valid (1), the state 4 transits. In this state 4, the synchronization establishment flag lock is valid (1), and the comparison value Th for maintaining synchronization is set.
Is input to the first comparator 501. The determination operation valid flag EN input to the synchronous position determination circuit 503 is
It becomes valid (1) only when the counter value of the symbol counter 505 becomes 191. Only at this timing, the comparison between the correlation value Corr and the comparison value Th is performed.

-State 5-State 5 is a forward protection state at the time of frame synchronization establishment, and the state changes next according to the synchronization position determination result (ok, ng). When the ok flag becomes valid (1), the state changes to state 4, and when the ng flag becomes valid (1), the state changes to state 6. In this state 5, as in the state 4, the synchronization establishment flag lock is valid (1).

-State 6-State 6 is a forward protection state at the time of frame synchronization establishment, and the state changes next according to the synchronization position determination result (ok, ng). When the ok flag becomes valid (1), the state changes to state 4, and when the ng flag becomes valid (1), the state changes to state 7. In this state 6, the synchronization establishment flag lock is valid (1) as in the state 4.

-State 7-State 7 is a forward protection state at the time of frame synchronization establishment, and the state changes next according to the synchronization position determination result (ok, ng). When the ok flag becomes valid (1), the state changes to state 4, and when the ng flag becomes valid (1), the state changes to state 0. In this state 7, the synchronization establishment flag lock is valid (1) as in the state 4.

Here, in this state 7, when the ng flag becomes valid (1), it indicates that synchronization has been lost from the synchronization holding state (forward protection state), and thereafter, the state shifts from state 0 to the pull-in state. In this way, in the state machine 550, when synchronization is lost four times in a row, the state machine 550 shifts to the retracted state again. , So that the pull-in operation is not performed.

--State 0 --- State 0 is a backward protection state of frame synchronization pull-in, and the state changes next according to the synchronization interval determination result (ok, ng). When the ok flag becomes valid (1), the state transits to the next state 1, and when the ng flag becomes valid (1), this state 0 is repeated. Here, in this state 0, the counter value of the symbol counter 505 is not newly updated.
Therefore, for example, even if the synchronization is accidentally lost and the synchronization is pulled in, the count value of the symbol counter 505 is not reset, and the counting is continued as it is. Although the count value of the symbol counter 505 does not always accurately indicate the symbol position of the data being transmitted, the counter value when the ok flag becomes valid (1) is equal to the previous counter value. Is determined, whether the ok flag issuance cycle is one frame or not can be reliably determined.

(Super Frame Synchronization Circuit) Next, the super frame synchronization circuit will be described.

The superframe synchronization circuit 205 calculates the correlation between the received data and the synchronization word, detects whether the subsequent synchronization word is w2 or w3, and detects the superframe start position. At the same time, the superframe synchronization circuit 205 sends the received data and the synchronization word (w
1) is calculated, and it is detected whether or not the synchronization word w1 is inverted, and it is detected whether or not the carrier wave synchronization is rotated by 180 degrees and synchronization is established. Note that the superframe synchronization circuit 205 may operate after the carrier wave synchronization is established. Therefore, the correlation can be detected without performing a differential operation between symbols in order to remove a carrier error.

FIG. 13 shows the configuration of the superframe synchronization circuit 205. Super frame synchronization circuit 205
Is composed of a correlation circuit 561 and a synchronization detection circuit 562, as shown in FIG.

The correlation circuit 561 sequentially receives the I signal component of the received data for each symbol, and
The correlation with the synchronization words w1 and w2 is calculated. Correlation circuit 5
61 outputs the calculated correlation value for each symbol. The correlation value data output from the correlation circuit 561 is supplied to the synchronization detection circuit 562.

Synchronization detection circuit 562 detects the start position of frame number 0 (ie, the start position of the superframe) based on the correlation value data output from correlation circuit 561, and outputs an FST0 flag. Further, the synchronization detection circuit 562 detects whether or not the carrier wave synchronization is being rotated by 180 degrees based on the correlation value data output from the correlation circuit 561, and synchronizes with the timing signal to generate a 180-degree phase inversion signal. Is output.

FIG. 14A is a circuit diagram of the correlation circuit 561.

The correlation circuit 561 includes an encoder 571, a shift register 572, a first TAB memory 573, a second TAB memory 574, a w1 correlation calculator 575,
and a w2 correlation calculator 576.

First, the I signal component (I) of the received data is input to the correlation circuit 561 for each symbol.

The encoder 571 outputs 0 when the received data (I) is a positive number, and outputs 1 when the received data (I) is a negative number. The encoding is performed in order to reduce the circuit scale of the correlation circuit. By performing encoding in this way, it is equivalent to performing hard decision on an input symbol and calculating a correlation using the result of the hard decision. Encoder 57
The output of 1 is input to the shift register 572.

The shift register 572 shifts the received data every cycle. The number of stored symbols is, for example, 192 symbols.

The first TAB memory 573 stores a synchronization word w1 for 20 symbols. The second TAB memory 574 stores a synchronization word w2 for 20 symbols.

The data for 20 symbols of the synchronization word w1 has the following specific values. w1 = 1110_1100_1101_0010_10
00 The data for 20 symbols of the synchronization word w2 has the following values. w2 = 0000 — 1011 — 0110 — 0111 — 01
The 11 w1 correlation calculator 575 includes 20 calculators for calculating the correlation of the synchronization word w1. The w1 correlation calculator 575 receives the value stored in the thirteenth to thirty-third symbols of the shift register 572 as i1, and outputs the value stored in the first TAB memory 573 (ie, the synchronization word w1). Input as i2. The w2 correlation calculator 576 receives the value stored in the 172th to 192th symbols of the shift register 572 as i1, and stores the value stored in the second TAB memory 574 (ie, the synchronization word w2). Is input as i2.

Each arithmetic unit performs an operation as shown in FIG.

That is, S0 = f (i1, i2) + Sif (i1, i2) becomes 1 when i1 = i2, and i
When 1 ≠ i2, the function is −1. Also, i1
Is the value stored in the shift register 575, i
Is a value stored in the TAB memory.

Then, the operation results of all the 20 operation units of the w1 correlation operation unit 575 are all added up every cycle, and
The accumulated value for each cycle is output as w1 correlation value data. Also, the operation results of all the 20 operation units of the w2 correlation operation unit 576 are cumulatively added for each cycle, and the cumulative addition value for each cycle is output as w2 correlation value data.

Although the shift register 572 is a series of 192 shift registers, it is not necessary to output w1 correlation value data and w2 correlation value data at the same time. Is also good. In this case, the correlation result with w1 is calculated at the timing when TAB1 is all input, the correlation result is held, and the correlation result with w2 is calculated at the timing when all TAB2 is input. The result may be held and supplied to the synchronization detection circuit 562.

Next, the synchronization detecting circuit will be described.

The synchronization words of frame number 0 are w1 and w
It is a combination with 2. On the other hand, frame number 0
The synchronization words of the other frames are a combination of w1 and w3. When the carrier synchronization is rotated by 180 degrees, all the transmission data are bit-inverted. Therefore, the detection of the first frame (frame number 0) of the superframe and the detection of the phase inversion state of the carrier synchronization are as follows: It is determined whether the received symbol of TAB1 at the frame synchronization timing is normal or inverted. It is determined whether the received symbol of TAB2 is w2 or w3. It can be done by doing.

Here, in order to evaluate the normal / inverted state of the received data, w1 obtained at the generation timing of the synchronization word is used.
It is sufficient to evaluate whether the correlation value data is an integer or a negative number. If the w1 correlation value data is a positive number, the received data becomes normal rotation. If the w1 correlation value data is a negative number, the received data is inverted. That is, when the carrier wave synchronization is rotated by 180 degrees, all the transmission data is bit-inverted, so that the w1 correlation value data has the lowest correlation value (specifically, the circuit of FIG. 14 shown earlier). In this case, the value is -20.)

Whether the received symbol of TAB2 is w2 or w2
In order to determine whether it is 3, it is first evaluated whether the w2 correlation value data at the frame synchronization timing is an integer or a negative number. If TAB1 is normal rotation and TAB2 is normal rotation, the synchronization word described in TAB2 is w2. If TAB1 is normal and TAB2 is inverted, the synchronization word described in TAB2 is w3. If TAB1 is inverted and TAB2 is non-inverted, the synchronization word described in TAB2 is w3. If TAB1 is inverted and TAB2 is inverted, the synchronization word described in TAB2 is w2.

If TAB2 is w2, it is the first frame of the super frame (frame number 0), so the FST0 flag is set to valid (1), and TAB2 is set to w3.
If so, the frame is not the first frame of the super frame (frame numbers 1 to 7), and the FST0 flag is invalidated (0).

More specifically, as a circuit configuration example of the synchronization detection circuit 562, as shown in FIG.
1, the second comparison circuit 582, and the EXOR circuit 583
, An inversion circuit 584, a first AND circuit 585, a second AND circuit 586, and a latch circuit 587.

The first comparison circuit 581 compares whether the w1 correlation value data is a positive number or a negative number. The first comparison circuit 581 makes the output valid (1) if the w1 correlation value data is 0 or more, and invalidates (0) if the w1 correlation value data is less than 0.

The second comparing circuit 582 compares whether the w2 correlation value data is a positive number or a negative number. The second comparison circuit 582 makes the output valid (1) if the w2 correlation value data is 0 or more, and makes the output invalid (0) if the w2 correlation value data is less than 0.

The EXOR circuit 583 is connected to the first comparison circuit 5
If the output of 81 and the output of the second comparison circuit 582 match, the output is made valid (1), and if they do not match, the output is invalid (0).
And

The inverting circuit 584 includes a first comparing circuit 581
The output of is inverted.

The first AND circuit 585 performs an AND logical operation on the synchronization word generation timing “timing” and the output of the EXOR circuit 583, and masks a detection output other than the synchronization word generation timing “timing”.

The second AND circuit 586 performs an AND logical operation on the synchronization word generation timing “timing” and the output of the inversion circuit 585 to obtain the synchronization word generation timing “t”.
Mask the detection output other than in the iming.

The register circuit 587 is a register to which writing is permitted at the synchronization word generation timing, and the output value of the second AND circuit 586 is written.

Synchronous detection circuit 56 having the above circuit configuration
2, the output of the first AND circuit 585 is output as the FST0 flag, and the output of the register circuit 587 is 18
It is output as a 0 degree phase inversion signal.

[0224] the carrier synchronization section Next, a more detailed description about the carrier synchronization section 134.

FIG. 16 is a block diagram of the carrier synchronizer 134.

The carrier synchronizer 134 includes a timing control circuit 601, an error detection circuit 602, a loop filter 604, and a VCO (Voltage Controlled Oscillator).
604.

A frame start flag (FST flag) is input to the timing control circuit 601 from the frame synchronization circuit 133 shown in FIG. The timing control circuit 601 counts the number of symbols from the FST flag, thereby defining a symbol timing that is always BPSK-modulated in BS digital broadcasting such as TMCC data, TAB signal (synchronization word), and burst signal. To identify. The timing control circuit 601 generates a BPSK flag that is valid (1) when the symbol is a TMCC data, a TAB signal, or a burst signal, and supplies the BPSK flag to the loop filter 602.

The error signal detection circuit 602 receives the I signal data and the Q signal data output from the waveform shaping filters 130 and 131 shown in FIG. The error amount detection circuit 602 calculates a phase error amount or a frequency error amount Δθ from the original signal point of BPSK with respect to the input symbol. The detected error amount Δθ is determined by the loop filter 603
Supplied to

The loop filter 603 has, for example, a delay element of first order or more, and performs loop filtering by weighting the input error amount Δθ by a predetermined amount. The loop filter 603 converts the filtered error amount Δθ into VC
Supply it to O604. Here, this loop filter 60
In No. 3, the delay element is updated only at the TMCC, TAB, and burst positions according to the BPSK flag. Therefore, V
Updating of oscillation frequency for CO604 is TAB, TMC
C, only at the burst position, at other positions,
The last control value is retained. In other words, the carrier synchronization operation is performed intermittently using only the error amount Δθ of the symbol modulated by BPSK.

For example, the loop filter 603 includes a first multiplier 611 that multiplies the error amount Δθ by a constant K, and a second multiplier 612 that multiplies the filter output by a constant (1−K).
, An adder 613 that adds the output of the first multiplier 611 and the output of the second multiplier 612, and a register 614 that delays the output of the adder 613. In this case, the register 614, the multiplier 611, and the adder 613 constitute a delay element. This register 614
, The BPSK flag is input as an enable signal,
Only when the BPSK flag is valid (1),
Update internal data.

The VCO 604 is composed of, for example, an accumulator and a (cos θ, sin ⁻¹ θ) ^* circuit. The output from the loop filter 603 is cumulatively added at Mod 360 °, the addition result is converted into a quadrature signal, and a carrier wave error And outputs a phase rotation correction signal (RI, RQ) having a frequency corresponding to. ^{* Indicates} a complex conjugate.

The phase rotation correction signal thus generated is supplied to the carrier correction circuit 129 shown in FIG. The carrier correction circuit 129 removes the carrier error component included in the received signal by complexly multiplying the received signal by the phase rotation correction signal.

As described above, the carrier synchronizer 134 specifies the symbol positions of the TAB, TMCC, and burst signals based on the frame start flag (FST) obtained by the frame synchronizer 133, and includes these symbols. The carrier error is corrected according to the phase and frequency error amounts.

After the carrier synchronizer 134 synchronizes the carrier, the superframe is synchronized and the TMCC information is decoded. Therefore, once the carrier is synchronized, it is possible to specify not only the TAB, TMCC, and burst position but also the modulation method of all symbols by referring to the TMCC information.

Therefore, after carrier wave synchronization is established, T
Carrier synchronization may be performed by detecting the amount of phase error of all symbols without intermittently performing carrier synchronization using only the AB, TMCC, and burst positions.

FIG. 17 is a circuit diagram of a carrier synchronizer 650 for detecting a phase error amount of all symbols and performing a carrier synchronization process.

The timing control circuit 651 receives a frame start flag (FST flag), a superframe start flag (SFST) and TMCC information. The timing control circuit 651 analyzes the TMCC information, counts the number of symbols from the FST flag and the SFST flag, and generates a modulation scheme designation signal TM for specifying the modulation scheme of each symbol. The modulation method designation signal TM is supplied to the error amount detection circuit 652 and the loop filter 6.
53.

The error signal detection circuit 652 receives the I signal data and the Q signal data output from the waveform shaping filters 130 and 131 shown in FIG. The error amount detection circuit 652 calculates a phase error amount or a frequency error amount Δθ with respect to the input symbol. Here, the error amount detection circuit 652 calculates a phase error amount Δθ from a signal point corresponding to the supplied modulation scheme designating signal. For example, if the symbol is BPSK modulated, the phase error from the signal points of 0 and π is calculated. If the symbol is QPSK modulated, the phase error amount from the signal points of π / 4, 3π / 4, 5π / 4 and 7π / 4 is calculated. If the symbol is 8PSK-modulated, 0, π / 4, π / 2, 3π
The phase error amounts from the signal points of / 4, π, 5π / 4, 3π / 2 and 7π / 4 are calculated. The detected error amount Δθ is supplied to the loop filter 653.

The loop filter 653 performs filtering by varying the weight for the error amount Δθ. At this time, for example, the weight is changed between the TAB, TMCC, burst position and the main signal position, or the weight is changed according to the modulation method. For example, TAB, T
Large weighting is performed at the MCC and burst positions, and low weighting is performed at the main signal position. Also, BPSK is weighted the largest, 8PSK is weighted the least, and QPSK is weighted in the middle.

The loop filter 653 includes, for example, a first multiplier 661 for multiplying the error amount Δθ by a constant K.
A second multiplier 662 for multiplying the filter output by a constant (1-K), an adder 663 for adding the output of the first multiplier 661 and the output of the second multiplier 662, and an adder 6
63, and a register 664 for delaying the output. Here, the first multiplier 661 and the second multiplier 6
By changing the multiplier K of 62 according to the modulation method information TM, the loop band is changed, and by changing G, the loop gain is converted. It is possible to change the weighting.

Note that the function of the VCO 654 is
Same as 4.

Modification of IIR Filter Next, the IIR filter used in the frame synchronization unit 133
A modified example of the filter will be described.

In the IIR filter shown in FIG. 10, the number of words for one frame (39936 words) is used in order to average each correlation value data extracted for each frame interval.
Is used.

When the frame synchronization processing is performed, a frame start position is not established at the time of pull-in, and thus a memory capacity of one frame (39936 words) is necessarily required. However, after the frame synchronization is established, the synchronization detection circuit 206 at the subsequent stage needs only data of only the symbol of the timing of generation of the synchronization word. That is, after frame synchronization is established,
Filtering is performed only on the correlation value data at the synchronization word occurrence position.

In the BS digital broadcast receiving apparatus,
For example, a large amount of memory is used in a decoding circuit such as an RS decoder and a deinterleaver. However, these decoding circuits do not need to operate unless timing synchronization, frame synchronization, and carrier synchronization are established in the demodulation unit.

Here, when pulling in the frame synchronization, a memory used for a subsequent decoding circuit such as an error correction circuit or a deinterleaver is used, and after establishing the frame synchronization, a one-word delay memory is used. An IIR filter for switching the delay memory used for filtering between when the frame synchronization is pulled in and after it is established will be described.

FIG. 18 is a circuit diagram of the IIR filter. Here, an example using a memory used for the RS decoding unit 108 will be described.

The IIR filter 700 includes the first amplifier 7
01, an adder 702, an input selector 703, an error correction memory 704, a delay register 705, a selector 706, and a second amplifier 707.

The first amplifier 701 receives the correlation value data output from the frame correlation circuit 205. First
Amplifier 701 multiplies the correlation value data by a predetermined gain K. The correlation value data multiplied by the gain K is added to the adder 70.
2 is supplied.

An adder 702 adds the output from the first amplifier 701 and the output from the second amplifier 707.
The addition result is input to the input selector 703 and the delay register 70.
5 is supplied.

The input selector 703 is connected to the RS decoding unit 108
And the output data from the adder 702 are input. The input selector 703 is switched by the synchronization establishment flag lock output from the state machine 550 shown in FIG. The synchronization establishment flag lock is a flag that is valid (1) when frame synchronization is established and is invalid (0) when frame synchronization is pulled in. The input selector 703 is
When the synchronization establishment flag lock is valid (1), the data from the RS decoding unit 108 is input to the error correction memory 704, and when the synchronization establishment flag lock is invalid (0), the data from the adder 702 is input to the error correction memory. 70
Enter 4

When the synchronization establishment flag lock is valid (1), the error correction memory 704 stores the data in the internal address register so that it functions in the same manner as the FIFO for one frame of data (39936 words). Perform reading. When the synchronization establishment flag lock is invalid (0), data writing / reading is performed under the control of the RS decoding unit 108.

The delay register 705 is a register for storing data of one word. The delay register 705 is
Synchronous position flag Tim indicating the expected position of the synchronous word
ing is input as an enable signal. The synchronization position flag Timing is input from the synchronization detection circuit 206. The delay register 705 updates the data only when the synchronization position flag Timing is valid (1).

The output selector 706 receives the output data from the error correction memory 704 and the output data from the delay register 705. The input selector 703 is
It is switched by the synchronization establishment flag lock. In the output selector 706, the synchronization establishment flag lock is valid (1).
In the case of (1), the data from the delay register 705 is supplied to the second amplifier 707, and when the synchronization establishment flag lock is invalid (0), the data from the error correction memory 704 is supplied to the second amplifier 707.

The second amplifier 707 includes an output selector 70
For output data from 6. Multiply the gain (1-K). The result of the multiplication is supplied to the adder 702.

In such an IIR filter 700, when pulling in frame synchronization, the error correction memory 70
4, the correlation value data extracted at each frame interval is averaged with appropriate weighting. Then, after the frame synchronization is established, the error correction memory 704 is released. Then, the synchronization word (TAB) is stored in the delay register 705 for storing one word of data.
The correlation value data obtained at the generation timing of the signal is averaged with appropriate weighting.

Effects As described above, the BS digital broadcast receiving apparatus according to the embodiment of the present invention performs synchronization processing of the symbol timing of digital satellite broadcast transmission data, and subsequently performs synchronization processing of the digital satellite broadcast transmission data. The synchronization processing of the frame timing is performed by detecting the synchronization word that is present, and then the reception phase of at least the synchronization word is detected based on the frame synchronization timing, and the carrier synchronization processing is performed.

That is, in the BS digital broadcast receiving apparatus, the carrier synchronization processing is performed after the frame synchronization processing. Accordingly, the carrier synchronization processing can be performed with a very simple configuration, and even in the case of digital satellite broadcasting in which the modulation scheme changes dynamically, a symbol having a narrow phase between signal points such as QPSK or 8PSK can be used. , The BPSK-modulated symbol having a wide phase between signal points is detected and the carrier synchronization process is performed, so that the carrier synchronization process can be performed with high accuracy.

Further, the BS digital broadcast receiving apparatus detects difference data between symbols of the transmission data when setting the frame synchronization timing, and determines the correlation between the difference data of the transmission data and the difference data of the synchronization word. I am taking. Therefore, the position of the synchronization word can be specified with the carrier wave error removed, and the frame synchronization process and the carrier wave synchronization process can be performed with extremely high accuracy.

In the BS digital broadcast receiving apparatus, when setting the frame synchronization timing, the correlation value between the difference data of the transmission data and the difference data of the synchronization word is filtered at the frame period. The filtering is performed by, for example, IIR (Infinite Impulse Respo
nse) Filtering is performed using a filter.
Therefore, it is possible to eliminate the influence of noise or the like that occurs accidentally, and it is possible to more accurately perform the frame synchronization process and the carrier wave synchronization process.

In the BS digital broadcast receiving apparatus, after frame synchronization is established, filtering is performed only on the symbol at the position where the synchronization word occurs. When the frame synchronization is pulled in, filtering is performed using a decoding memory such as an error correction memory or a memory such as a deinterleaver that is not used before the frame synchronization is established.
Filtering is performed using a delay memory having a data capacity of a symbol. Therefore, the memory capacity required for filtering can be extremely reduced.

In the BS digital broadcast receiving apparatus, the synchronization position is detected by comparing the correlation value data with a predetermined value, and the interval between the synchronization positions is compared with the interval between the synchronization positions. To detect the synchronization interval. Then, using a symbol counter for counting the number of symbols of the transmission data in one frame period, after the above-mentioned synchronization interval becomes one frame interval continuously for a predetermined number of times, the count value is set as an initial value. Is set to a predetermined value, a frame start signal is issued. Therefore, the frame synchronization position can be reliably detected with a simple configuration, and the frame synchronization can be reliably maintained even after the frame synchronization is established.

In the BS digital broadcast receiving apparatus, the count value of the symbol counter is converted to transmission data based on the synchronization position detected by the synchronization position detection unit and the synchronization interval obtained by the synchronization interval detection unit. The frame synchronization process is controlled using a state machine that transitions between a synchronization pull-in state for synchronization and a synchronization holding state for holding a state in which the count value of the symbol counter is synchronized with the transmission data. . for that reason,
The frame synchronization processing method can be easily switched between the frame synchronization pull-in state and the frame synchronization protection state.

[0264]

In the digital satellite broadcast demodulating apparatus and method according to the present invention, the synchronization processing of the symbol timing of the digital satellite broadcast transmission data is performed, and then, the synchronization word included in the digital satellite broadcast transmission data is converted. By performing detection, it performs frame timing synchronization processing,
Subsequently, based on the frame synchronization timing, at least the reception phase of the synchronization word is detected and the carrier synchronization processing is performed.

That is, according to the present invention, the carrier synchronization process is performed after the frame synchronization process. Therefore, the carrier synchronization processing can be performed with a very simple configuration, and at the same time, even in the case of digital satellite broadcasting in which the modulation scheme changes dynamically, QPSK or 8PS
Without using a symbol with a narrow phase between signal points such as K,
Since the BPSK-modulated symbol having a wide phase between signal points is detected and the carrier synchronization process is performed, the carrier synchronization process can be performed with high accuracy.

In the present invention, when frame synchronization timing is determined, difference data between symbols of transmission data is detected, and correlation between the difference data of the transmission data and the difference data of the synchronization word is performed. Therefore, the position of the synchronization word can be specified with the carrier wave error removed, and the frame synchronization process and the carrier wave synchronization process can be performed with extremely high accuracy.

In the present invention, when the frame synchronization timing is set, the correlation value between the difference data of the transmission data and the difference data of the synchronization word is filtered at the frame period. The filtering is, for example, II
Filtering is performed using an R (Infinite Impulse Response) filter. Therefore, it is possible to eliminate the influence of noise or the like that occurs accidentally, and it is possible to more accurately perform the frame synchronization process and the carrier wave synchronization process.

In the present invention, after frame synchronization is established, filtering is performed only on the symbol at the position where the synchronization word occurs. At the time of frame synchronization pull-in, filtering is performed using a decoding memory such as an error correction memory or a memory such as a deinterleaver which is not used before frame synchronization is established. Filtering is performed using a delay memory having a data capacity of. Therefore, the memory capacity required for filtering can be extremely reduced.

In the present invention, the synchronization position is detected by comparing the correlation value data with a predetermined value, and further, the synchronization interval is detected by comparing the interval between the synchronization positions with the interval between the synchronization positions. I do. Then, using a symbol counter for counting the number of symbols of the transmission data in one frame period, after the above-mentioned synchronization interval becomes one frame interval continuously for a predetermined number of times, the count value is set as an initial value. Is set to a predetermined value, a frame start signal is issued. Therefore, the frame synchronization position can be reliably detected with a simple configuration, and the frame synchronization can be reliably maintained even after the frame synchronization is established.

According to the present invention, the synchronization value for synchronizing the count value of the symbol counter with the transmission data based on the synchronization position detected by the synchronization position detection unit and the synchronization interval obtained by the synchronization interval detection unit. The frame synchronization process is controlled using a state machine that transitions between a pull-in state and a synchronization holding state for holding a state in which the count value of the symbol counter is synchronized with the transmission data. Therefore, it is possible to easily switch the frame synchronization processing method between the frame synchronization pull-in state and the frame synchronization protection state.

Also, in the present invention, a carrier error is corrected by complexly multiplying transmission data consisting of rectangular coordinate signals by a rotation correction signal, and a phase rotation error amount is detected from the transmission data in which the carrier error has been corrected. Then, a rotation correction signal corresponding to the phase rotation error amount is generated, the phase rotation error amount of the transmission data in which the carrier wave error is corrected is calculated based on the modulation method of the synchronization word, and the number of symbols is counted from the frame synchronization timing. At least the symbol position of the synchronization word is specified, the phase rotation error amount of the specified symbol is filtered, and a rotation correction signal whose frequency and phase are controlled according to the filtered phase rotation error amount is generated. In this way, a carrier synchronization process is performed.

As a result, the carrier synchronization processing can be performed with a very simple configuration, and the QPSC can be used even in the case of digital satellite broadcasting in which the modulation method changes dynamically.
Since the BPSK modulated symbol having a wide phase between signal points is detected and the carrier synchronization processing is performed without using a symbol having a narrow phase between signal points such as K or 8PSK, the carrier synchronization processing can be performed with high precision. it can.

According to the present invention, after the carrier wave synchronization is established, the modulation method of the main signal is specified based on the superframe start start position and the TMCC information.
Carrier synchronization is performed by detecting not only the synchronization word, burst signal and / or TMCC signal but also the error amount of the main signal. Therefore, carrier wave synchronization can be performed more reliably.

[Brief description of the drawings]

FIG. 1 is a block diagram of a BS digital broadcast receiving apparatus to which the present invention is applied.

FIG. 2 is a block diagram of a demodulation unit of the BS digital broadcast receiving apparatus.

FIG. 3 is a diagram for explaining a superframe structure of a BS digital broadcast signal.

FIG. 4 is a diagram for explaining a frame structure of a BS digital broadcast signal.

FIG. 5 is a flowchart showing a synchronization processing procedure of the demodulation unit.

FIG. 6 is a block diagram of a frame synchronization unit of the demodulation unit.

FIG. 7 is a circuit diagram of a differential detection circuit of the frame synchronization unit.

FIG. 8 is a configuration diagram of a correlation circuit of the frame synchronization unit.

FIG. 9 is a diagram for explaining a data configuration of a synchronization word.

FIG. 10 is a configuration diagram of an IIR filter of the frame synchronization unit.

FIG. 11 is a circuit diagram of a synchronization detection unit of the frame synchronization unit.

FIG. 12 is a diagram showing a state machine of the synchronization detection unit.

FIG. 13 is a block diagram of a superframe synchronization circuit of the synchronization detection unit.

FIG. 14 is a configuration diagram of a correlation circuit of the superframe synchronization circuit.

FIG. 15 is a circuit diagram of a synchronization circuit of the superframe synchronization circuit.

FIG. 16 is a block diagram of a carrier synchronization section of the demodulation section.

FIG. 17 is a block diagram showing another example of the configuration of the carrier synchronizer.

FIG. 18 is a configuration diagram showing another configuration example of the IIR filter.

FIG. 19 is a block diagram showing a general transmission model when digital data is transmitted by performing digital quadrature modulation.

FIG. 20 is a diagram showing a signal point arrangement of QPSK and its eye pattern.

FIG. 21 is a diagram showing a signal point arrangement of 8PSK and its eye pattern.

[Explanation of symbols]

101 demodulator, 121 first multiplier, 122 second
Multiplier, 123 local oscillator, 124 90-degree phase shifter, 125 first low-pass filter, 126 second low-pass filter, 127 first analog-to-digital converter, 128 second analog-to-digital converter, 129
Carrier correction unit, 130 first waveform shaping filter, 1
31 second waveform shaping filter, 132 timing synchronization section, 133 frame synchronization section, 134 carrier synchronization section

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 5/44 H04N 7/20 630 7/20 630 H04L 27/22 C (72) Inventor Seishi Ono Tokyo 6-7-35 Kita-Shinagawa, Shinagawa-ku Sony Corporation F-term (reference) DD02 EE02 HH01 HH12 HH43 JJ02 MM13 MM33 MM36 MM56

Claims (32)

[Claims] 1. A digital satellite broadcast demodulator for demodulating a broadcast signal of digital satellite broadcast, a timing synchronizing means for synchronizing symbol timing of transmission data, and detecting a synchronization word from the transmission data synchronized with the timing. Frame synchronization means for detecting the frame synchronization timing of the transmission data; identifying at least the symbol position of the synchronization word based on the frame timing; detecting the reception phase of each symbol of the synchronization word; A digital satellite broadcast demodulator comprising a carrier synchronization means. 2. The frame synchronization means detects difference data between symbols of the transmission data, and correlates the difference data of the transmission data with the difference data of the synchronization word.
2. The digital satellite broadcast demodulator according to claim 1, wherein a frame synchronization timing of transmission data is detected. 3. The apparatus according to claim 1, wherein said frame synchronization means detects a frame synchronization timing of the transmission data by filtering a correlation value between the difference data of the transmission data and the difference data of the synchronization word in a frame cycle. Item 3. A digital satellite broadcast demodulator according to item 2. 4. The method according to claim 1, wherein the frame synchronization means compares the correlation value between the difference data of the transmission data and the difference data of the synchronization word with an IIR (Infi
4. The digital satellite broadcast demodulator according to claim 3, wherein filtering is performed using a filter (nite impulse response) to detect a frame synchronization timing of transmission data. 5. Decoding means for decoding demodulated transmission data, wherein the frame synchronization means has a delay register for delaying at least one symbol of data by one frame period, and at the time of pulling in frame synchronization timing, Using the memory of the decoding means, IIR filtering is performed by delaying the correlation values of all symbols in one frame by one frame period to detect the frame synchronization timing of the transmission data. Using the delay register, delaying the correlation value of at least one symbol at the symbol position of the frame synchronization timing by one frame period, performing IIR filtering, and detecting the frame synchronization timing of the transmission data. The digital satellite broadcast demodulator according to claim 4, . 6. A synchronous position detecting section for comparing the correlation value with a predetermined value to detect a synchronous position, and a synchronous interval by comparing the synchronous position interval with one frame interval. And a symbol counter that counts the number of symbols of the transmission data in one frame cycle. The symbol counter is configured such that, after the synchronization interval has become one frame interval continuously for a predetermined number of times, 3. The digital satellite broadcast demodulator according to claim 2, wherein the count value is set as an initial value, and a frame start signal is issued when the count value reaches a predetermined value. 7. The frame synchronization means, based on the synchronization position detected by a synchronization position detection unit and the synchronization interval obtained by the synchronization interval detection unit,
A state machine that transitions between a synchronization pull-in state for synchronizing the count value of the symbol counter with the transmission data and a synchronization holding state for maintaining a state in which the count value of the symbol counter is synchronized with the transmission data. 7. The digital satellite broadcast demodulator according to claim 6, wherein: 8. The synchronous position detecting section, when the state machine is in a synchronous holding state, compares the correlation value with a predetermined value only at a predetermined symbol position indicated by the symbol counter. The digital satellite broadcast demodulator according to claim 7, wherein: 9. The state machine transitions from the synchronization pull-in state to the synchronization holding state when the synchronization interval becomes one frame interval continuously for a predetermined number of times, and in the synchronization holding state, the correlation value continues for a predetermined number of times. 9. The digital satellite broadcast demodulator according to claim 8, wherein when the value is smaller than a predetermined value, the state shifts from the synchronization holding state to the synchronization pull-in state. 10. The digital satellite broadcast demodulator according to claim 9, wherein the count value of the symbol counter is set to an initial value when transitioning from the synchronization pull-in state to the synchronization holding state. 11. The digital satellite broadcast demodulator according to claim 7, wherein said synchronization detector changes a value of a comparison value with a correlation value between a synchronization pull-in state and a synchronization holding state. 12. The carrier synchronizing means, wherein: a carrier correction unit for correcting a carrier error by complexly multiplying transmission data consisting of orthogonal coordinate signals by a rotation correction signal; and correcting the carrier error by the carrier correction unit. A rotation correction signal generation unit that detects a phase rotation error amount from the transmitted transmission data and generates a rotation correction signal in accordance with the phase rotation error amount. The phase rotation error amount of the transmission data with the corrected error is calculated based on the modulation method of the synchronization word, the number of symbols is counted from the frame synchronization timing, at least the symbol position of the synchronization word is specified, and the phase rotation of the specified symbol is performed. Filter the error amount, and control the frequency and phase according to the filtered phase rotation error amount. 2. The digital satellite broadcast demodulator according to claim 1, wherein a controlled rotation correction signal is generated, and the generated rotation correction signal is output to the carrier correction unit. 13. The rotation correction signal generator counts the number of symbols from a frame synchronization timing, specifies a symbol position of a synchronization word, a burst signal, and / or a TMCC signal, and calculates a phase rotation error amount of the specified symbol. 13. The digital satellite broadcast demodulation device according to claim 12, wherein filtering is performed on. 14. After the carrier synchronization is established, the carrier synchronization means calculates the phase rotation error amount of each symbol according to the modulation scheme of each symbol specified based on the superframe synchronization timing. Performing filtering on the phase rotation error amount, generating a rotation correction signal whose frequency and phase are controlled according to the filtered phase rotation error amount, and outputting the generated rotation correction signal to the carrier correction unit. 13. The digital satellite broadcast demodulator according to claim 12, wherein: 15. The digital satellite broadcasting according to claim 14, wherein said carrier synchronization means performs filtering by changing a weight of the calculated phase rotation error amount according to a modulation scheme of each symbol. Demodulator. 16. The carrier synchronizing means performs a large weighting on a symbol modulated by BPSK, and modulates a symbol modulated by a modulation scheme other than BPSK from BPSK according to a modulation scheme. 16. The digital satellite broadcast demodulation device according to claim 15, wherein a weight of the carrier is calculated to calculate a carrier error. 17. A digital satellite broadcast demodulating method for demodulating a digital satellite broadcast signal, wherein a synchronization process of symbol timing of transmission data is performed, a synchronization word is detected from the transmission data synchronized in timing, and the transmission is performed. A digital satellite for detecting a frame synchronization timing of data, identifying at least a symbol position of the synchronization word based on the frame timing, detecting a reception phase of each symbol of the synchronization word, and performing a synchronization process of a carrier. Broadcast demodulation method. 18. A method of detecting difference data between symbols of transmission data and detecting a frame synchronization timing of the transmission data by correlating the difference data of the transmission data with the difference data of a synchronization word. The digital satellite broadcast demodulation method according to claim 17. 19. The digital satellite according to claim 18, wherein a correlation value between the difference data of the transmission data and the difference data of the synchronization word is filtered at a frame period to detect a frame synchronization timing of the transmission data. Broadcast demodulation method. 20. An IIR (Infinite Impulse Response) having a frame period delay buffer for a correlation value between differential data of transmission data and differential data of a synchronization word.
20. The digital satellite broadcast demodulation method according to claim 19, wherein e) filtering is performed to detect a frame synchronization timing of transmission data. 21. At the time of pulling in frame synchronization timing, the correlation value of all symbols in one frame is set to 1 using a memory used in data decoding processing after demodulation.
IIR filtering is performed with a delay of the frame period to detect the frame synchronization timing of the transmission data. After the synchronization of the frame synchronization timing is established, the delay register is used to correlate at least one symbol at the symbol position of the frame synchronization timing. 21. The digital satellite broadcast demodulation method according to claim 20, wherein the value is delayed by one frame period, IIR filtering is performed, and frame synchronization timing of transmission data is detected. 22. A synchronous position is detected by comparing the correlation value with a predetermined value, and a synchronous interval is detected by comparing an interval between the synchronous positions with one frame interval. The number of symbols of the transmission data is counted by using a repeated symbol counter. After the synchronization interval becomes one frame interval continuously for a predetermined number of times, the count value becomes an initial value, and the count value becomes 19. The digital satellite broadcast demodulation method according to claim 18, wherein a frame start signal is issued when the value reaches a predetermined value. 23. A synchronization pull-in state for synchronizing the count value of the symbol counter with the transmission data and a state in which the count value of the symbol counter is synchronized with the transmission data based on the synchronization position and the synchronization interval. 23. The digital satellite broadcast demodulation method according to claim 22, wherein the control is performed using a state machine that transits between a synchronization holding state and a synchronization holding state. 24. The method according to claim 23, wherein when the state machine is in a synchronization holding state, the correlation value is compared with a predetermined value only at a predetermined symbol position indicated by the symbol counter. Digital satellite broadcast demodulation method as described. 25. The state machine transitions from the synchronization pull-in state to the synchronization holding state when the synchronization interval becomes one frame interval continuously for a predetermined number of times, and in the synchronization holding state, the correlation value continuously changes for a predetermined number of times. 25. The digital satellite broadcast demodulation method according to claim 24, wherein when the value is smaller than a predetermined value, a transition is made from the synchronization holding state to the synchronization pull-in state. 26. The digital satellite broadcast demodulation method according to claim 25, wherein a count value of said symbol counter is set to an initial value when transitioning from said synchronization pull-in state to said synchronization holding state. 27. The digital satellite broadcast demodulation method according to claim 23, wherein the value of the comparison value with the correlation value is changed between the synchronization pull-in state and the synchronization holding state. 28. A carrier wave synchronization process comprising correcting a carrier error by complexly multiplying a transmission data consisting of rectangular coordinate signals by a rotation correction signal, and calculating a phase rotation error amount from the transmission data in which the carrier error is corrected. , A rotation correction signal corresponding to the phase rotation error amount is generated, the phase rotation error amount of the transmission data with the carrier error corrected is calculated based on the synchronization word modulation method, and the number of symbols is calculated from the frame synchronization timing. Count and specify at least the symbol position of the synchronization word, filter the phase rotation error amount of the specified symbol, and generate a rotation correction signal whose frequency and phase are controlled according to the filtered phase rotation error amount. 18. The digital satellite broadcast demodulation method according to claim 17, wherein the method is performed by generating. 29. Counting the number of symbols from a frame synchronization timing, specifying a symbol position of a synchronization word, a burst signal and / or a TMCC signal, and performing filtering on a phase rotation error amount of the specified symbol. 29. The digital satellite broadcast demodulation method according to claim 28. 30. After the synchronization of carrier wave synchronization is established, a phase rotation error amount of each symbol is calculated in accordance with a modulation scheme of each symbol specified based on a superframe synchronization timing. 29. The digital satellite broadcast demodulation method according to claim 28, further comprising: performing a filtering to generate a rotation correction signal whose frequency and phase are controlled according to the filtered phase rotation error amount. 31. The digital satellite broadcast demodulation method according to claim 30, wherein the calculated phase rotation error amount is subjected to filtering by changing a weight according to a modulation scheme of each symbol. 32. A large weight is given to a symbol that is BPSK modulated, and a smaller weight is given to a symbol that is modulated by a modulation scheme other than BPSK in accordance with the modulation scheme. The digital satellite broadcast demodulation method according to claim 31, wherein a carrier error is calculated.