JP2002111768A - Device and method for demodulating digital satellite broadcast - Google Patents

Abstract

PROBLEM TO BE SOLVED: To securely synchronize a carrier at high speed even in environment where a frequency deviation between the transmission frequency of a transmission signal and that of the signal of a local oscillator is large such as low C/N environment. SOLUTION: In a BS digital broadcast demodulating device, the symbol timing of transmission data on digital satellite broadcast is synchronized and a synchronizing word included in transmission data on the digital satellite broadcast is detected. Thus, frame timing is synchronized. The received phase of the synchronizing word is detected based on frame synchronous timing and the carrier is synchronized. In carrier synchronism, the frequency synchronism and the phase synchronism of the carrier are independently performed. The phase of the carrier is synchronized on transmission data after the frequency is synchronized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital satellite broadcast demodulator for demodulating digital satellite broadcasts and a digital satellite broadcast demodulation method.

[0002]

2. Description of the Related Art FIG. 21 is a block diagram showing a general transmission model when digital quadrature modulation is performed to transmit digital data.

The transmitting system Tx includes a data generator 11, a serial / parallel (S / P) converter 12, and a local oscillator 1
3, a -90 degree phase shifter 14, a first multiplier 15, a second multiplier 16, an adder 17, and a waveform shaping filter 1
8 is provided.

The data generator 11 of the transmission system Tx generates digital data obtained by serializing I signal data and Q signal data. The generated digital data is supplied to a serial / parallel (S / P) converter 12.

The S / P converter 12 performs level conversion of the input digital data from (0, 1) data to (1, -1) data, and performs serial / parallel conversion together therewith. , I signal data to a first multiplier 15 and the Q signal data to a second multiplier 16.

The local oscillator 13 generates a carrier wave which is a cosine wave having a frequency fc and an initial phase th. The generated carrier is supplied to the −90 degree phase shifter 14 and the first multiplier 15.

[0007] The -90 degree phase shifter 14 delays the phase of the carrier wave, which is a cos wave, by 90 degrees to generate a -sin wave. The generated −sine wave is supplied to the second multiplier 16.

The first multiplier 15 outputs the I signal data and co
The signal is multiplied by the s-wave and supplied to the addition circuit 17. The second multiplier 16 multiplies the Q signal data by the −sine wave and supplies the result to the addition circuit 17. The adder circuit 17 outputs a cosine wave multiplied by the I signal data and a sin wave multiplied by the Q signal data.
Add the waves. As a result of the addition, a quadrature modulated signal obtained by digital quadrature modulation of the carrier having the frequency fc is generated.

The quadrature-modulated signal is subjected to waveform shaping and amplification by a waveform shaping filter 18 so that the transmission path (C
channel).

The transmission system (Channel) includes an adder 19 for adding noise to a transmission signal. The transmission signal transmitted from the transmission system Tx is received by the reception system Rx with noise added by the transmission path.

The receiving system Rx includes a first multiplier 21 and a second multiplier 21.
, A local oscillator 23, and a −90-degree phase shifter 2
4, a first low-pass filter 25, a second low-pass filter 26, and a first analog / digital (A / D)
A converter 27, a second analog / digital (A / D) converter 28, a carrier correction unit 29, a first waveform shaping filter 30, a second waveform shaping filter 31, and a carrier synchronization unit 32 , A timing synchronizer 33, a parallel / serial (P / S) converter 34, and a slicer 35.

The received signal is input to a first multiplier 21 and a second multiplier 22.

The local oscillator 23 generates a carrier wave which is a cos wave having a frequency fc 'and an initial phase th'. Frequency f
c 'and the initial phase th' do not generally match the carrier on the transmitting side and have different frequencies and phases. The generated carrier is supplied to the -90 degree phase shifter 24 and the first multiplier 21.

The 90-degree phase shifter 24 delays the phase of the carrier wave, which is a cos wave, by 90 degrees to generate a -sin wave. The generated −sine wave is supplied to the second multiplier 22.

The first multiplier 21 multiplies the received signal by the cosine wave and quadrature demodulates the I signal. Second multiplier 22
Multiplies the received signal by the −sine wave and quadrature demodulates the Q signal. From the demodulated I signal, the high-frequency component is removed by a first low-pass filter 25 and the first A / D converter 2
7 is supplied. The demodulated Q signal is supplied to a second A / D converter 28 after a high-frequency component is removed by a second low-pass filter 26.

The first A / D converter 27 digitizes the I signal. Further, the second A / D converter 28 digitizes the Q signal. The first A / D converter 27 and the second A / D converter 28 use the sampling clock CLK output from the timing synchronization unit 33 to output the I signal and the Q signal.
Sample the signal. At this time, the sampling frequency is controlled by the timing synchronization section 33 so that the frequency and the phase are synchronized with the transmission symbol clock on the transmission side. The digitized I signal data and Q signal data are supplied to the carrier correction unit 29, respectively.

The carrier correction unit 29 performs a complex multiplication of the rotational phase correction signals (RI, RQ) output from the carrier synchronization unit 33 on the I signal data and the Q signal data. The I signal data and the Q signal data are converted to the rotational phase correction signals (RI, R
Q) is complex-multiplied to obtain the frequency fc ′ and phase th ′ of the carrier generated by the local oscillator 23 on the receiving side and the frequency fc and phase th of the carrier of the received signal.
Is corrected. The phase-corrected I signal data is supplied to the P / S converter 34 after the waveform is shaped by the first waveform shaping filter 30. The phase-corrected Q signal data is supplied to a P / S converter 34 after being subjected to waveform shaping by a second waveform shaping filter 31.

The carrier synchronizer 32 calculates a rotation phase correction signal (RI, RQ) which is a signal having a frequency and a phase corresponding to the carrier frequency error and the phase error of the received data. The carrier frequency error and the phase error of the received data are caused by the frequency shift and the phase shift of the carrier of the local oscillator 23. The calculated rotational phase correction signal (RI,
RQ) is supplied to the carrier correction unit 29.

The timing synchronization section 33 detects a clock error of the received data and generates a sampling clock such that the clock error becomes zero, that is, a sampling clock synchronized with the symbol clock of the transmission symbol on the transmission side. The generated sampling clock is the first A
/ D converter 27 and a second A / D converter 28.

The P / S converter 34 selects received data in the order of I signal data and Q signal data, and converts the data into serial data. The generated serial data is stored in slicer 3
5 is supplied.

The slicer 35 outputs 0 when the input data is larger than a predetermined value, and outputs 1 when the input data is smaller than a predetermined value.

Then, the transmission data is reproduced from the slicer 35.

In such digital data transmission,
On the receiving side, the demodulation process is performed by reproducing the transmission symbol clock generated on the transmitting side. The reproduction of the transmission symbol clock is called timing reproduction. On the receiving side, a correct demodulation result can be obtained by correcting the symbol clock of the received signal by some means instead of reproducing the transmission symbol clock. A process of obtaining a correct demodulation result by correcting a transmission symbol, including performing a timing reproduction and performing a demodulation process, is called timing synchronization.

On the receiving side, the coordinate system defining the transmission symbol space generated on the transmitting side is reproduced to perform demodulation processing. The reproduction of the coordinate system in the transmission symbol space is called carrier wave reproduction. On the receiving side, instead of reproducing the coordinate system that defines the transmission symbol space,
Correcting the coordinate system that defines the symbol space of the received signal by some means makes it possible to obtain a correct demodulation result. Obtaining a correct demodulation result by correcting the coordinate system defining the transmission symbol space, including reproducing the coordinate system defining the transmission symbol space and performing demodulation processing, is referred to as carrier synchronization.

[0025]

By the way, for example, CS
In a conventional digital transmission system such as digital broadcasting, when the C / N is relatively good, or the frequency deviation between the transmission frequency of the transmission signal and the frequency of the transmission signal of the local oscillator is small, and carrier wave synchronization processing is performed, By performing the synchronization process on the carrier wave phase, a correct demodulation result could be obtained. In other words, the carrier synchronization processing could be performed by detecting the phase error between the carrier signal of the transmission signal and the transmission signal of the local oscillator, and correcting the phase error.

However, for example, in a transmission system such as a BS digital broadcast where the C / N is small and the frequency deviation between the transmission frequency of the transmission signal and the frequency of the signal transmitted from the local oscillator is large, as in the prior art. Even if the carrier wave synchronization process is performed by correcting the phase error, synchronization cannot be achieved, or the time required to establish synchronization becomes extremely long.

The present invention provides a digital satellite for reliably and quickly detecting carrier synchronization even in an environment in which the frequency difference between the transmission frequency of a transmission signal and the frequency of a transmission signal of a local oscillator is large, such as in a low C / N environment. An object of the present invention is to provide a broadcast demodulation device and a digital satellite broadcast demodulation method.

[0028]

SUMMARY OF THE INVENTION A digital satellite broadcast demodulator according to the present invention includes a timing synchronizing means for synchronizing a symbol timing of transmission data, and detecting a synchronization word from the timing-synchronized transmission data. A frame synchronization means for detecting a frame synchronization timing of transmission data, at least a symbol position of the synchronization word is specified based on the frame timing, a carrier frequency error of each symbol of the synchronization word is detected, Carrier frequency synchronization means for performing, and a carrier phase synchronization means for identifying at least the symbol position of the synchronization word based on frame timing, detecting a carrier phase error of each symbol of the synchronization word, and performing a carrier phase synchronization process. The carrier phase synchronizing means includes a carrier frequency synchronizing means. Provided for the transmission data after the frequency synchronization of the carrier it is, to perform the phase synchronization of the carrier wave by.

In the digital satellite broadcast demodulator according to the present invention, synchronization processing of the symbol timing of the transmission data is performed, the frame synchronization timing of the transmission data is detected, and at least the symbol position of the synchronization word is specified based on the frame synchronization timing. Detect the carrier frequency error of each symbol of this synchronization word, perform frequency synchronization processing of the carrier, identify at least the symbol position of the synchronization word based on the frame timing, detect the carrier phase error of each symbol of this synchronization word, Carrier phase synchronization is performed.

That is, in the digital satellite broadcast demodulator according to the present invention, the carrier synchronization process is performed after the frame synchronization process is performed, and the carrier synchronization is performed on the transmission data after the frequency synchronization of the carrier is performed. Thus, the phase of the carrier is synchronized.

The digital satellite broadcast demodulation method according to the present invention performs synchronization processing of the symbol timing of transmission data, detects a synchronization word from the transmission data synchronized in timing, and detects the frame synchronization timing of the transmission data. Identifying at least the symbol position of the synchronization word based on the frame timing, detecting a carrier frequency error of each symbol of the synchronization word, performing frequency synchronization processing of the carrier, and transmitting data after the frequency synchronization processing of the carrier is performed. On the other hand, at least the symbol position of the synchronization word is specified based on the frame timing, the carrier phase error of each symbol of the synchronization word is detected, and the phase synchronization of the carrier is performed.

In the digital satellite broadcast demodulation method according to the present invention, the symbol timing of the transmission data is synchronized, the frame synchronization timing of the transmission data is detected, and at least the symbol position of the synchronization word is specified based on the frame synchronization timing. Detect the carrier frequency error of each symbol of this synchronization word, perform frequency synchronization processing of the carrier, identify at least the symbol position of the synchronization word based on the frame timing, detect the carrier phase error of each symbol of this synchronization word, Carrier phase synchronization is performed.

That is, in the digital satellite broadcast demodulation method according to the present invention, the carrier synchronization process is performed after the frame synchronization process is performed. Further, in the carrier synchronization, the transmission data after the frequency synchronization of the carrier is performed. Thus, the phase of the carrier is synchronized.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a BS according to an embodiment of the present invention will be described.
A digital broadcast receiving device will be described.

First Embodiment (Overall Configuration) FIG. 1 is a block diagram of a BS digital broadcast receiving apparatus, and the BS digital broadcast receiving apparatus will be described.

The receiving apparatus 100 includes a demodulation section 101 and a first
A demultiplexer 102, an inner code decoding unit 103,
The second demultiplexer 104 and the deinterleaver 10
5, the main signal inverse energy spreading section 106, the frame reconstructing section 107, the main signal RS decoding section 108, the TMCC
It comprises an inverse energy spreading section 109, a third demultiplexer 110, a TMCCRS decoding section 111, and a TMCC control section 112.

The demodulation unit 101 receives, for example, an RF signal received by a parabolic antenna or the like. The demodulation unit 101 multiplies the RF signal by the carrier signal to demodulate the quadrature modulated I and Q signals. The demodulation unit 101 also performs frequency conversion, carrier wave synchronization, timing synchronization, and frame synchronization processing. The demodulation unit 101
Is a TAB signal (synchronization word) modulated by BPSK
To detect the superframe and the start position of the frame. The demodulated I signal data and Q signal data are sent to the first demultiplexer 102.

The first demultiplexer 102 counts symbols from the frame start position detected by the demodulation unit 101, and outputs a burst signal at a predetermined symbol position.
Main signal data and TMCC data (including TAB signal)
Separate from The burst signal is read and discarded as it is. The main signal data and the TMCC data are sent to inner code decoding section 103.

The inner code decoder 104 performs depuncturing and Viterbi decoding according to the modulation scheme and inner code rate of each symbol. The inner code decoded data is sent to the second demultiplexer 104.

The second demultiplexer 104 separates the main signal data from the TMCC data (including the TAB signal). The separated main signal data is supplied to the deinterleaver 1
05. Separated TMCC data (TAB
Signal), the TMCC inverse energy diffusion processor 10
6 is sent.

The deinterleaver 105 deinterleaves the main signal data according to a rule reverse to the interleaving process performed on the transmission side. The deinterleaved main signal is sent to main signal inverse energy spreading section 106.

The main signal inverse energy spreading section 106
The next sequence pseudo-random sequence (PRBS) is added one bit at a time to the main signal data, and the inverse process to the energy spreading process performed on the transmission side is performed. Note that a pseudo random code sequence (PRBS) is initialized at the beginning of a superframe. Also, although the energy spreading process is not performed on the first byte of each slot, the PRBS continues to be generated during this time. The main signal data subjected to inverse energy spreading is sent to frame reconstructing section 107.

The frame reconstructing unit 107 reconstructs the data structure into a frame structure corresponding to the data frame on the transmission side, such as a process of adding a synchronization word (0x47) of the transport packet (TSP) deleted during transmission. I do. The reconstructed main signal data is sent to main signal RS decoding section 108.

The main signal RS decoding section 108 converts the RS (204, 188) into transmission packet units each composed of 204 bytes.
, And outputs the TSP.

TMCC inverse energy diffusion processing section 109
Is the TMCC data for one superframe and TAB
After accumulating the signal in the buffer, the ninth-order pseudo-random sequence (PRBS) is added one bit at a time to the TMCC data and the TAB signal, and inverse processing is performed on the energy spreading processing performed on the transmission side. This pseudo random code sequence (PRBS) is initialized at the beginning of a superframe. Further, energy diffusion is not performed on the TAB signal, but the generation of the PRBS continues. The energy-spread TMCC data and TAB signal are
To the demultiplexer 110.

The third demultiplexer 110 has a TMC
The C data and the TAB signal are separated. TAB isolated
The signal is discarded. The separated TMCC data is sent to TMCCRS decoding section 111.

The TMCCRS decoding section 111 converts the TMCC data consisting of 64 bytes into the RS (64, 48)
It performs decryption and outputs TMCC information. The RS-decoded TMCC information is transmitted to the TMCC control unit 112.

The TMCC control unit 112 extracts TMCC data necessary for transmission path decoding from the TMCC information, obtains TMCC information corresponding to each transport stream (TS), and transmits information necessary for decoding to each functional block. To deliver.

The receiving apparatus 100 having the above-described configuration receives a BS digital broadcast and demodulates a transport stream conforming to the MPEG-2 system.

(Configuration of Demodulation Unit) FIG. 2 shows the configuration of the demodulation unit 101 of the BS digital receiving apparatus 100, and the demodulation unit 101 will be further described.

The demodulation unit 101 includes a first multiplier 121,
Second multiplier 122, local oscillator 123, -90 degree phase shifter 124, first low-pass filter 125, second low-pass filter 126, and first analog / digital (A / D) conversion 127, a second analog / digital (A / D) converter 128, and a first complex multiplier 12
9, a frequency synchronization unit 130, and a second complex multiplier 131
, A phase synchronization unit 132, a timing synchronization unit 133,
A frame synchronization unit 134, a third multiplier 135, and a fourth
136, a first waveform shaping filter 137,
And a second waveform shaping filter 138.

For example, an RF signal received by a parabolic antenna or the like is input to a first multiplier 121 and a second multiplier 122.

The local oscillator 123 generates a carrier wave which is a cos wave having a frequency fc 'and an initial phase th'. The frequency fc 'and the initial phase th' do not coincide with the carrier on the transmitting side, and have different frequencies. The generated carrier is -90
The signal is supplied to the phase shifter 124 and the first multiplier 121.

The -90 degree phase shifter 124 delays the phase of the carrier wave, which is a cos wave, by 90 degrees to generate a -sine wave.
The generated −sine wave is supplied to the second multiplier 122.

The first multiplier 121 calculates the cos
The I signal is quadrature-demodulated by multiplying the signal by a wave. Second multiplier 1
Reference numeral 22 multiplies the received signal by the −sin wave and quadrature-demodulates the Q signal. The demodulated I signal is supplied to a first A / D converter 127 after a high-frequency component is removed by a first low-pass filter 125. The demodulated Q signal is
The high-frequency component is removed by the second low-pass filter 126 and supplied to the second A / D converter 128.

The first A / D converter 127 digitizes the I signal. Further, the second A / D converter 128
Digitize the signal. The first A / D converter 127 and the second A / D converter 128 include a timing synchronization unit 133
I by the sampling clock CLK output from
The signal and the Q signal are sampled. At this time, the sampling frequency is controlled by the timing synchronization unit 133 so that the frequency and the phase are synchronized with the transmission symbol clock on the transmission side. Digitized I signal data and Q
The signal data is supplied to the first complex multiplier 129, respectively.

The first complex multiplier 129 is composed of the first and second
Is multiplied by complex multiplication of the transmission data (I, Q) output from the A / D converters 127 and 128 and the complex conjugate of the frequency error correction signal (I ₁ , Q ₁ ) output from the frequency synchronization unit 130. , And transmission data (I ′, Q ′). That is, the first complex multiplier 129 calculates (I ′, Q ′) = (I, Q) × (I ₁ , Q ₁ ) * = (I × I ₁ + Q × Q ₁ , Q × I ₁ −I × Q ₁ ). (I ₁ , Q ₁ ) * is
It is a conjugate complex number of (I ₁ , Q ₁ ).

The transmission data (I ′, Q ′) output from the first complex multiplier 129 is applied to the waveform shaping filter 13.
7 and the waveform shaping filter 138.

The frequency synchronization section 130 detects a carrier frequency error component included in the transmission data (I ', Q') output from the first complex multiplier 129 and subjected to waveform shaping. Then, a frequency error correction signal (I ₁ , Q ₁ ) having a frequency corresponding to the carrier frequency error component is generated.

The first complex multiplier 129 converts the complex conjugate of the frequency error correction signal (I ₁ , Q ₁ ) into the transmission data (I, Q).
By complex multiplication, the frequency error correction signal (I
The phase of the transmission data (I, Q) is rotated only by the phase component of ( ₁ , Q ₁ ). As a result, the first complex multiplier 123
The frequency error component included in the transmission data (I ', Q') output from the FB is fed back and corrected. Therefore, the frequency fc 'of the carrier generated by the local oscillator 123 on the receiving side and the frequency f
The frequency deviation occurring between c and c is corrected.

The frequency synchronization of the carrier performed by the frequency synchronization section 130 is performed in a state where the timing synchronization is performed by the timing synchronization section 133 and the frame synchronization is performed by the frame synchronization section 134. . The frequency synchronizing unit 130 has a frequency synchronizing characteristic of the carrier wave that can obtain a predetermined characteristic even with the reception C / N = 0 dB under the condition that the timing synchronization and the frame synchronization are established. It is assumed that

The second complex multiplier 131 transmits the transmission data (I ′, Q ′) whose carrier frequency error has been corrected by the first complex multiplier 129 and the phase error correction signal output from the phase synchronization section 131. The complex data is multiplied by the complex conjugate of (I ₂ , Q ₂ ) to output transmission data (I ″, Q ″). That is, the second complex multiplier 131 calculates (I ″, Q ″) = (I ′, Q ′) × (I ₂ , Q ₂ ) * = (I ′ × I ₂ + Q ′ × An operation such as Q ₂ , Q ′ × I ₂ −I ′ × Q ₂ ) is performed.

The phase synchronizer 132 has a function of the second complex multiplier 1
A carrier wave phase error component included in the transmission data (I ″, Q ″) output from 31 is detected. Then, a phase error correction signal (I ₂ , Q ₂ ) of a phase component corresponding to the carrier phase error component is generated.

The second complex multiplier 131 converts the complex conjugate of the phase error correction signal (I ₂ , Q ₂ ) into transmission data (I ′,
Q 'by complex multiplication on), only the phase component of the phase error correction signal (I _2, Q _2), the transmission data (I',
Q ′) is rotated in phase. As a result, the transmission data (I ″, Q ″) output from the second complex multiplier 125
Are fed back and corrected. Therefore, the phase shift occurring between the phase th 'of the carrier generated by the local oscillator 123 on the receiving side and the phase th of the carrier on the transmitting side is corrected. That is, the carrier phase error is corrected.

The frequency synchronization of the carrier performed by the phase synchronizing section 132 is synchronized with the timing synchronizing section 133, and the frame synchronizing section 1
This is performed in a state where the frame synchronization is achieved by 34 and the frequency synchronization of the carrier is achieved by the frequency synchronization unit 130. Then, under the condition that the timing synchronization, the frame synchronization and the frequency synchronization of the carrier are achieved, the carrier synchronizer 130 determines the phase of the carrier that can obtain a predetermined characteristic even for the reception C / N = 0 dB. Assume that they have synchronization characteristics.

The timing synchronizing section 133 is a circuit that performs a timing synchronizing process by controlling the sampling clock of the A / D converters 127 and 128. The timing synchronization unit 133 detects a clock error of the transmission data (I ″, Q ″) output from the second complex multiplier 131, and detects a sampling clock such that the clock error becomes zero, that is, a transmission clock on the transmission side. A sampling clock whose phase and frequency are synchronized with the symbol clock of the transmission symbol is generated. The timing synchronization unit 133 detects a clock error by using, for example, a zero crossing method. The generated clock is used as a sampling clock for the first A / D converter 127 and the second A / D converter 128.

The timing synchronizing section 133 outputs the transmission data (I ″, I ″) output from the second complex multiplier 131.
Even if Q ″) includes a carrier frequency error and a carrier phase error, it is assumed that it has a timing synchronization characteristic enough to obtain a predetermined characteristic even for reception C / N = 0 dB.

The frame synchronization section 134 is a circuit for performing a frame synchronization process for detecting the start position of a frame by detecting a TAB signal (synchronization word) in the transmission data (I ″, Q ″).

Here, in BS digital broadcasting, a data structure called a super frame is defined. As shown in FIG. 3, the superframe is composed of eight frames (frame # 0 to frame # 7).
Each frame is composed of a control signal section (TMCC signal and TAB signal (synchronization word)) and a main signal section (main signal and burst signal).

As shown in FIG. 4, the main signal section has 48 slots (slot # 0 to slot #) per frame.
47). This main signal section is
The main signal data of the symbol and the burst signal of 4 symbols are arranged alternately. The burst signal is a BPSK modulated signal.

The control signal section has a transmission and multiplexing configuration (TMCC) of 8 bytes per frame.
ation Control) signal and a 2-byte TAB signal (synchronization word) added before and after the signal.
The TMCC signal and the TAB signal are each subjected to BPSK modulation (r = １ ／), and in terms of the number of transmission symbols,
128 symbols for TMCC and 32 symbols for TAB signal
Become a symbol. Here, the value of the TAB signal attached to the stage preceding the TMCC is W1 (0x1B95). Also, the TA attached after the TMCC
The value of the B signal is W2 for the first frame # 0.
(0xA340), and the value is W3 (0x5CBF) for the second to eighth frames. W
2 and W3 have a bit-inverted relationship.

Therefore, by detecting the TAB signal (synchronization word), it is possible to synchronize the frames, and by distinguishing and detecting W2 and W3, it is possible to synchronize the superframe. .

The 2-byte TAB signal is actually convolutionally coded to be a 32-bit transmission symbol. Among them, the first 12 bits are affected by the last main signal data of the previous frame and the value is undefined, but the latter 20 bits are in a range that is not affected by the previous frame. Become. Therefore, the frame synchronization section 134 detects the convolutionally coded fixed values (w1 for W1, w2 / w3 for W2 / W3) as a synchronization signal.

The frame synchronizing section 134 performs this frame synchronizing process in a state where the timing is synchronized but the carrier synchronization (frequency synchronization and phase synchronization) is not established. Specifically, a difference operation between symbols is performed on transmission data synchronized with timing. Then, a correlation between the bit string subjected to the difference operation and the synchronization word (w1, w2 / w3) subjected to the difference operation is obtained. And
A symbol position having the highest correlation (or a symbol having a correlation value higher than a certain threshold) is detected, and the symbol position is set as a frame synchronization position. Note that the TAB signal W2
And W3 are in a bit-inverted relationship, so that when the difference operation between symbols is performed, the values become the same.

The frame synchronizing section 134 uses such a TA
The B signal is detected, and a frame start flag (FST flag) indicating a frame start position and a superframe start flag (SFST flag) indicating a start position of a superframe are set.
Flag). Also, the frame synchronization unit 134
Not only FST flag and SFST flag, but also SFS
By counting the number of symbols from the T flag, TA
TAB flag indicating the symbol position of B signal (synchronization word), TMC flag indicating the symbol position of TMCC
Flag, which is a flag indicating the symbol position of the main signal
An N flag and a BRST flag indicating the symbol position of the burst signal may also be generated and output. The frame start signal (FST) and the superframe start flag (S
FST) is supplied to the carrier synchronizer 134.

The frame synchronizer 134 also generates a 180-degree phase inversion signal. The phase synchronizer 132 that synchronizes the phase of the carrier is a carrier synchronization method that allows a phase uncertainty of 180 degrees (when the carrier synchronizes, the phase is 180
(There is a possibility that it may be rotated and synchronized). Therefore, the frame synchronization section 134 detects the bit inversion state of the synchronization word (TAB signal), and
Of the carrier phase error. If a 180 ° carrier phase error is detected, the 180 ° phase inverted signal is
It outputs as 1 and outputs a 180 ° phase inversion signal as +1 if no 180 ° carrier phase error is detected. This 180 degree phase inversion signal is supplied to the third multiplier 13
5 and the fourth multiplier 136.

If the phase synchronization section 132 can perform carrier wave synchronization without leaving the phase uncertainty of 180 degrees, 18
The 0-degree phase-inverted signal may always be set to +1 or the third multiplier 135, the fourth multiplier 136, and the 180-degree phase-inverted signal may be omitted. Also, the frame synchronization unit 1
Reference numeral 34 performs a frame synchronization operation in a state where the timing is synchronized by the timing synchronization unit 133. Then, under the condition that carrier wave synchronization (frequency synchronization and phase synchronization) is not established, the frame synchronization unit 134 sets a frame synchronization characteristic sufficient to obtain a predetermined characteristic even for reception C / N = 0 dB. Shall have.

The third multiplier 135 is a complex multiplier 131
Is multiplied by the 180-degree phase inverted signal supplied from the frame synchronization unit 134. If the 180-degree phase inverted signal is +1, the I signal data (I ") is Output as is. If the 180 degree phase inversion signal is -1, the sign of the I signal data (I ") is inverted and output.

The fourth multiplier 136 includes a complex multiplier 131
Is multiplied by the 180-degree phase inverted signal supplied from the frame synchronization unit 134. If the 180-degree phase inverted signal is +1, the Q signal data (Q ") becomes Output as is. If the 180 degree phase inversion signal is -1, the sign of the Q signal data (Q ") is inverted and output.

Then, the third multiplier 135 and the fourth multiplier 135
Of the transmission data (I ″,
Q ″) is supplied to the inner code decoding unit 103.

(Synchronous Operation Flow of Demodulator) FIG. 5 shows a synchronous operation flow of the demodulator, and the synchronous operation of the demodulator will be described.

First, when the system is reset (step S1), the process proceeds to a timing synchronization pull-in process (step S2).

In the timing synchronization pull-in process (step S2), the timing synchronization unit 133 detects the transmission data (I ″, Q ″) output from the second complex multiplier 131, and the A / D converter 127 , 128 are controlled synchronously. When the timing synchronization is established, a notification that the timing synchronization has been completed is issued, and the process proceeds to the next frame synchronization pull-in process (step S3).

At the time of the timing synchronization pull-in process (step S2), if the frame synchronization pull-in process, the carrier wave frequency synchronization, and the carrier wave phase synchronization pull-in process are also performed in parallel, the timing synchronization is completed. The notification does not need to be issued. However, if the timing synchronization is not established, the pull-in processing of the frame synchronization, the pull-in processing of the frequency synchronization of the carrier and the pull-in processing of the phase synchronization of the carrier cannot be performed, and therefore these pull-in operations may be stopped. If the operations of the frame synchronization pull-in process and the carrier wave synchronization pull-in process are stopped during the timing synchronization pull-in process, power consumption can be saved. After the timing synchronization is established, the state in which the timing synchronization is established is kept protected.

Subsequently, in the frame synchronization pull-in process (step S3), the frame synchronization unit 134 outputs the transmission data (I ″, I ″) output from the second complex multiplier 131.
Q ″), and the difference data between the symbols of the transmission data (I ″, Q ″) and the synchronization word (w1, w2 / w3)
The frame synchronization timing is detected by correlating with the differential data of the frame. When the frame synchronization timing is detected, a notification that the frame synchronization has been completed is issued, and the process proceeds to the next carrier frequency synchronization pull-in process (step S4).

In the frame synchronization pull-in process (step S3), when the process of pulling in the frequency synchronization of the carrier wave and the phase synchronization of the carrier wave is performed in parallel, the notification that the frame synchronization has been completed is not issued. Is also good. However, if the frame synchronization timing is not detected, the pull-in process of the frequency synchronization of the carrier and the phase synchronization of the carrier is difficult. Therefore, the pull-in operation of the frequency synchronization of the carrier and the phase synchronization of the carrier may be stopped.
In this frame synchronization pull-in process, if the operation of the pull-in process of the frequency synchronization of the carrier and the phase synchronization of the carrier is stopped, power consumption can be saved. After the frame synchronization has been established, the state in which the frame synchronization has been established continues to be protected.

Subsequently, in the process of pulling in the frequency synchronization of the carrier (step S4), the frequency synchronization unit 130
Of the transmission data (I ′,
Q ′), and detects a frequency error amount of a symbol (TMCC, TAB signal, burst signal symbol) specified based on the frame synchronization timing output from the frame synchronization unit 134, and corrects this frequency error amount. A frequency error correction signal (I ₁ , Q ₁ ) for the frequency is generated. The generated frequency error correction signal (I ₁ , Q ₁ )
Of the transmission data (I, Q)
, The frequency error of the carrier is corrected. When the frequency synchronization of the carrier is established, a notification that the frequency synchronization of the carrier has been completed is issued, and the process proceeds to the process of pulling in the phase synchronization of the next carrier (step S5).

In the process of pulling in the frequency synchronization of the carrier (step S4), if the process of pulling in the phase synchronization of the carrier is performed in parallel, it is not necessary to issue a notification that the frequency synchronization of the carrier has been completed. Good. The phase locking operation of the carrier may be stopped until the frequency synchronization of the carrier is established. If the operation of the pull-in processing of the phase synchronization of the carrier is stopped during the pull-in processing of the frequency synchronization of the carrier, power consumption can be saved. After the frequency synchronization of the carrier is established, the state in which the frequency synchronization of the carrier is established continues to be protected.

Subsequently, in the process of pulling in the phase synchronization of the carrier (step S5), the phase synchronization section 132 outputs the transmission data (I ″, I ″) output from the second complex multiplier 131.
Q "), and detects the phase error amount of a symbol (TMCC, TAB signal, burst signal symbol) specified based on the frame synchronization timing output from the frame synchronization unit 134, and corrects this phase error amount. A phase error correction signal (I ₂ , Q ₂ ) having a phase component is generated.
The generated phase error correction signal (I ₂ , Q ₂ )
Of the transmission data (I ′,
By performing complex multiplication with Q ′), the phase error of the carrier is corrected. Once carrier phase synchronization is established,
The state shifts to the state where the protection of the timing synchronization, the protection of the frame synchronization, the frequency synchronization of the carrier and the phase synchronization of the carrier are protected (step S6).

When the timing synchronization is lost during the above processing, the process proceeds to the timing synchronization pull-in processing (step S2), and the processing is continued from step 2. If the frame synchronization is lost, the process proceeds to the frame synchronization pull-in process (step S3), and the process is continued from step S3. If the frequency synchronization of the carrier is lost, the process proceeds to the process of pulling in the frequency synchronization of the carrier (step S4), and the process is continued from step S4. If the phase of the carrier is out of phase, the process proceeds to the step of pulling in the phase of the carrier (step S5), and the process is continued from step S5.

As described above, by performing the synchronization operation in the order of the timing synchronization, the frame synchronization, the carrier frequency synchronization, and the carrier phase synchronization, the demodulation unit 101 employs a plurality of modulation schemes and operates each modulation scheme. It is possible to reliably detect various synchronizations of digital satellite broadcasting that change in a simple manner with a simple configuration. In addition, synchronization can be reliably detected with a small circuit scale even in a poor reception environment.

(Carrier Wave Frequency Synchronizing Unit) Next, the carrier frequency synchronizing unit 130 will be described in more detail.

FIG. 6 is a block diagram of the frequency synchronization section 130.

As shown in FIG. 6, the frequency synchronization section 130 includes a timing control circuit 141, a frequency error detection circuit 142, a filter 143, and an NCO (Numerical Control).
rol oscillator 144).

The timing control circuit 141 receives a frame start flag (FST flag) from the frame synchronization circuit 134 shown in FIG. The timing control circuit 141 counts the number of symbols from the FST flag, thereby transmitting the BP in the BS digital broadcast such as TMCC data, TAB signal (synchronization word), and burst signal.
The symbol timing that is specified to be SK modulated is specified. The timing control circuit 141 generates a frequency synchronization information update flag specifying that the symbol is the position of the TMCC data, the TAB signal, and the burst signal, and supplies the frequency synchronization information update flag to the filter 143 and the NCO 144. This frequency synchronization information update flag includes the TMCC data, TA
This flag is valid (1) for each symbol except the first symbol of the B signal and the burst signal. This is because the frequency error detection circuit 142, which will be described later, performs a differential operation between the symbols, so that the first symbol is B
This is because the information is not information generated based on the PSK-modulated signal.

As shown in FIG. 7, the frequency error detecting circuit 142 includes a phase error detecting circuit 151 and a register 152.
And a subtractor 153.

The phase error detection circuit 151 detects a phase error component included in the transmission data (I ', Q') output from the first complex multiplier 129. Specifically, the phase error detection circuit 151 transmits the transmission data (I ′, Q ′)
Calculates the phase error amount Δθ ₁ indicating how much the phase is shifted from the signal point of the original transmission symbol of BPSK. The calculated phase error amount Δθ ₁ is supplied to the register 152 and the subtractor 153.

The register 152 stores the phase error detection circuit 15
1 the phase error Δθ detected ₁For one symbol
Delay by the amount of the clock. One symbol mark by register 152
Lock-delayed phase error amount Δθ₁To the subtractor 153
Is entered.

The subtractor 153 includes a phase error detection circuit 151
From the current phase error amount [Delta] [theta] ₁ that is output from the 1 symbol clock delayed phase error amount [Delta] [theta] ₁ is subtracted by the register 142, and calculates a frequency error amount Delta] f _1. Here, the subtraction circuit 153 performs simple subtraction, and outputs
It also has a MOD calculation function in an angle range of 0 °. BP
In the case of SK modulation, the range of -90 ° ≦ Δf ₁ ≦ 90 ° is the angle detection range. That is, in one symbol time, the phase rotation amount due to the frequency error is equal to or more than -90 ° and less than + 90 °. Therefore, the subtractor 153 performs the following MOD operation together with the simple subtraction. (Δθ ₁ −Δθ ₁ φ + 90 °) mod 180 ° −90 ° where Δθ ₁ φ is the output of the register 152.

The frequency error Δf ₁ detected by the frequency error detection circuit 131 as described above
Supplied to

The filter 143 is, for example, an IIR (Infini
It is composed of a loop filter such as a te Impulse Response filter and has the characteristics of an LPF (Low pass filter). The filter 143 receives the frequency error Δf ₁ from the frequency error detection circuit 142, averages the input frequency error Δf ₁ , and outputs the averaged frequency error Δf ₁ .

For example, as shown in FIG. 8, the filter 143 multiplies a frequency error Δf ₁ by a gain G and a frequency multiplier Δf ₁ by a coefficient K for determining a band. A second multiplier 155, a third multiplier 156 for multiplying the filter output by a coefficient (1-K),
An adder 157 that adds the output of the multiplier 155 and the output of the third multiplier 156, and a register 158 that delays the output of the adder 157. The filter 143 having such a configuration loop-filters the input frequency error amount Δf ₁ with the coefficient K and the gain G, and outputs the averaged frequency error amount Δf ₁ from the register 158.

Here, the register 158 holds the frequency error amount Δf ₁ averaged at that time. This register 158 stores the timing control circuit 141
Is updated as an enable signal, and the internal data is updated only when the frequency synchronization information update flag is valid (1). Therefore, the filter 143 includes TMCC, TAB,
Frequency error Δf ₁ obtained at the position of the burst symbol
, And retains the last filter output value in other symbol positions. That is, the filter 143 extracts only the frequency error Δf _{1 of the} symbol modulated by BPSK and performs intermittent filtering.

The frequency error Δf ₁ averaged from the filter 143 is input to the NCO 144. NCO1
44 generates and outputs a frequency error correction signal (I ₁ , Q ₁ ) based on the frequency error amount Δf ₁ .

As shown in FIG. 9, the NCO 144
, A second accumulator 162, and a rectangular coordinate conversion circuit 163.

The first accumulator 161 includes an adder 165
And a register 166. Adder 165
Is the frequency error Δf ₁ input from the filter 143
And the value stored in the register 166 are added. Register 166 updates the stored value with the addition result. The first accumulator 161 includes the adder 165 and the register 166.
, The frequency error amount Δf _{1 for} each symbol clock
Is cumulatively added. By cumulatively adding the frequency error amount Δf ₁ in this manner, the register 166 stores the frequency correction amount f _{1 at} that time. The first accumulator 161 supplies the frequency correction amount f ₁ at that time stored in the register 166 to the second accumulator 162.

The second accumulator 162 includes an adder 167
And a register 168. Adder 167
Calculates the addition of the frequency correction amount f ₁ input from the first accumulator 161 and the value stored in the register 168. Register 168 updates the stored value with the addition result. The second accumulator 162 includes the adder 167 and the register 1
68, the frequency correction amount f for each symbol clock
Performs cumulative addition of ₁ . By cumulatively adding the frequency correction amount f ₁ in this manner, the phase correction amount θ _{1 at} that time is stored in the register 168. The second accumulator 162 stores the value stored in the register 168,
The phase correction amount θ ₁ at that time is converted into a rectangular coordinate conversion circuit 1
63.

The rectangular coordinate conversion circuit 163 performs a process of converting the phase correction amount θ ₁ output as angle data into a rectangular coordinate signal. For example, the register 168 of the second accumulator 162 is configured to perform a modulo operation at Mod 360 °, and a rectangular coordinate signal is generated using a conversion table that converts data output from the register 168 into rectangular coordinate data. I do. This orthogonal coordinate conversion circuit 163 supplies the first complex multiplier 129 with a frequency error correction signal (I ₁ , Q ₁ ) obtained by converting the phase correction amount θ ₁ into a rectangular coordinate signal.

Here, the first accumulator 1 of the NCO 144
The register 166 (register storing the frequency correction amount f ₁ at that time) receives the frequency synchronization information update flag supplied from the timing control circuit 141 as an enable signal, and indicates that the BPSK flag is valid (1). Update internal data only when it is.

Therefore, updating of the oscillation frequency of the frequency error correction signal (I ₁ , Q ₁ ) output from the NCO 144
This is performed only at the TAB, TMCC, and burst positions, and the remaining oscillation frequency is held at other positions. That is, the NCO 144 applies the frequency error correction signal (I ₁ , Q ₁ ) only to the symbol modulated by BPSK.
Intermittent operation such as changing the oscillation frequency of

[0111] frequency synchronization unit 129 as described above, detects a frequency error amount Delta] f _1, averaging filter the frequency error amount Delta] f ₁ detected. Then, the averaged frequency error amount Δf ₁ is added twice to convert it to the phase correction amount θ ₁ at that time, and then the frequency error correction signal (I ₁ ,
Q ₁ ). By rotating the phase of the transmission data (I, Q) using the frequency error correction signal (I ₁ , Q ₁ ) obtained in this manner, the carrier frequency error included in the transmission data (I, Q) is obtained. Is corrected.
Further, by counting the number of symbols from a frame start flag (FST) obtained by performing frame synchronization, the position of a symbol that is always BPSK modulated, such as TMCC, TAB, or burst, is specified. The synchronization process of the carrier frequency is performed only at the symbol position where the symbol is present.

When the carrier frequency error is completely corrected, the frequency error Δf ₁ output from the first accumulator 161 becomes 0, and the phase correction amount output from the second accumulator 162 becomes zero. The amount θ ₁ continues to output a constant value.

(Phase Synchronizing Section of Carrier) Next, the phase synchronizing section 130 of the carrier will be described in more detail.

FIG. 10 is a block diagram of the phase synchronization section 132.

As shown in FIG. 10, the phase synchronization section 132 includes a timing control circuit 171 and a phase error detection circuit 1.
72, a filter 173, and an NCO 174.

A frame start flag (FST flag) is input to the timing control circuit 171 from the frame synchronization circuit 134 shown in FIG. The timing control circuit 171 counts the number of symbols from the FST flag, and thereby determines the symbol timing that is always BPSK-modulated in BS digital broadcasting such as TMCC data, TAB signal (synchronization word), and burst signal. To identify. The timing control circuit 171 generates a BPSK flag that is valid (1) when the symbol is a TMCC data, a TAB signal, or a burst signal, and supplies the BPSK flag to the filter 173 and the NCO 174.

Note that the timing synchronization circuit 171
It may be used in common with the timing synchronization circuit 141 of the frequency synchronization unit 130.

The phase error detection circuit 172 detects a phase error component included in the transmission data (I ″, Q ″) output from the second complex multiplier 131. Specifically, the phase error detection circuit 172 transmits the transmission data (I ″, Q ″)
Calculates the phase error amount Δθ ₂ indicating how much the phase is shifted from the signal point of the original transmission symbol of BPSK. The calculated phase error amount Δθ ₂ is supplied to the filter 173.

The filter 173 is, for example, an IIR (Infini
It is composed of a loop filter such as a te Impulse Response filter and has the characteristics of an LPF (Low pass filter). The configuration may be the same as the filter 143 of the frequency synchronization section 130 shown in FIG. However, the phase error amount Δθ
The value of the gain G by which ₂ is multiplied and the value of the coefficient K that determines the band are adaptively set, and the filter 143 of the frequency synchronization unit 130
And may be different. The filter 173 loop-filters the input phase error amount Δθ ₂ with a coefficient K and a gain G, and outputs an averaged phase error amount Δθ ₂ .

Here, in the register holding the averaged phase error amount Δθ ₂ at that time, the BPSK flag supplied from the timing control circuit 171 is input as an enable signal, and the BPSK flag is made valid (1). Update internal data only when for that reason,
The filter 173 operates only for the phase error amount Δθ ₂ obtained at the positions of the TMCC, TAB, and burst symbols, and holds the last filter output value at other symbol positions. That is, this filter 143 is
Only the phase error amount Δθ _{2 of the} symbol modulated by SK is extracted and intermittently filtered.

The NCO 174 receives the averaged phase error Δθ ₂ from the filter 173. NCO17
4 generates and outputs a phase error correction signal (I ₂ , Q ₂ ) based on the phase error amount Δθ ₂ .

The NCO 174 comprises a cumulative adder 181 and a rectangular coordinate conversion circuit 182, as shown in FIG.

The accumulator 181 comprises an adder 183 and a register 184. The adder 183 performs an addition operation on the phase error amount Δθ ₂ input from the filter 173 and the value stored in the register 184. Register 184
The stored value is updated with the addition result. The accumulator 181 is
The adder 183 and the register 184 perform cumulative addition of the phase error amount Δθ ₂ for each symbol clock. By cumulatively adding the phase error amount Δθ ₂ in this manner,
The register 184 stores the phase correction amount θ _{2 at} that time.
Will be stored. The accumulator 181 supplies the phase correction amount θ ₂ stored in the register 184 at that time to the orthogonal coordinate conversion circuit 182.

Here, register 184 of accumulator 181
(The register holding the phase correction amount θ ₂ at that time) is the BP supplied from the timing control circuit 171.
The SK flag is input as the enable signal EN, and the BP
Only when the SK flag is valid (1), the internal data is updated.

Therefore, the phase error correction signal (I ₂ , Q ₂ ) output from NCO 174 is updated by TAB, TMC
C, only at the burst position, at other positions,
The last phase correction amount is held. That is, this NCO
174 performs an intermittent operation such as changing the phase error correction signal (I ₂ , Q ₂ ) only for the symbol modulated by BPSK.

The BPS input to the register 184
The K flag is input by the register 185 with a delay of one timing. This is because the register 184 is updated using the phase error amount Δθ ₂ updated by the filter 173 at the previous stage.

The rectangular coordinate conversion circuit 182 performs a process of converting the phase correction amount θ ₂ output as angle data into a rectangular coordinate signal. For example, register 184 is Mod36
The remainder operation is performed at 0 °, and its register 184
A rectangular coordinate signal is generated using a conversion table for converting the data output from the data into rectangular coordinate data. The orthogonal coordinate conversion circuit 182 converts the phase correction amount θ ₂ into a rectangular coordinate signal and obtains a frequency error correction signal (I ₂ , Q ₂ ).
Is supplied to the second complex multiplier 131.

[0128] phase synchronization unit 132 as described above, detects a phase error amount [Delta] [theta] _2, averaging by filtering the phase error amount [Delta] [theta] ₂ was detected. Then, after accumulating the averaged phase error amount Δθ ₂ and converting it into a phase correction amount θ ₂ at that time, a frequency error correction signal (I ₂ , Q ₂ ) is generated. The frequency error correction signal (I ₂ , Q ₂ ) thus obtained
Accordingly, by phase rotation transmission data (I _1, Q _1), so that the carrier phase error contained in the transmission data (I _1, Q ₁₎ is corrected. When the carrier phase error is completely corrected, the phase error amount Δθ ₂ output from the filter 135 becomes 0, and the accumulator 16
The phase correction amount θ ₂ output from the output unit 4 continuously outputs a constant value.

As described above, the demodulation section 101 of the digital satellite broadcast receiving apparatus according to the first embodiment performs the synchronization processing of the symbol timing of the digital satellite broadcast transmission data. The frame synchronization is performed by detecting the synchronization word included in the frame synchronization.Then, the symbol position of the synchronization word is detected based on the frame synchronization timing, and the frequency synchronization of the carrier is performed. The symbol position of the synchronization word is detected based on the synchronization timing, and the phase synchronization of the carrier is performed.

Accordingly, the carrier synchronization processing can be performed with a very simple configuration, and at the same time, even in the case of digital satellite broadcasting in which the modulation scheme changes dynamically, QPSK can be performed.
BPSK-modulated symbols having a wide phase between signal points are detected and carrier synchronization processing is performed without using symbols having a narrow phase between signal points such as 8PSK or 8PSK, so that carrier synchronization processing can be performed with high accuracy. .

Further, of the carrier frequency error and the carrier phase error included in the transmission data (I, Q), only the carrier frequency error component is corrected by the first complex multiplier 129, whereby the carrier wave is corrected. Frequency synchronization is performed. Then, the second complex multiplier 13 corrects the carrier phase error with respect to the transmission data (I ', Q') which has been subjected to the carrier frequency synchronization processing and contains only the carrier wave phase error component.
1 performs the phase synchronization of the carrier.
As described above, by performing carrier phase synchronization after performing carrier frequency synchronization, the carrier phase error component has no effect on the frequency error correction signal, and the band of the phase rotation amount with respect to the transmission data can be narrowed. it can.

Therefore, in the demodulation unit 101 of the digital satellite broadcast receiving apparatus according to the first embodiment, the frequency shift between the transmission frequency of the transmission signal and the frequency of the transmission signal of the local oscillator in a low C / N environment is obtained. Even under a large environment, carrier synchronization can be detected reliably and at high speed.

After the frequency synchronization and the phase synchronization of the carrier are established, the superframe can be synchronized. Therefore, the T
MCC (Transmission and Multiplexing Configuration)
n Control) information is decoded. The TMCC information describes the modulation scheme of all symbols. Therefore,
By referring to the TMCC information, TAB, TMC
It is possible to specify not only the C and burst positions but also the modulation method of all symbols.

Therefore, after the frequency synchronization and the phase synchronization of the carrier are established, the synchronization process is not performed intermittently using only the TAB, TMCC, and burst positions, but the phase error amount of all the symbols is detected to detect the carrier. Frequency synchronization and phase synchronization processing may be performed.

Second Embodiment Next, a BS digital broadcast receiving apparatus according to a second embodiment of the present invention will be described.

The overall configuration (the configuration shown in FIG. 1) of the BS digital receiving apparatus according to the second embodiment and the third to fifth embodiments which will be described later is the same as that of the first embodiment. And only the configuration of the demodulation unit is different. Therefore, in the following description of the embodiments, only the demodulation unit will be described in detail.

In describing the second embodiment, the same components as those in the above-described first embodiment are denoted by the same reference numerals in the drawings, and detailed description thereof will be omitted. .

FIG. 12 is a block diagram of a second embodiment of the present invention.
2 shows a configuration of a demodulation unit applied to the S digital reception device.

The demodulation unit 201 according to the second embodiment includes the first
Multiplier 121, a second multiplier 122, a local oscillator 123, a 90-degree phase shifter 124, a first low-pass filter 125, a second low-pass filter 126,
Analog / digital (A / D) converter 127 and the second
Analog / digital (A / D) converter 128, complex multiplier 129, first waveform shaping filter 137, second waveform shaping filter 138, and angle conversion circuit 202
, A frequency synchronization unit 204, a polar coordinate conversion circuit 210,
Second subtractor 205, phase synchronization section 206, timing synchronization section 207, frame synchronization section 208, adder 2
09.

This demodulation section 201 is composed of first and second A /
The configuration up to the D converters 127 and 128 is the same as that of the first embodiment.

The complex multiplier 129 includes the first and second A /
The transmission data (I, Q) output from the D converters 127 and 128 and the complex conjugate of the frequency error correction signal (I ₁ , Q ₁ ) output from the polar coordinate conversion unit 210 are subjected to complex multiplication to obtain transmission data. (I ', Q') is output. That is,
The first complex multiplier 129 calculates (I ′, Q ′) = (I, Q) × (I ₁ , Q ₁ ) * = (I × I ₁ + Q × Q ₁ , Q × I ₁₋ I × Q ₁ ). (I ₁ , Q ₁ ) * is
It is a conjugate complex number of (I ₁ , Q ₁ ).

Transmission data (I ′, Q ′) output from first complex multiplier 129 is applied to waveform shaping filter 13.
7 and the waveform shaping filter 138.

The angle conversion circuit 202 converts transmission data (I ', Q') consisting of rectangular coordinate signals output from the first and second waveform shaping filters 137, 138 into an angle signal θ '.
Convert to For example, the angle conversion circuit 202 may generate an angle signal by performing a numerical operation from the I and Q signals, or may generate an angle signal using a conversion table that converts a rectangular coordinate signal into an angle signal. You may. The angle conversion circuit 202 supplies the transmission data θ ′ converted into the angle signal to the second subtractor 205 and the frequency synchronization unit 204.

The frequency synchronizing section 204 includes the angle conversion circuit 20
2 detects a carrier frequency error component included in the transmission data θ ′ output from the second data. Then, to generate a frequency error correction signal theta ₁ consisting of frequency and angular signal corresponding to the carrier frequency error component.

The frequency synchronization section 204 is different from the frequency synchronization section 130 of the first embodiment in that the phase error Δθ ₁ is calculated not from the quadrature signal but from the angle signal, and
The difference is that the frequency error correction signal to be output is output not as an orthogonal signal but as an angle signal, but the realized functions are the same.

The frequency error correction signal θ ₁ output as the angle signal is supplied to the polar coordinate conversion circuit 210.

The polar coordinate conversion circuit 210 converts the frequency error correction signal θ ₁ as an angle signal into a frequency error correction signal (I ₁ , Q ₁ ) of a rectangular coordinate signal. The frequency error correction signal (I ₁ , Q ₁ ), which is a rectangular coordinate signal, is output from the complex converter 1
29.

[0148] complex multiplier 129, a frequency error correction signal (I _1, Q ₁₎ the complex conjugate transmission data (I, Q) of the by complex multiplication, the frequency error correction signal (I _1,
The phase of the transmission data (I, Q) is rotated by the phase component of Q ₁ ). As a result, the frequency error component included in the transmission data (I ′, Q ′) output from the complex multiplier 123 is fed back and corrected. Therefore, a frequency shift occurring between the frequency fc ′ of the carrier generated by the local oscillator 123 on the receiving side and the frequency fc of the carrier on the transmitting side is corrected.

The second subtractor 205 subtracts the transmission data θ ′ in which the carrier frequency error has been corrected and the phase error correction signal θ ₂ output from the phase synchronization section 131, and outputs the transmission data θ ″. That is, the second subtractor 205
The following calculation is performed. θ ″ = θ′−θ _{2 The} phase synchronization unit 206 detects a carrier phase error component included in the transmission data θ ″ output from the second subtractor 205. Then, to produce a phase error correction signal theta ₂ consisting angle signal of the phase component corresponding to the carrier phase error component.

The phase synchronization section 206 is different from the phase synchronization section 132 of the first embodiment in that the phase error Δθ ₂ is calculated not from the quadrature signal but from the angle signal, and the phase error correction signal to be output. Is output as an angle signal instead of a quadrature signal, but the realized functions are the same.

The second subtractor 205 subtracts the phase error correction signal θ ₂ from the transmission data θ ′ to rotate the transmission data θ ′ by the phase component of the phase error correction signal θ ₂ . As a result, the phase error component contained in the transmission data θ ″ output from the second subtractor 205 is fed back and corrected. Therefore, the phase of the carrier generated by the local oscillator 123 on the receiving side is corrected. The phase shift occurring between th 'and the phase th of the carrier on the transmitting side is corrected, that is, the carrier phase error is corrected.

The timing synchronizing unit 207 is a circuit that performs a timing synchronizing process by controlling the sampling clock of the A / D converters 127 and 128. This timing synchronization unit 207 is realized, although different from the timing synchronization unit 133 of the first embodiment, in that a clock error is detected from transmission data of an angle signal instead of transmission data of an orthogonal signal. The functions are the same.

The frame synchronizing section 208 performs this frame synchronizing process in a state where the timing is synchronized but the carrier wave (frequency synchronization and phase synchronization) is not. This frame synchronization circuit 208 is different from the frame synchronization circuit 134 of the first embodiment in that a synchronization word is detected not from orthogonal signal transmission data but from angle signal transmission data, but is realized. The functions are the same. Note that the frame synchronization unit 208 also generates a 180-degree phase inversion signal including an angle signal. When a 180 ° carrier phase error is detected, the phase synchronizer 206 that performs carrier phase synchronization converts the 180 ° phase inversion signal to −
If the 180 ° carrier wave phase error is not detected, the 180 ° phase inverted signal is output as 0 °. This 180 degree phase inversion signal is added to the adder 20.
9.

The adder 209 adds the transmission data θ ″ output from the second subtractor 205 and the 180 ° phase-inverted signal supplied from the frame synchronization unit 208.
If the 0-degree phase inversion signal is 0, the transmission data θ ″ is output as it is. If the 180-degree phase inversion signal is −180, the transmission data θ ″ is output after being rotated by 180 °.

The output transmission data θ ″ is supplied to the inner code decoder 103.

As described above, in the demodulation section 201 of the BS digital receiving apparatus according to the second embodiment of the present invention, a circuit for performing frequency synchronization of a carrier and a circuit for performing phase synchronization of a carrier are connected in series. Then, demodulation is performed. That is,
After performing the frequency synchronization processing of the carrier, the phase synchronization processing of the carrier is independently performed. Therefore, the correction component of the phase error of the carrier does not affect the correction amount of the frequency error of the carrier.

At the same time, since the carrier wave synchronization processing is performed using the angle signal, the circuit scale can be reduced.
Note that, for example, the inner code decoding unit 1 subsequent to the demodulation unit 201
04 may be converted back to a polar coordinate signal in order to obtain consistency with the inner code decoding unit 10.
The fourth branch metric may be calculated using the angle information.

Third Embodiment A BS digital broadcast receiving apparatus according to a third embodiment of the present invention will now be described.

Note that the third embodiment is different from the second embodiment only in the internal configuration of the frequency synchronization section of the demodulation section 201. Therefore, in the third embodiment, only the frequency synchronization unit will be described in detail.

As shown in FIG. 13, the frequency synchronizing section 220 includes a timing control circuit 221, a frequency error detecting circuit 222, a filter 223, an NCO 224, and a level detecting circuit 225.

The timing control circuit 221 receives a frame start flag (FST flag) from the frame synchronization circuit 208. The timing control circuit 221 counts the number of symbols from the FST flag, thereby obtaining the TMCC data, the TAB signal (synchronization word),
A symbol timing that is specified to be BPSK-modulated in a BS digital broadcast such as a burst signal is specified. The timing control circuit 221 determines that the symbol is TM
A frequency synchronization information update flag for specifying CC data, a TAB signal, and a burst signal is generated.
23 and the NCO 224. Further, the timing control circuit 221 determines whether or not the frequency synchronization of the carrier is established based on the comparison result from the level detection circuit 225, and is effective when it is determined that the frequency synchronization is established (1).
A synchronization establishment flag is generated. The timing control circuit 221 supplies a synchronization establishment flag to the NCO 224.
The frequency synchronization information update flag is a flag that is valid (1) for each symbol except for the first symbol of the TMCC data, the TAB signal, and the burst signal, as in the first embodiment.

The transmission data θ 'output from the angle conversion circuit 202 is input to the frequency error detection circuit 222.
The frequency error detection circuit 222 detects a frequency error component Δf ₁ included in the transmission data θ ′. The detected frequency error Δf ₁ is supplied to the filter 223.

The filter 223 is composed of a loop filter such as an IIR filter, and has an LPF (Low pass filter).
r). Its configuration is the same as that of the filter 143 shown in FIG. The frequency error amount Δf ₁ averaged by the filter 223 is supplied to the NCO 224 and the level detection circuit 225.

The level detection circuit 225 includes a filter 223
The signal level of the frequency error amount Δf ₁ output from is detected, and this signal level is compared with a predetermined threshold th. Then, the comparison result is supplied to the timing control circuit 221.

The frequency error Δf ₁ output from the filter 223 is input to the NCO 224. NCO224
Outputs a frequency error correction signal theta ₁ on the basis of the frequency error amount Delta] f _1.

Specifically, the NCO 224 includes a first accumulator 231 and a second accumulator 232, as shown in FIG.
And an AND circuit 233.

The first accumulator 231 includes an adder 235
And a register 236. Adder 235
Is the frequency error Δf ₁ input from the filter 223
And the value stored in the register 236. Register 236 updates the stored value with the result of the addition. The first accumulator 231 includes the adder 235 and the register 236.
, The frequency error amount Δf _{1 for} each symbol clock
Is cumulatively added. By cumulatively adding the frequency error amount Δf ₁ in this manner, the register 236 stores the frequency correction amount f _{1 at} that time. The first accumulator 231 supplies the frequency correction amount f ₁ at that time stored in the register 236 to the second accumulator 232.

The second accumulator 232 includes an adder 237
And a register 238. Adder 237
Calculates the addition of the frequency correction amount f ₁ input from the first accumulator 231 and the value stored in the register 238. Register 238 updates the stored value with the addition result. The second accumulator 232 includes the adder 237 and the register 2
38, the frequency correction amount f for each symbol clock
Performs cumulative addition of ₁ . By cumulatively adding the frequency correction amount f ₁ in this way, the register 238 stores the phase correction amount θ _{1 at} that time. The second accumulator 232 stores the value stored in the register 238,
The phase correction amount theta ₁ at that time as a frequency error correction signal theta ₁ supplied to the first subtracter 203.

Here, the AND circuit 223 performs an AND operation on the frequency synchronization information update flag supplied from the timing control circuit 221 and the inverted signal of the synchronization probability flag. Register 2 of first accumulator 231 of NCO 224
36 (a register storing the frequency correction amount f ₁ at that time) indicates that the output signal of the AND circuit 223 is
Input as an enable signal. That is, in this register 236, the synchronization establishment flag is invalid (0) (that is, the state where frequency synchronization is not established: the pull-in state), and the frequency synchronization information update flag is valid (1). Only update the internal data when.

Therefore, before the synchronization is established (synchronous pull-in state), the updating of the oscillation frequency of the frequency error correction signal θ ₁ output from the NCO 224 is performed by TAB, TMC.
C, only at the burst position, at other positions,
The last oscillation frequency is kept. In other words, performs intermittent operation of changing the oscillation frequency of the frequency error correction signal theta ₁ only for the symbols that are modulated by BPSK.

After the synchronization is established, the NCO 224
Frequency error correction signal θ output from ₁Update of the oscillation frequency
The last oscillation frequency at the time of synchronization establishment is not
The Rukoto.

That is, when the frequency synchronization of the carrier is established, the averaged frequency error Δf ₁ output from the filter 223 becomes smaller than a certain value, and when the synchronization is completely established, it becomes theoretically 0. Become. Therefore, the output value of a certain filter 223 is compared with a certain threshold th, and when the output value is smaller than the threshold th, it is determined that the frequency synchronization has been established, and the establishment of the synchronization is detected. When the frequency synchronization of the carrier wave is established, it holds the oscillation frequency of the frequency error correction signal theta ₁ at a constant value, to stabilize.

After the synchronization is established (synchronous holding state),
Detecting the output of the filter 223, if greater than the threshold th ₂ filter output is, determines that the desynchronization, the synchronization establishment flag as invalid (0), and starts again synchronization pull-in operation. Here, the threshold th used in the synchronization holding state
₂ is set to a value larger than the threshold value th used at the time of synchronization pull-in, so as to provide resistance to loss of synchronization.

Such control for changing the threshold between synchronization pull-in and synchronization holding to perform synchronization protection is performed, for example, as shown in FIG.
This can be performed by a state machine as shown in FIG.

The state machine performs control in states 1 to 3 indicating a synchronization pull-in state and states 4 to 6 indicating a synchronization holding state.

Hereinafter, each state of the state machine will be described.

The following state machine is represented by Δf ₁
Is compared with the threshold th, and a state transition is performed based on the result. As the self-time interval for performing the transition, an appropriate section is set as a measurement section of Δf ₁ .

When a reset signal is input, synchronization pull-in starts, and the state transits to state 1.

Subsequently, in state 1, the filter output Δ
and f _1, it is compared with the threshold th. As a result of the comparison, if the filter output Δf ₁ is smaller than the threshold th, the state transits to the state 2. If the comparison shows that the filter output Δf ₁ is equal to or larger than the threshold th, the state 1 is maintained. In this state 1, the synchronization establishment flag is invalid (0).

Subsequently, in state 2, the filter output Δ
comparing the f ₁ and threshold value th. As a result of the comparison, if the filter output Δf ₁ is smaller than the threshold th, the state transits to state 3. If the comparison shows that the filter output Δf ₁ is equal to or larger than the threshold th, the state transits to state 1. In this state 2, the synchronization establishment flag is invalid (0).

Subsequently, in state 3, the filter output Δ
and f _1, it is compared with the threshold th. As a result of the comparison, if the filter output Δf ₁ is smaller than the threshold th, the state transits to state 4. If the result of comparison shows that the filter output Δf ₁ is equal to or larger than the threshold th, the state transits to state 1. Here, when transitioning to state 4, the synchronization establishment flag is set to valid (0).

That is, it is determined that synchronization has been established only when the filter output Δf ₁ is smaller than the threshold th for three consecutive times. As a result, it is possible to eliminate a pull-in mistake caused by accidentally causing the filter output Δf _{1 to} be smaller than the threshold value th.

Subsequently, in state 4 of the synchronization protection state, the filter output Δf ₁ is compared with the threshold value th2. As a result of the comparison, if the filter output Δf ₁ is equal to or larger than the threshold th, the state transits to state 5. If the result of comparison shows that the filter output Δf ₁ is smaller than the threshold th2, state 4 is maintained. In this state 4, the synchronization establishment flag is set to valid (1).

Subsequently, in the synchronization protection state 5, the filter output Δf ₁ is compared with the threshold value th2. As a result of the comparison, if the filter output Δf ₁ is equal to or more than the threshold th, the state transits to state 6. If the result of the comparison shows that the filter output Δf ₁ is smaller than the threshold th2, the state transits to state 4. In this state 5, the synchronization establishment flag is set to valid (1).

Subsequently, in the state 6 of the synchronization protection state, the filter output Δf ₁ is compared with the threshold value th2. As a result of the comparison, if the filter output Δf ₁ is equal to or larger than the threshold th2, the state transits to state 1. If the result of the comparison shows that the filter output Δf ₁ is smaller than the threshold th, the state transits to state 4. Here, when transitioning to state 1, the synchronization establishment flag is set to invalid (0).

That is, it is determined that synchronization has been lost only when the filter output Δf ₁ is smaller than the threshold value th2 three times in succession. As a result, it is possible to eliminate a mistake that the synchronization is lost because the filter output Δf ₁ is larger than the threshold value th2 by accident.

Although the third embodiment is a modification of the internal structure of the frequency synchronization unit of the demodulation unit 201 of the second embodiment, the frequency synchronization unit described here is replaced by the first. It can also be applied to the embodiment. In this case, a rectangular coordinate conversion circuit is provided at the last stage of the NCO 224,
What is necessary is just to generate the frequency error correction signal of the rectangular coordinate signal.

Fourth Embodiment A BS digital broadcast receiving apparatus according to a fourth embodiment of the present invention will be described.

Note that the fourth embodiment is different from the third embodiment only in the internal configuration of the NCO of the frequency synchronization section of the demodulation section 201. Therefore, in the fourth embodiment, only the NCO will be described in detail.

As shown in FIG. 16, the NCO 250 includes an adder 251, a sweep circuit 252, and a selector 253.
, Register 254, accumulator 255, and OR circuit 2
56.

The adder 251 performs an addition operation on the averaged frequency error Δf ₁ and the value stored in the register 254.
The result of the addition operation is supplied to the selector 253.

The sweep circuit 252 is a circuit that generates a sweep signal whose value simply increases (or decreases) over time. The sweep circuit 252 outputs a frequency sweep signal dF when pulling in frequency synchronization.
The sweep circuit 252 increases the signal level of the frequency sweep signal dF, and stops the output when synchronization is established. The frequency sweep signal dF generated from the sweep circuit 252 is supplied to the selector 253.

The selector 253 selectively switches between the output value from the adder 251 and the frequency sweep signal dF from the sweep circuit 252, and supplies them to the register 254. The selector 253 performs switching control according to the synchronization establishment flag output from the timing control circuit 221. When the synchronization establishment flag is invalid (0) (that is, when the synchronization is established), the selector 253 outputs
The frequency sweep signal dF from the sweep circuit 252 is supplied to the register 254. On the other hand, the selector 253 supplies the output of the adder 251 to the register 254 when the synchronization establishment flag is valid (1) (that is, in the synchronization holding state).

The register 254 stores the frequency sweep signal dF output from the sweep circuit 252 in the synchronization pull-in state. Also, register 2
Numeral 54 stores the frequency error amount Δf ₁ cumulatively added for each symbol clock in the synchronization holding state, and outputs the frequency correction amount f ₁ at that time obtained as a result of cumulatively adding the frequency error amount Δf _1. Will be done.

It is to be noted that the register 254 is provided in the OR circuit 2
56 output signals are provided as enable signals. O
The R circuit 256 is a circuit that performs an OR operation on the inverted signal of the synchronization establishment flag and the frequency synchronization information update flag. Therefore, when the synchronization establishment flag is invalid (0) (synchronization pull-in state), the register 254 always updates the internal data. On the other hand, when the synchronization establishment flag is valid (1) (synchronization protection state), the internal data is updated only when the frequency synchronization information update flag is valid (1). Therefore, at the time of synchronization protection, updating is the frequency error correction signal theta ₁ of the oscillation frequency output from NCO224 is, TAB, TMCC, occur only at the burst position, and in the other position, the end of the oscillation frequency is held You. In other words, performs intermittent operation of changing the oscillation frequency of the frequency error correction signal theta ₁ only for the symbols that are modulated by BPSK.

The second accumulator 255 includes an adder 257
And a register 258. In the second accumulator 255, the adder 237 performs an addition operation on the input frequency correction amount f ₁ (or the frequency sweep signal dF) and the value stored in the register 238, and the addition result is stored in the register 238.
The cumulative addition of the frequency correction amount f ₁ (or the frequency sweep signal dF) is performed for each symbol clock. The second accumulator 255 outputs the phase correction amount θ ₁ at that time by cumulatively adding the frequency correction amount f ₁ (or the frequency sweep signal dF). The second accumulator 232 uses this phase correction amount θ ₁ as the frequency error correction signal θ ₁
03.

The operation of sweep circuit 252 will be described with reference to the flowchart shown in FIG.

First, when the reception of the BS digital broadcast or the like is started and the frequency synchronization of the carrier is started, a sweep start command is input to the sweep circuit 252 from the outside (step S11). At this time, the synchronization establishment flag is
It is invalid (0), and the selector 253 has selected the sweep circuit 253.

Subsequently, the sweep circuit 252 sets the value of the frequency sweep signal dF to an initial value (step S1).
2).

Subsequently, sweep circuit 252 generates sweep signal dF of the set signal level, and waits for processing for a predetermined standby time (step S13).

Subsequently, after the elapse of the standby time, the sweep circuit 252 determines whether or not synchronization has been established with reference to the synchronization establishment flag. If frequency synchronization is achieved at the generated signal level, the output Δf _{1 of the} filter 223 is output.
Becomes smaller than the threshold th, and the timing control circuit 2
21 sets the synchronization establishment flag to valid (1). Conversely, if frequency synchronization is not established at the generated signal level, the output Δf _{1 of the} filter 223 becomes equal to or greater than the threshold th, and the timing control circuit 221 invalidates the synchronization establishment flag (0).
And keep it.

If the synchronization is not established, the sweep circuit 252 further adds a predetermined step value (dFstep) to the value of the frequency sweep signal dF (Step S).
15) The process from step S13 is repeated again until synchronization is established.

Then, when synchronization is established, sweep circuit 15 stops outputting frequency sweep signal dF. At this time, the synchronization establishment flag is set to valid (1),
The selector 253 selects the adder 251.

According to the fourth embodiment of the present invention, when pulling in the frequency synchronization of the carrier, the frequency error correction signal θ ₁ is set to a predetermined frequency range based on the frequency sweep signal dF generated from the sweep circuit 252. Sweep between. At each stage of the sweep, the frequency error amount Δf ₁ of the carrier is detected, and whether this frequency error amount Δf ₁ is smaller than a predetermined threshold value is determined to determine whether frequency synchronization has been established. I do. Subsequently, when the frequency synchronization is established, the selector 253 is switched, the register 250 and the adder 251 form a cumulative adder, and a synchronous loop is formed. When forming a synchronous loop by forming the accumulator, the sweep value latched in the register 254 is fed back to the adder 251 as it is, and the transition from the synchronization pull-in to the synchronization holding operation is performed.

As described above, in the fourth embodiment, the frequency synchronization correction operation can be performed at high speed by sweeping the frequency error correction signal θ ₁ when the frequency synchronization is performed.

Although the fourth embodiment is a modification of the internal configuration of the NCO of the frequency synchronization section of the demodulation section 201 of the third embodiment, it is applied to the first embodiment. You can also. In this case, a rectangular coordinate conversion circuit may be provided at the last stage of the NCO 224 to generate a frequency error correction signal of the rectangular coordinate signal.

In the fourth embodiment, the frequency error correction signal θ ₁ is swept to form a synchronous loop after synchronization is established. However, after the synchronization is established, the sweep is stopped and the established state is changed. to hold (i.e., to keep remain fixed frequency error correction signal theta ₁₎ it may be. In this case, the state of the synchronization loss is constantly monitored, and when the synchronization is lost, the sweep circuit 252 is operated again to repeat the operation from the synchronization pull-in.

Fifth Embodiment Next, a BS digital broadcast receiving apparatus according to a fifth embodiment of the present invention will be described.

The fifth embodiment is different from the second embodiment only in the internal structure of the frequency synchronization section and the phase synchronization section of the demodulation section 201. Therefore, in the fifth embodiment, only the frequency synchronization unit and the phase synchronization unit will be described in detail.

First, the frequency synchronization section will be described.

As shown in FIG. 18, the frequency synchronization section 270 includes a timing control circuit 271, a frequency error detection circuit 272, a filter 273, an NCO 274, and a level detection circuit 275.

The timing control circuit 271 receives a frame start flag (FST flag) from the frame synchronization circuit 208. The timing control circuit 271 counts the number of symbols from the FST flag, thereby obtaining the TMCC data, the TAB signal (synchronization word),
The symbol timing that specifies that BPSK modulation is always performed in BS digital broadcasting such as a burst signal is specified. The timing control circuit 271 determines that the symbol is T
A frequency synchronization information update flag that specifies the position of the MCC data, the TAB signal, and the burst signal is generated and supplied to the filter 273 and the NCO 274. Further, the timing control circuit 271 determines whether or not the frequency synchronization of the carrier is established based on the comparison result from the level detection circuit 275, and when it is determined that the frequency synchronization is established, the synchronization establishment flag which becomes valid (1) Generate The timing control circuit 271 supplies a synchronization establishment flag to the filter 273.

The frequency error component Δf ₁ included in the transmission data θ ′ as the angle data output from the first subtractor 203 is detected. Detected frequency error Δ
f ₁ is supplied to the filter 273.

The filter 273 is, for example, an IIR (Infini
It is composed of a loop filter such as a te Impulse Response filter and has the characteristics of an LPF (Low pass filter). The filter 273 receives the frequency error Δf ₁ from the frequency error detection circuit 272, averages the input frequency error Δf ₁ , and outputs the result.

The level detection circuit 275 includes a filter 273
Averaged to detect the level of the frequency error amount Delta] f ₁ is outputted from the two, the frequency error amount Delta] f ₁ with a predetermined threshold value t
h. Then, the comparison result is supplied to the timing control circuit 271.

The NCO 274 receives the averaged frequency error Δf ₁ from the filter 273 and outputs a frequency error correction signal θ ₁ based on the frequency error Δf ₁ .
The configuration of the NCO 274 is the same as that of the second embodiment.

Next, the filter 273 will be further described.

As shown in FIG. 19, the filter 273
First multiplier 2 for multiplying frequency error Δf ₁ by gain G
81, a second multiplier 282 for multiplying the frequency error Δf ₁ by a coefficient K for determining a band, a third multiplier 283 for multiplying the filter output by a coefficient (1−K), and a second multiplication. An adder 284 that adds the output of the adder 282 and the output of the third multiplier 283, and a register 285 that delays the output of the adder 284. The filter 273 having such a configuration loop-filters the input frequency error amount Δf ₁ with the coefficient K and the gain G, and outputs the averaged frequency error amount Δf ₁ from the register 285.

Here, the filter 273 is used such that the values of the gain G and the coefficient K for determining the band are switched between when synchronizing and when synchronizing. For example, as shown in FIG. 19, selectors 286 and 287 for switching between G and K according to the synchronization probability flag are provided. The filter 273 sets the frequency characteristic of the filter to a low gain and a wide band when pulling in the synchronization, and sets the frequency characteristic of the filter to a high gain and a narrow band when the synchronization is maintained. That is, if the coefficients at the time of synchronization pull-in are G ₁ and K ₁ and the coefficients at the time of synchronization hold are G ₂ and K ₂ , the following relationship is set. K ₁ > K ₂ , G ₁ <G ₂ As a result, it is possible to shorten the time until the synchronization is pulled in at the time of synchronization pull-in, and to secure the stability of synchronization at the time of synchronization holding.

The register 285 holding the frequency error amount Δf ₁ averaged at that time receives the frequency synchronization information update flag supplied from the timing control circuit 141 as an enable signal, and the frequency synchronization information update flag is valid. Updating the internal data only when (1) is set is the same as in the second embodiment.

Next, the phase synchronization section will be described.

As shown in FIG. 20, the phase synchronization section 291 includes a timing control circuit 291 and a phase error detection circuit 2.
92, a filter 293, an NCO 294, and a level detection circuit 295.

The timing control circuit 291 receives a frame start flag (FST flag) from the frame synchronization circuit 208. The timing control circuit 291 counts the number of symbols from the FST flag, thereby obtaining the TMCC data, the TAB signal (synchronization word),
The symbol timing that specifies that BPSK modulation is always performed in BS digital broadcasting such as a burst signal is specified. The timing control circuit 291 determines that the symbol is T
Generates a BPSK flag that is valid (1) when it is an MCC data, a TAB signal, or a burst signal.
93 and NCO 294. Further, the timing control circuit 291 determines whether or not the frequency synchronization of the carrier is established based on the comparison result from the level detection circuit 295, and is effective when it is determined that the frequency synchronization is established (1).
A synchronization establishment flag is generated. The timing control circuit 291 supplies a synchronization establishment flag to the filter 293.

The phase error Δθ ₂ included in the transmission data θ ″ which is the angle data output from the second subtractor 205 is detected. The detected phase error Δθ ₂ is
It is supplied to the filter 293.

The filter 293 is, for example, an IIR (Infini
It is composed of a loop filter such as a te Impulse Response filter and has the characteristics of an LPF (Low pass filter). The filter 293 receives the phase error amount Δθ ₂ from the phase error detection circuit 292, averages the input phase error amount Δθ ₂ , and outputs the result.

The level detection circuit 295 includes a filter 293
, The level of the averaged phase error amount Δθ ₂ is detected, and the phase error amount Δθ ₂ is compared with a predetermined threshold value. Then, the comparison result is sent to the timing control circuit 2.
91.

The NCO 294 receives the averaged phase error Δθ ₂ from the filter 293 and outputs a phase error correction signal θ ₂ based on the phase error Δθ ₂ . This N
The configuration of the CO 294 is the same as that of the second embodiment.

Here, the filter 293 of this phase synchronization section
In the same manner as in the filter shown in FIG. 19, the values of the gain G and the coefficient K for determining the band are switched between when the synchronization is pulled in and when the synchronization is maintained. The filter 293 sets the frequency characteristic of the filter to low gain and wide band when pulling in the synchronization, and sets the frequency characteristic of the filter to high gain and narrow band when holding the synchronization. That is, the coefficients at the time of synchronization pull-in are G ₁ and K _1, and the coefficients at the time of synchronization hold are G ₂ and K ₂
Then, the setting is made so as to have the following relationship. K ₁ >
K ₂ , G ₁ <G ₂ As a result, it is possible to shorten the time until the synchronization is pulled in at the time of the synchronization pull-in, and to ensure the stability of the synchronization at the time of holding the synchronization.

The filter 27 of the frequency synchronization section 270
3 and the filter 293 of the phase synchronization section 290 have the same circuit configuration, but the values of the gain G and the coefficient K are adaptively determined and different.

[0230]

In the digital satellite broadcast demodulating apparatus and method according to the present invention, the synchronization processing of the symbol timing of the transmission data is performed, the frame synchronization timing of the transmission data is detected, and based on the frame synchronization timing, at least the symbol position of the synchronization word , Detecting the carrier frequency error of each symbol of the synchronization word, performing frequency synchronization processing of the carrier, specifying at least the symbol position of the synchronization word based on the frame timing, and determining the carrier phase error of each symbol of the synchronization word. Is detected, and a phase synchronization process of the carrier is performed.

That is, in the digital satellite broadcast demodulating apparatus and method according to the present invention, the carrier synchronization processing is performed after the frame synchronization processing, and the transmission data after the carrier frequency synchronization is performed in the carrier synchronization. , The phase of the carrier is synchronized.

Therefore, according to the present invention, frequency synchronization and phase synchronization of a carrier can be performed with a very simple configuration, and even in the case of digital satellite broadcasting in which the modulation method changes dynamically, QPSK or A signal having a wide phase between signal points is used without using a symbol having a narrow phase between signal points such as 8PSK.
Since the carrier synchronization processing is performed by detecting the PSK modulated symbol, the carrier synchronization processing can be performed with high accuracy.

Further, since phase synchronization is performed on transmission data on which carrier frequency synchronization has been performed, a signal band required for frequency synchronization and a signal band required for phase synchronization can be narrowed. Even in an environment such as a C / N environment where the frequency difference between the transmission frequency of the transmission signal and the frequency of the transmission signal of the local oscillator is large, carrier wave synchronization can be performed reliably and at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a BS digital broadcast receiving apparatus according to a first embodiment.

FIG. 2 is a block diagram of a demodulation unit of the BS digital broadcast receiving apparatus.

FIG. 3 is a diagram for explaining a superframe structure of a BS digital broadcast signal.

FIG. 4 is a diagram for explaining a frame structure of a BS digital broadcast signal.

FIG. 5 is a flowchart showing a synchronization processing procedure of the demodulation unit.

FIG. 6 is a block diagram of a frequency synchronization unit of the demodulation unit.

FIG. 7 is a block diagram of a frequency error detection circuit of the frequency synchronization section.

FIG. 8 is a block diagram of a filter of the frequency synchronization section.

FIG. 9 is a block diagram of an NCO of the frequency synchronization unit.

FIG. 10 is a block diagram of a phase synchronization unit of the demodulation unit.

FIG. 11 is a block diagram of an NCO of the phase synchronization section.

FIG. 12 is a block diagram illustrating a BS digital broadcast receiving apparatus according to a second embodiment.

FIG. 13 is a block diagram of a frequency synchronization unit used in the BS digital broadcast receiving device according to the third embodiment.

FIG. 14 is a block diagram of an NCO of the frequency synchronization unit.

FIG. 15 is a state machine showing a transition of an operation state of the frequency synchronization section.

FIG. 16 is a block diagram of a frequency synchronization unit used in a BS digital broadcast receiving apparatus according to a fourth embodiment.

FIG. 17 is a flowchart showing an operation procedure of a sweep circuit of the frequency synchronization section.

FIG. 18 is a block diagram of a frequency synchronization unit used in a BS digital broadcast receiving apparatus according to a fifth embodiment.

FIG. 19 is a block diagram of a filter of the frequency synchronization section.

FIG. 20 is a block diagram of a phase synchronization unit used in the BS digital broadcast receiving apparatus according to the fifth embodiment.

FIG. 21 is a block diagram showing a general transmission model when digital data is transmitted by performing digital quadrature modulation.

[Explanation of symbols]

101, 201 demodulation unit, 129 first complex multiplier,
130, 220, 270 Frequency synchronizer, 131 second
, 132,290 phase synchronization unit, 133
Timing synchronization unit, 134 frame synchronization unit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C025 AA13 AA30 BA14 BA18 BA25 DA01 DA04 5K004 AA05 AA08 FH08 FJ01 JH05 JJ01 5K047 AA02 AA11 CC01 CC08 EE02 EE04 GG13 GG16 HH01 HH03 HH12 HH43 MM13

Claims (32)

[Claims] 1. A digital satellite broadcast demodulator for demodulating a digital satellite broadcast signal, a timing synchronizing means for synchronizing a symbol timing of transmission data, and detecting a synchronization word from the timing-synchronized transmission data. Frame synchronization means for detecting the frame synchronization timing of the transmission data; identifying at least the symbol position of the synchronization word based on the frame timing; detecting a carrier frequency error of each symbol of the synchronization word; And a carrier phase synchronization unit for identifying at least the symbol position of the synchronization word based on the frame timing, detecting a carrier phase error of each symbol of the synchronization word, and performing a phase synchronization process of the carrier. Wherein the carrier phase synchronization means comprises: For the transmission data after the frequency synchronization of the carrier is by the wave frequency synchronization unit, a digital satellite broadcast demodulating apparatus comprising performing the phase synchronization of the carrier. 2. The frame synchronization means detects difference data between symbols of the transmission data, and correlates the difference data of the transmission data with the difference data of the synchronization word.
2. The digital satellite broadcast demodulator according to claim 1, wherein a frame synchronization timing of transmission data is detected. 3. The carrier frequency synchronizing means includes: a correction unit that corrects a carrier frequency error component of the transmission data based on a frequency error correction signal; and a carrier wave that detects a carrier frequency error of the transmission data output from the correction unit. A frequency error detection unit, a filter unit for filtering the carrier frequency error detected by the carrier frequency error detection unit, and a numerical control oscillator for generating a frequency error correction signal whose oscillation frequency changes according to the filtered carrier frequency error 2. The digital satellite broadcast demodulator according to claim 1, comprising: 4. The carrier frequency synchronizing means includes a timing control section for specifying at least a symbol position of a synchronization word based on the frame timing, and the filter section includes a symbol position of the synchronization word specified by the timing control section. Then, a filtering operation is performed, and at other symbol positions, an intermittent operation of holding the last filter output value is performed. At the symbol position of the synchronization word specified by the timing control unit, the carrier frequency 4. The digital satellite broadcast demodulator according to claim 3, wherein the oscillation frequency is varied in accordance with the error, and an intermittent operation for holding the last frequency is performed at other symbol positions. 5. The correction unit of the carrier frequency synchronization means,
4. The digital satellite broadcast demodulation according to claim 3, wherein the carrier data frequency error component is corrected by complexly multiplying the transmission data converted into the rectangular coordinate signal by the frequency error correction signal converted into the rectangular coordinate signal. apparatus. 6. The correction unit of the carrier frequency synchronization means,
The digital satellite broadcast demodulator according to claim 3, wherein the carrier frequency error component is corrected by subtracting the frequency error correction signal, which is a phase signal, from the transmission data, which is a phase signal. 7. The carrier wave phase synchronizing means includes: a compensating unit for compensating transmission data after carrier frequency synchronization by the carrier frequency synchronizing means based on a phase error compensation signal; A carrier phase error detector for detecting a carrier phase error of transmission data, a filter for filtering the carrier phase error detected by the carrier phase error detector, a phase whose phase changes according to the filtered carrier phase error 2. The digital satellite broadcast demodulator according to claim 1, further comprising a numerically controlled oscillator that generates an error correction signal. 8. The carrier phase synchronizing means includes a timing control unit for specifying at least a symbol position of a synchronization word based on the frame timing, and the filter unit includes a symbol position of the synchronization word specified by the timing control unit. 8. The digital satellite broadcast demodulator according to claim 7, wherein a filtering operation is performed, and an intermittent operation for holding a last filter output value is performed at other symbol positions. 9. The correction unit of the carrier phase synchronization unit performs complex multiplication of transmission data, which is a rectangular coordinate signal, with a phase error correction signal, which is a rectangular coordinate signal,
The digital satellite broadcast demodulator according to claim 7, wherein the carrier phase error component is corrected. 10. The correction unit of the carrier phase synchronization means,
8. The digital satellite broadcast demodulator according to claim 7, wherein the carrier phase error component is corrected by subtracting the phase error correction signal, which is a phase signal, from the transmission data, which is a phase signal. 11. The carrier frequency synchronizing means performs frequency correction of a carrier of the digital orthogonal signal by fixing a correction amount in a state where synchronization is established after frequency synchronization is established. The digital satellite broadcast demodulator according to the above. 12. The carrier frequency synchronizing means sweeps a phase error correction signal when pulling in frequency synchronization, and establishes frequency synchronization based on a carrier frequency error that changes according to the sweep. The digital satellite broadcast demodulator according to the above. 13. The carrier frequency synchronizing means has a frequency characteristic control unit for controlling a frequency characteristic of a carrier frequency locked loop.
2. The digital satellite broadcast demodulator according to claim 1, wherein the frequency characteristic is set to a low gain and / or a wide band, and when frequency synchronization is established, the frequency characteristic is set to a high gain and / or a narrow band. 14. The carrier phase synchronization means has a frequency characteristic control unit for controlling a frequency characteristic of a carrier phase locked loop, and the frequency characteristic control unit reduces the frequency characteristic to low gain and / or 2. The digital satellite broadcast demodulator according to claim 1, wherein the frequency characteristic is set to a high gain and / or a narrow band when phase synchronization is established. 15. The state control wherein the carrier frequency synchronization means sets a synchronization established state when the carrier frequency error component is lower than a predetermined threshold, and sets a synchronization pull-in state when the carrier frequency error component is higher than a predetermined threshold. Carrier phase synchronization means performs synchronization control using the state machine that performs the above-mentioned, if the carrier phase error component is lower than a predetermined threshold, the synchronization establishment state, if the carrier phase error component is higher than a predetermined threshold, 2. The digital satellite broadcast demodulator according to claim 1, wherein synchronization control is performed using a state machine that performs state control for setting an out-of-synchronization state. 16. The carrier frequency synchronizing means and the carrier phase synchronizing means perform control by each state machine by setting a threshold value in a synchronization pull-in state lower than a threshold value in a synchronization established state. The digital satellite broadcast demodulator according to claim 15. 17. A digital satellite broadcasting demodulation method for demodulating a broadcast signal of digital satellite broadcasting, wherein a synchronization process of symbol timing of transmission data is performed, a synchronization word is detected from the transmission data synchronized in timing, and the transmission data is detected. The frame synchronization timing is detected, the symbol position of at least the synchronization word is specified based on the frame timing, the carrier frequency error of each symbol of the synchronization word is detected, the carrier frequency synchronization process is performed, and the carrier frequency synchronization process is performed. In the transmission data after the above, the symbol position of at least the synchronization word is specified based on the frame timing, the carrier phase error of each symbol of the synchronization word is detected, and the phase synchronization of the carrier is performed. Digital satellite broadcast demodulation method. 18. A method of detecting difference data between symbols of transmission data and detecting a frame synchronization timing of the transmission data by correlating the difference data of the transmission data with the difference data of a synchronization word. The digital satellite broadcast demodulation method according to claim 17. 19. In the carrier frequency synchronization process, a carrier frequency error component of the transmission data is corrected based on a frequency error correction signal, and a carrier frequency error of the transmission data corrected based on the frequency error correction signal is detected. 18. The digital satellite broadcast demodulation method according to claim 17, wherein the detected carrier frequency error is filtered, and a frequency error correction signal whose oscillation frequency changes according to the filtered carrier frequency error is generated. 20. In the carrier frequency synchronization, at least a symbol position of a synchronization word is specified based on the frame timing, a filtering operation is performed at the symbol position of the specified synchronization word, and a final filter output is performed at other symbol positions. By holding the value, an intermittent filtering operation is performed, the oscillation frequency is changed according to the carrier frequency error at the symbol position of the characteristic synchronization word, and the last frequency is held at other symbol positions. 20. The digital satellite broadcast demodulation method according to claim 19, wherein a frequency control operation of the frequency error correction signal is performed intermittently. 21. A carrier frequency error component is corrected by complexly multiplying a transmission data set as a rectangular coordinate signal by a frequency error correction signal set as a rectangular coordinate signal. Digital satellite broadcasting demodulation method. 22. The digital satellite broadcast demodulation according to claim 19, wherein the carrier frequency error component is corrected by subtracting the frequency error correction signal converted to the phase signal from the transmission data converted to the phase signal. Method. 23. A carrier wave phase synchronization process, wherein the carrier phase error component of the transmission data after the carrier frequency synchronization is corrected based on a phase error correction signal, and the transmission corrected based on the phase error correction signal. A carrier phase error detection unit for detecting a carrier phase error of the data; and a phase error correction signal for changing a phase according to the filtered carrier phase error by filtering the detected carrier phase error. Item 18. The digital satellite broadcast demodulation method according to Item 17. 24. The carrier phase synchronization means for specifying at least a symbol position of a synchronization word based on the frame timing, performing a filtering operation at a symbol position of the specified synchronization word, and performing a last filtering at other symbol positions. The digital satellite broadcast demodulation method according to claim 23, wherein an intermittent filtering operation is performed by holding the output value. 25. A carrier wave phase error component is corrected by complexly multiplying transmission data converted into a rectangular coordinate signal by a phase error correction signal converted into a rectangular coordinate signal. Digital satellite broadcasting demodulation method. 26. The digital satellite broadcast demodulation according to claim 23, wherein the carrier phase error component is corrected by subtracting the phase error correction signal, which is a phase signal, from the transmission data, which is a phase signal. Method. 27. The digital satellite broadcast demodulation method according to claim 17, wherein after the frequency synchronization is established, the correction amount of the state in which the synchronization is established is fixed to perform the frequency correction of the carrier of the digital orthogonal signal. . 28. The digital satellite broadcast demodulation method according to claim 17, wherein at the time of pulling in the frequency synchronization, the phase error correction signal is swept, and the frequency synchronization is established based on a carrier frequency error that changes according to the sweep. . 29. The frequency characteristic of a carrier frequency locked loop is set to a low gain and / or a wide band when frequency synchronization is pulled in, and the frequency characteristic is set to a high gain and / or a narrow band when frequency synchronization is established. Item 18. The digital satellite broadcast demodulation method according to Item 17. 30. The frequency characteristic of the carrier frequency locked loop is set to a low gain and / or a wide band when phase locking is performed, and the frequency characteristic is set to a high gain and / or a narrow band when phase synchronization is established. Item 18. The digital satellite broadcast demodulation method according to Item 17. 31. A state control in which, in the carrier frequency synchronization processing, if the carrier frequency error component is lower than a predetermined threshold, a synchronization is established, and if the carrier frequency error component is higher than a predetermined threshold, a synchronization pull-in state is set. Performing synchronization control using a state machine that performs the above, in the carrier phase synchronization process, if the carrier phase error component is lower than a predetermined threshold, the synchronization is established, if the carrier phase error component is higher than a predetermined threshold 18. The digital satellite broadcast demodulation method according to claim 17, wherein synchronization control is performed by using a state machine that performs state control for setting an out-of-synchronization state. 32. In the carrier frequency synchronization process and the carrier phase synchronization process, the threshold value in the synchronization established state is
32. The digital satellite broadcast demodulation method according to claim 31, wherein the control in each state machine is performed by lowering the threshold value in the synchronization pull-in state.